Search

Forthcoming infrared event-based sensors will have utility in the space-based surveillance domain where they could potentially perform traditional sensing and tracking functions with significantly enhanced temporal resolution and reduced downstream datalink demands and power consumption. As a first step toward extending event-based sensing technology into the mid-wave infrared, a DC simulation of the conventional event-based sensor unit cell's photoreceptor circuit is performed, and the results are compared with measurements of a printed circuit board implementation of the same circuit to assess what design freedom is available to interface the photoreceptor with a mid-wave infrared photodetector. Detailed analysis of the circuit and measurements provides insight into which fundamental properties of the transistors drive the photoreceptor's dynamic range and demonstrates several characteristics that are relevant to mid-wave infrared sensing. These characteristics include the capability to produce a stable, low voltage bias on the infrared photodetector to maximize sensitivity, and that operating the circuit below room temperature increases the photoreceptor's dynamic range. Measurements show that even the simplest implementation of the photoreceptor circuit exhibits a dynamic range of logarithmic compression of 150 dB at room temperature. However, the dynamic range is ultimately limited by the mid-wave infrared photodetector's dark current activation energy, which is significantly lower than the threshold voltage (energy) of the photoreceptor's feedback transistor and, thus, there is an incentive for the photodetector's dark current to be diffusion-limited. [ABSTRACT FROM AUTHOR]

We have performed a small-signal admittance analysis to extract trap parameters in an AlGaN/GaN high electron mobility transistor-on-Si. Whereas the admittance in the accumulation- and depletion-bias regimes is primarily due to the interface traps, the admittance near the threshold voltage and below is due to mono-energetic traps inside GaN. The density extracted for threading dislocation-related 1D traps at ≈ 0.22 eV below the GaN conduction band edge is similar to that previously reported by reverse-biased gate leakage analysis of the analyzed device. Our analysis suggests additional 1D traps of comparatively lower density ≈ 4 × 10 14 cm − 3 but considerably large capture cross section ≈ 8 × 10 − 14 cm 2 in the GaN layer at ≈ 0.31 eV below the conduction band. The AlGaN trap density is considerably larger near the AlGaN/GaN interface than in the bulk AlGaN. The AlGaN traps mainly contribute to the voltage stretch; their admittance contribution is negligible. Gate leakage dominates the conductance at lower frequencies. [ABSTRACT FROM AUTHOR]

The Bernards–Malliaras model, published in 2007, is the primary reference for the operation of organic electrochemical transistors (OECTs). It assumes that, as in most transistors, the electronic transport is drift only. However, in other electrochemical devices, such as batteries, the charge neutrality is accompanied by diffusion-only transport. Using detailed 2D device simulations of the entire structure while accounting for ionic and electronic conduction, we show that high ion density (>1019 cm−3) results in Debye screening of the drain–source bias at the electrodes' interface. Hence, unlike the drift-only current in standard FETs or low ion density OECTs, the current in high ion density OECTs is diffusion only. Also, we show that since in OECTs, the volumetric capacitor and the semiconductor are one, the threshold voltage has a different meaning than that in FETs, where the semiconductor and the gate-oxide capacitor are distinct entities. We use the above insights to derive a new model useful to experimentalists. Lastly, we fabricated PEDOT:PSS fiber-OECTs and used the results to verify the model. [ABSTRACT FROM AUTHOR]

In this paper, the p-GaN gate AlGaN/GaN high electron mobility transistors (HEMTs) with varying combinations of gate metal work function and gate geometry are fabricated and investigate the influence of gate leakage current (IGS) on the threshold voltage (VTH) and subthreshold swing (SS). The unique dependence of VTH and SS on gate geometry for different metals is observed, which is different from traditional field-effect transistors. A novel hybrid physics model, consisting of the traditional capacitance divider model and hole injection model, is proposed to explain this phenomenon, and the results exhibit an excellent agreement with the experimental data. The holes traverse the gate/p-GaN Schottky barrier by thermal emission or tunneling and inject into the p-GaN layer, generating the IGS. Expanding upon the traditional capacitance divider model, a portion of the injected holes accumulate at the p-GaN/AlGaN interface and induce the corresponding electrons at the AlGaN/GaN heterojunction, which promotes channel conduction. Hence, the transfer curves display the correlation between IGS and VTH as well as SS. The results show that high IGS can alleviate the instability of VTH caused by the lithographic overlay error, and simultaneously optimize SS. This work offers a novel perspective for examining the turn-on mechanism of p-GaN HEMTs, thereby contributing to device design. [ABSTRACT FROM AUTHOR]

A comprehensive quantitative root cause study of defect evolution leading to memory window closure from a charge balance and charge trapping perspective throughout all phases of a Si channel Hf0.5Zr0.5O2 (HZO) ferroelectric field-effect-transistor (FEFET) is reported. Starting with the first write pulse, an excessive SiO2 interlayer field is revealed that triggers the creation of defect levels Dit in excess of 1015 cm−2 eV−1 at the HZO–SiO2 interface screening ferroelectric (FE) polarization while enabling FE switching. Under subsequent early bipolar fatigue cycling (up to 104 cycles), defect creation commences at the SiO2–Si interface due to the high injected hole fluence (0.39 C/m2) during each stress pulse causing negative bias instability (NBI), which shifts the threshold voltage of the erase state VT,ERS by −0.3 V with accrual of permanently captured charge Nit of up to +5 × 10−3 C/m2 (3 × 1012 cm−2). Subsequently, Nit NBI generation at the SiO2–Si interface accelerates reaching levels of +7 × 10−2 C/m2, locking both FEFET program and erase drain current vs gate–source-voltage (ID–VGS) characteristics in the FEFET on-state inducing memory window closure at 105 cycles while FE switching (switched polarization Psw = 0.34 C/m2) remains essentially intact. These findings guide the down-selection toward suitable semiconductor/FE systems for charge balanced, reliable, and high endurance FEFETs. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate a hydrogen-terminated diamond (H-diamond) field-effect transistor (FET) with Al2O3/CeB6 gate materials. The CeB6 and Al2O3 films have been deposited by electron beam evaporation technique, sequentially. For the 4/8/12/15 μm gate length (LG) devices, the whole devices demonstrate distinct p-type normally off characteristics, and all the threshold voltage are negative; all the absolute values of leakage current density are 10−4 A/cm2 at a VGS of −11 V, exhibiting a relatively low leakage current density compared with CeB6 FETs, and this further demonstrates the feasibility of the introduction of Al2O3 to reduce the leakage current density; the maximum drain–source current density is −114.6, −96.0, −80.9, and −73.7 mA/mm, which may be benefited from the well-protected channel. For the 12 μm LG devices, the saturation carrier mobility is 593.6 cm2/V s, demonstrating a good channel transport characteristic. This work may provide a promising strategy for the application of normally off H-diamond FETs significantly. [ABSTRACT FROM AUTHOR]

In this work, bottom-Schottky-structure InGaZnOx (IGZO) Schottky barrier diodes (SBDs) with sputtered PtOx anodes were fabricated and annealed in oxygen at different temperatures. Critical parameters and negative bias stress (NBS) stability of SBDs with different annealing temperatures are investigated. With the annealing temperature increases, the barrier height and rectification ratio of the SBDs exhibited a rising-then-declining trend, while the ideality factor slightly increased until 200 °C. The SBDs show up overall reliability except for a leakage current rising trend under light, which can be attributed to free electron generation from the ionized oxygen vacancy. Among all the SBDs, the 175 °C annealed ones exhibited the best overall performance, including a high barrier height of 0.89 eV, an ideality factor of 1.14, and a large rectification ratio of over 108. Compared to the initial SBDs, the annealed ones showed up great improvement in NBS stability except for the 200 °C annealed ones, which was permanently degraded and not able to recover to original states. According to experimental result analysis and IGZO material characteristics, a stability model based on the subgap trap transition from V O 2 + to VO and new V O 2 + creation was proposed, which applies to both the short-term and long-term NBS tests. The results above demonstrate that oxygen annealing at appropriate temperature is an effective method to improve both device performance and NBS stability for PtOx–IGZO SBDs. [ABSTRACT FROM AUTHOR]

In this work, three atomic layer deposition (ALD) approaches are used to deposit an Al2O3 gate insulator on n-GaN for application in vertical GaN power switches: thermal ALD (ThALD), plasma-enhanced ALD (PEALD), and their stacked combination. The latter is a novel method to yield the most ideal insulating layer. Also, the influence of an in situ NH3 or H2 plasma pre-treatment is studied. Planar MIS capacitors are used to investigate the electrical properties and robustness of the gate insulators. In vacuo x-ray photoelectron spectroscopy (XPS) is used to study the changes in chemical composition after every surface treatment. XPS shows that all plasma pre-treatments efficiently remove all carbon contamination from the surface, but only NH3 plasma is observed to additionally remove the native oxide from the n-GaN surface. The water precursor step in the ThALD process does not completely remove the CH3 ligands of the trimethylaluminum precursor step, which might electrically be associated with a reduced forward bias robustness. The O2 plasma step in the PEALD process is associated with the removal of carbon and a tremendous increase of the O content in the GaN surface region. Electrically, this strongly correlates to an enhanced forward bias robustness and an increased forward bias hysteresis, respectively. The ThALD/PEALD stack method mitigates the shortcomings of both ALD processes while maintaining its advantages. Electrical measurements indicate that the stack method alongside NH3 plasma pretreatment provides the best characteristics in terms of hysteresis, threshold voltage, forward bias robustness, and interface trap density of states. [ABSTRACT FROM AUTHOR]

We have systematically investigated effects of metal–semiconductor or insulator–semiconductor interfacial layers (ILs) in AlGaN/GaN devices, where AlO x , TiO x , or NiO x is employed as an IL. From capacitance–voltage characteristics of metal/IL/AlGaN/GaN devices with a metal–semiconductor IL between the gate metal and AlGaN, it is shown that the IL modulates the threshold voltage V th , attributed to the vacuum level step induced by the dipole of the IL. We find negative vacuum level steps for AlO x and TiO x ILs, and positive for NiO x , from which the IL dipole density is estimated for each IL material. The two-dimensional electron gas carrier concentration in the metal/IL/AlGaN/GaN devices is also modulated by the vacuum level step. On the other hand, from capacitance–voltage characteristics of metal/ Al 2 O 3 /IL/AlGaN/GaN devices with an insulator–semiconductor IL between Al 2 O 3 and AlGaN, the fixed charge density of the Al 2 O 3 /IL/AlGaN interface is evaluated by the Al 2 O 3 thickness dependence of V th . For AlO x and TiO x ILs, the fixed charge density is higher than that of the Al 2 O 3 /AlGaN interface with no IL, while lower for NiO x. The fixed charge density for an IL shows a positive correlation with the IL dipole density, suggesting that the fixed charge is related to the unbalanced IL dipole. Furthermore, using the conductance method, we find a low trap density of the Al 2 O 3 /IL/AlGaN interface for AlO x and NiO x ILs, in comparison with that of the Al 2 O 3 /AlGaN interface with no IL. [ABSTRACT FROM AUTHOR]

Gallium oxide (G a 2 O 3 ) is a promising ultra-wide bandgap material offering a large bandgap (> --> 4.7 eV) and high critical electric fields. The increasing demand for electronic devices for high-power applications in electric automobiles, high-performance computing, green energy technologies, etc., requires higher voltages and currents with enhanced efficiency. Vertical transistors, such as fin-shaped field-effect transistors (FinFETs) have emerged to meet the growing need with improved current handling capabilities, reduced resistance, and enhanced thermal performance. However, to fully exploit the Ga 2 O 3 power transistors, precise and reliable physics-driven models are crucial. Therefore, a comprehensive surface potential model has been developed in this work for a vertical Ga 2 O 3 FinFET. The electric potential across the channel is explained by analyzing the two-dimensional (2D) Poisson equation employing parabolic approximation. Such a surface potential model is instrumental in determining the performance of the Ga 2 O 3 FinFET as it affects the threshold voltage, the drain current, and fringing capacitance. Exploiting the surface potentials, a fringing capacitance model is derived which is crucial in analyzing the speed of the device in compact integrated circuits. In addition, statistical analysis of the Ga 2 O 3 FinFET using the Monte Carlo simulation technique is performed to determine the leakage current fluctuation due to doping variations. The validation of the analytical model with experimental results confirms the effectiveness and prospects of the developed models in the rapid development and characterization of next-generation high-performance vertical Ga 2 O 3 power transistors. [ABSTRACT FROM AUTHOR]

In this paper, we designed double V-shaped Al/Ni multilayer energy-containing microdevices with different V-angles, and we performed finite element modeling and simulation of the heat transfer process of the designed energy-containing microdevice. Temperature-dependent resistivity was introduced to effectively simulate the phase change during ignition. We simulated the temperature and current density distribution in the central region of the Al/Ni multilayer energy-containing microdevice and predicted the ignition voltage threshold for the specific device structure. Al/Ni multilayer energy-containing microdevices with different V-angles were prepared by electron beam evaporation technology, and ignition experiments on the prepared devices under the excitation of 47 μF capacitance were conducted. The experimental results show that the critical voltage of ignition increases with the increase in the V-angle, which verifies the correctness of the proposed finite element model. [ABSTRACT FROM AUTHOR]

In recent years, neural networks have achieved phenomenal success across a wide range of applications. They have also proven useful for solving differential equations. The focus of this work is on the Poisson–Boltzmann equation (PBE) that governs the electrostatics of a metal–oxide–semiconductor capacitor. We were motivated by the question of whether a neural network can effectively learn the solution of PBE using the methodology pioneered by Lagaris et al. [IEEE Trans. Neural Netw. 9 (1998)]. In this method, a neural network is used to generate a set of trial solutions that adhere to the boundary conditions, which are then optimized using the governing equation. However, the challenge with this method is the lack of a generic procedure for creating trial solutions for intricate boundary conditions. We introduce a novel method for generating trial solutions that adhere to the Robin and Dirichlet boundary conditions associated with the PBE. Remarkably, by optimizing the network parameters, we can learn an optimal trial solution that accurately captures essential physical insights, such as the depletion width, the threshold voltage, and the inversion charge. Furthermore, we show that our functional solution can extend beyond the sampling domain. [ABSTRACT FROM AUTHOR]

Intrinsically random hardware devices are increasingly attracting attention for their potential use in probabilistic computing architectures. One such device is the single-photon avalanche diode (SPAD) and an associated functional unit, the variable-rate SPAD circuit (VRSC), recently proposed by us as a source of randomness for sampling and annealing Ising and Potts models. This work develops a more advanced understanding of these VRSCs by introducing several VRSC design options and studying their tradeoffs as implemented in a 65-nm CMOS process. Each VRSC is composed of a SPAD and a processing circuit. Combinations of three different SPAD designs and three different types of processing circuits were evaluated on several metrics such as area, speed, and variability. Measured results from the SPAD design space show that even extremely small SPADs are suitable for probabilistic computing purposes, and that high dark count rates are not detrimental either, so SPADs for probabilistic computing are actually easier to integrate in standard CMOS processes. Results from the circuit design space show that the time-to-analog-based designs introduced in this work can produce highly exponential and analytical transfer functions, but that the less analytically tractable output of the previously proposed filter-based designs can achieve less variability in a smaller footprint. Probabilistic bits (P-bits) composed of the fabricated VRSCs achieve bit flip rates of 50 MHz and allow at least one order of magnitude of control over their simulated annealing temperature.

Ceramic matrix composites (CMCs) on one level are excellent materials for acoustic emission (AE) analysis. They are excellent waveguides for AE waveform transmission due to the high modulus to density ratio. CMC inelastic behavior is due to micro‐ and macrocrack formation from matrix crack interaction with the fibers via a relatively weak fiber/matrix interface which create ideal stress waves. Because of this, AE is an excellent detector of microcracks in general, and most importantly in the case of CMCs, the initial or lowest stress crack formation. This property can be related to long time stressed‐oxidation degradation of nonoxide composites, in particular. In addition, AE has been used to effectively determine the stress distribution for matrix cracks which cause the nonlinear stress–strain behavior. However, a key to quantitatively correlating AE with sources is first and foremost to locate where the AE originated. For a tensile test, most AE comes from the near‐grip region and the radius region outside the gage area of interest. Outside the gage region AE would not be considered useful data pertaining to stress/strain behavior and must be sorted out from the AE dataset. Location is determined by the difference in time of arrivals (TOAs) of waveforms received on each sensor from a given AE source. Automated TOA techniques such as threshold voltage crossing or Akaike information criteria (AIC) have limitations in overall accuracy of differences in TOA (Δt) of two different sensors required for location analysis. This study has incorporated several signal filter and enhancement techniques and an approach toward increasing the accuracy of the classic TOA techniques. First TOA was determined for the two sensors of the AE tests "manually" based on first extensional peak of the waveform, this served as the "exact" difference in TOA. Δt's were then determined for the various filter/TOA techniques and compared to those from the manual determined Δt. The best filter/TOA techniques resulted in more than two times better accuracy (defined as percentage of events within 0.1 µs of the exact Δt) than the conventional threshold crossing or AIC technique. [ABSTRACT FROM AUTHOR]

Threshold voltage (VTH) instability affects the reliability of silicon carbide (SiC) MOSFETs. In this article, the influence of gate bias (VGS) and high temperature on VTH instability is investigated under wide VGS and very‐high temperature range (150°C to 275°C). The degradation mechanism of gate oxide under coupling of different electrical and thermal stress is revealed. When the device is subjected to +VGS, the relationship between VTH shift and temperature is not monotonic and there is a temperature turning point. This is mainly related to the capture/release and generation of electron traps. However, the VTH shift increases sharply and gate oxide breakdown for the device bias at +35 V, which is related to Fowler–Nordheim (F–N) tunnelling effect. For a large −VGS, the VTH shift is very small. Moreover, when the negative VGS decreases, the VTH shift is positively correlated with temperature, which may result from the activation and charge exchange of hole traps. However, the influence of moving ions changes the temperature dependence of VTH shift for the device bias at −30 V. Finally, the devices of different manufacturers are studied and similar change patterns are found. This finding provides guidance for the further application of SiC MOSFETs under high temperatures and different voltages. [ABSTRACT FROM AUTHOR]

Despite the roll-to-roll (R2R) gravure printing method emerging as an alternative sustainable technology for fabricating logic circuits based on p- and n-types of single-walled carbon nanotube thin film transistors (p,n-SWCNT-TFTs), the wide variation of large threshold voltage (Vth > ~8) in the R2R printed p,n-SWCNT-TFTs prevents the integration of complementary logic circuit. Here, the Vth variation of the p,n-SWCNT-TFTs was narrowed down by developing a method of using the first gravure roll with the minimized superposition error (< ±40 µm) of engraved registration marks and implementing the R2R doping process for tailoring the Vth using polymer-based p- and n-doping inks. Through those two methods, the R2R printed the p,n-SWCNT-TFTs was tailored to shift Vth to near ±2.7 V and reduce Vth variation to ±1.6 V while the noise margin was improved by 24% so that a large number of R2R printed logic gates could be integrated with clear logic levels at ±10 V of operation voltage. Based on the tailored p,n-SWCNT-TFTs, a fully R2R printed 4-bit arithmetic and logic unit was successfully demonstrated by integrating 156 p,n-SWCNT-TFTs. [ABSTRACT FROM AUTHOR]

Ovonic threshold switching (OTS), characterized by a rapid resistance drop in chalcogenide glass, has enabled the realization of memory and selectors. Despite over five decades of development, the challenges in characterizing the transient switching in amorphous materials upon reaching the threshold voltage have hindered the establishment of its underlying mechanism. This study uses femtosecond terahertz spectroscopy and ab initio simulation to elucidate the dynamics of the free‐carrier and IR‐active phonons involved in OTS. Specifically, in Te‐rich amorphous GeTe, the generation of transient phonons is observed within picoseconds, a phenomenon associated with an increased Born effective charge due to the alignment of Te‐centered bonds. The findings demonstrate a correlation between the enhancement of polarizability, due to orbital alignment during the disorder–order structural transition while maintaining a macroscopic amorphous structure, and the switching behavior. These results provide valuable insights into the enigmatic OTS phenomenon. [ABSTRACT FROM AUTHOR]

Real biological neurons are dynamical systems that can process a nonlinear, arbitrary input signal with a dynamic threshold voltage, exhibit refractory time, and have a smooth F – I curve. This paper presents a generalized bio-plausible neuron model with refractoriness, frequency adaptation, and dynamic threshold. The spiking characteristics of the generalized neuron are enhanced with less circuitry and fewer parameters compared to older circuits. The proposed silicon neuron can generate all known spiking behaviors, just like a biological neuron. The circuit is designed using a 180 nm standard CMOS process. The entire design uses 22 transistors with a total power consumption of only 2 nW for a 1 nA step current at a spike frequency of 122 Hz. The power consumption and spike frequency rate depend on the input current. The proposed neuron is also capable of displaying both Type I and Type II frequency response characteristics. In addition, our neuron model underwent Monte Carlo simulation with 1000 sample runs to assess its robustness and stability against process variations and uncertainties. The results indicate that the average energy consumption of the proposed neuron model falls within the range of 16 pJ to 68 pJ. [ABSTRACT FROM AUTHOR]

Reducing the driving voltage is a long‐term and important challenge in the development of light‐emitting diodes (LEDs) because the light‐emission threshold voltage cannot be below the theoretical limit of the emitter's bandgap divided by the elementary charge. Here, green perovskite nanocrystal (PeNC) LEDs are inverted that emit light at ultralow voltages (below the theoretical limit) realized by efficient Auger‐assisted energy up‐conversion at the interface of the zinc oxide nanoparticles (ZnO NPs) electron injection layer and PeNC light‐emission layers. The up‐conversion utilizes the recombination energy of the charge‐transfer excitons. After modifying the interface by plasma treatment of the ZnO NPs and by inserting an organic interlayer between the ZnO NPs and PeNCs, the device performance is dramatically improved from that of the unmodified PeNC LED. The threshold voltage at which the emission spectrum can be observed is 1.55 V, substantially lower than 2.34 V (the PeNC emitter's bandgap divided by the elementary charge). Moreover, after mixing an organic aromatic semiconductor compound in the PeNC light‐emission layer, the carrier balance is regulated and the threshold voltage is further reduced to 1.30 V. [ABSTRACT FROM AUTHOR]

Herein, an ultralow‐threshold voltage‐responsive synaptic memristor based on CuxO and B‐doped diamond (BDD) heterojunctions is developed. The aggregation of oxygen vacancies corresponding to the high‐ and low‐resistance states forms the foundation for the hysteresis behavior. The I–V curves exhibit impressive analog resistive switching (analog RS), which renders the memristor highly suitable for simulating synaptic stimulation. The reliable stability of this structure is confirmed using 122 individual devices, achieving a yield of 90.2% with highly consistent I–V curves. In addition, the effect of the B‐dopant level in the diamond is investigated. By reducing the B/C ratio of the precursor from 1:500 to 1:2000 during the hot filament chemical vapor deposition synthesis process, a significant 55.3% reduction in current is achieved, leading to lower energy consumption. The Schottky barrier height increases with decreasing B‐dopant levels, providing a broader adjustable range for synaptic weight renewal. Remarkably, when the pulse amplitude is decreased to an ultralow value of 3 mV, the synaptic function of the device remains observable, with an energy consumption of only 9.5 × 10−11 J. To the best of the authors’ knowledge, this is the first report of such a low‐amplitude pulse voltage in a two‐terminal memristor. [ABSTRACT FROM AUTHOR]

In this work, we report on the beta-gallium oxide (β-Ga2O3) monolithic bidirectional switch. The as-fabricated switch works on enhancement mode operation with a threshold voltage of ∼4 V. Maximum drain current density of 1.93 mA/mm is obtained with a drain voltage of 5 V. The bidirectional switch in a bidirectional mode has an ON/OFF current ratio of ∼107 with ON-resistance of 1.11 and 1.09 kΩ · mm in forward and reverse direction, respectively. However, in diode mode, the device shows an ON/OFF current ratio of 1.6 × 108 and 1.4 × 108 in forward and reverse conduction modes, respectively. The fabricated β-Ga2O3 monolithic bidirectional switch is then used to chop a 60 Hz Alternating Current signal at a chopping frequency of 1 kHz, indicating its potential applications in a range of converters. [ABSTRACT FROM AUTHOR]

This work investigates the gate oxide reliability of commercial 1.2 kV silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) with planar and trench gate structures. The performance of threshold voltage (V t h) and gate leakage current (I g s s) in SiC MOSFETs is evaluated under positive and negative gate voltage stress. The oxide lifetimes of SiC planar and trench MOSFETs at 150 °C are measured using constant voltage Time-Dependent Dielectric Breakdown (TDDB) testing. From the test results, it is found that electron trapping and hole trapping in S i O 2 caused by oxide electric field (E o x)  stress affect the V t h of SiC MOSFETs. The saturation and turnaround behavior of the V t h shift during positive and negative gate voltage stresses indicates that the influence of charge trapping in the gate oxide varies with stress time. The I g s s under positive and negative gate voltages depends on the tunneling barrier height for electrons and holes, respectively, which can be calculated using the Fowler–Nordheim (FN) tunneling mechanism. Moreover, the presence of near-interface traps (NITs) affects the barrier height for holes under negative gate voltages. The behavior of V t h shift and I g s s under high-temperature gate bias reflects the charge trapping occurring in different regions of the gate oxide. In addition, compared to SiC planar MOSFETs, SiC trench MOSFETs with thicker gate oxide tend to exhibit higher lifetimes in TDDB tests. [ABSTRACT FROM AUTHOR]

Ferroelectric (FE) hafnium zirconium oxide (HZO) thin‐film transistors (TFTs) are of increasing interest for next‐generation memory and computing applications. However, these devices face challenges in achieving a substantial memory window (MW). This report presents amorphous InGaZnO (a‐IGZO) ferroelectric–dielectric (FD), dual‐gate thin‐film transistors (DG‐TFTs) with FE‐HZO as a bottom gate insulator (GI) and SiO2 as a top GI. The ferroelectricity in HZO is confirmed through the grazing incidence X‐ray diffraction (GI‐XRD), capacitance, and polarization measurements. The FD‐DG TFT can increase the MW by tuning the threshold voltage (VTH) due to electrostatic coupling between the top gate (TG) and bottom gate (BG). The increase of MW at the TG driving is related to the coupling factor which is equal to the ratio of the equivalent capacitance of top to bottom gated transistors. During the bottom sweep, the FD‐DG‐TFT demonstrates an anticlockwise hysteresis with a MW of 4.98 V, a high ION/IOFF ratio of ≈106, and a steep subthreshold swing (SS) of 90 mV dec−1. On the contrary, MW of 12 V and SS of 140 mV dec−1 are observed for the top sweep operation. A thinner ferroelectric GI at BG TFT induces sufficient electrostatic coupling to cause a large VTH shift at TG driving, resulting in a boosted MW. [ABSTRACT FROM AUTHOR]

The gate reliability of p-GaN gate high electron mobility transistors (HEMTs) was investigated in this Letter. Compared with conventional p-GaN gate HEMT, the in situ SiN cap-layer on the p-GaN layer can lift up the energy band and form a metal–insulator–semiconductor structure. With the introduction of an in situ SiN cap-layer, the DC electrical characteristics and reliability have been significantly improved. The reverse gate leakage current is reduced by 3 orders of magnitude. The threshold voltage shifts from 1.67 to 3.25 V, the on-resistances increased from 8.7 to 9.9 Ω mm, and the gate breakdown voltage is improved from 10.2 to 16.3 V. After conducting time-dependent gate breakdown measurement and predicting lifetime with a 10-year failure rate of 63%, it is calculated that the maximum allowable gate voltage increased from 6.3 to 11.4 V. The 10-year gate voltage swing has improved from 4.63 to 8.15 V. In addition, the in situ SiN HEMT exhibits good stability under high temperatures and long-term stress tests. The experimental results demonstrate that the in situ SiN cap-layer offers significant advantages in gate reliability. [ABSTRACT FROM AUTHOR]

In this paper, the effect of p–n heterostructures on the electro‐optical and heat regulation performances of polymer dispersed liquid crystal (PDLC) dimming films are studied. In detail, the WO3, Ag2O, and WO3/Ag2O p–n heterostructures are successfully synthesized via the co‐precipitation method. The products are analyzed by XRD, SEM, TEM, and XPS and the results demonstrated that the WO3 nanorods successfully grew on the surface of Ag2O. Compared to the primitive sample, the incorporation of p–n heterostructures into the composite films significantly enhances the electro‐optical properties. For a 20µm‐thick film, the saturation voltage (Vsat) decreases by 38.7% from 24.8 to 15.2 V, and the threshold voltage (Vth) is reduced by 22.9% from 12.7 to 9.8 V, while the contrast ratio reaches 132. Due to the molecular structure of the polymer monomers and the micro‐network structure of the film, the film exhibits high emissivity in the mid infrared spectrum, enabling enhanced dynamic cooling management through radiative cooling around the clock. Matrix & laboratory (MATLAB) calculations show that the maximum cooling power during the day and night reached 97.63 and 136.24W m‐2 K‐1, respectively. This research has great significance for the development of highly energy‐efficient smart windows. [ABSTRACT FROM AUTHOR]

The threshold voltage $(V_{th})$ enables us to measure the functionality of ultra-scaled field effect transistors (FETs) and plays a key role in the performance evaluation of devices. Although many $V_{th}$ extraction methods exist and are in use in the industry, selecting an optimized and universal method is still difficult. Additionally, these methods often rely on expert validation, which increases the time cost for researchers to optimize the extraction process. In this work, we propose a universal and autonomous machine learning model, specifically a convolutional neural network based $V_{th}$ extractor model. The novelty of this work lies in simultaneously processing gate, drain, source, and bulk currents combined with gate voltage to remove the dependency on setting boundaries for gate voltage. Additionally, the training dataset is composed of measurements coming from transistors of different technology nodes (Planar, MOSFET, FinFET, Gate-All-Around) to provide generalization. Our method produces significantly more accurate results than traditional ML algorithms by extracting $V_{th}$ in 3mV mean absolute error rate and is verified with different performance metrics. [ABSTRACT FROM AUTHOR]

This study presents the numerical modeling of an underlap gate cavity-integrated reconfigurable silicon nanowire Schottky barrier transistor (UGC-RSiNW SBT) that features a gate-drain underlap region, specifically designed for biosensing applications. The proposed device features a cavity under the control gate on the source side, allowing the immobilization of neutral and charged biomolecules having different dielectric constants. The program gate is specifically placed over the channel-drain Schottky junction to reduce the ambipolar behavior of the device. Using the 2D Poisson equation, we model electrostatic characteristics such as electric potential, threshold voltage, electric field, and drain current. Biomolecules in a cavity can be detected and identified by measuring the variation in threshold voltage ( V Th ), which is caused by the biomolecules' interactions with the local electric field and their influence on charge carrier transport. Simulation results using Silvaco TCAD tools demonstrate significant improvements in sensitivity of the proposed biosensor as compared to conventional RFET biosensors. The study shows a 97.91% increase in the V Th sensitivity of the device for the N-channel and a 16% improvement for the P-channel. The drain current sensitivity and the linearity of proposed biosensor is enhanced upto the values of 2792 and 0.997 respectively in n-mode configuration whereas in p-mode configuration, the drain current sensitivity and the linearity comes out to be 968 and 0.995 respectively. These high sensitivity and linearity values make this biosensor superior to the existing state-of-the-art biosensors. The simulated results were validated when compared with existing literature, confirming the effectiveness of the Silvaco TCAD tool in accurately modeling the biosensor's performance These findings offer valuable insights for developing highly sensitive biosensors for healthcare and biotechnology applications. [ABSTRACT FROM AUTHOR]

In this study, a nitride‐based blue PEDOT‐LED is fabricated and a preliminary assessment of the device characteristics is done. To prevent detaching of the PEDOT/PSS layer from the LED substrate when immersing in water or developing solution, Ag was deposited on top of the PEDOT/PSS layer. Additionally, exfoliation is suppressed by reducing the developing time and protecting the wafer edge with a photoresist. Different etching methods for Ag and PEDOT/PSS are investigated. The Ar ion‐beam etching resulted in uniform and flat‐etched surfaces. Regarding the performance of the PEDOT‐LEDs, a high Mg‐doping concentration of 1.0 × 1020 cm−2 leads to a relatively low threshold current voltage in the V–I characteristics. However, for the PEDOT‐LED with p‐Al0.25Ga0.75 N EBL, a steep light output saturation is observed at high current density when analyzing the L–I characteristics. [ABSTRACT FROM AUTHOR]

Gallium nitride (GaN)‐on‐Si high electron mobility transistors require insulating GaN buffers, which are prone to charge trapping and result in dynamic ON‐state resistance (dRDS,on) that negatively impacts performance and reliability. Herein, simultaneous measurements of threshold voltage shift (dVTH) and dRDS,on during OFF‐state stress with microsecond time resolution are employed. Ohmic p‐GaN gate contacts enable the use of dVTH to probe charge accumulation under the gate, while dRDS,on probes charge accumulation in the gate‐drain access region. Comparison of dVTH and dRDS,on provides direct evidence of lateral hole transport in the GaN buffer when exposed to a lateral electric field in OFF‐state. This lateral hole transport causes positive charge accumulation in the buffer under the gate and triggers a newly proposed electron injection mechanism into the same region. Only by considering the combination of lateral hole transport and electron injection under the gate the observed up to fivefold dRDS,on increase in OFF‐state stress compared to back‐gating at low biases can be explained. Furthermore, another electron spillover mechanism is introduced that occurs for large positive charge accumulation under the gate and limits the maximum negative dVTH. All known and newly introduced processes during OFF‐state are summarized in a concise dynamic buffer charging model. [ABSTRACT FROM AUTHOR]

Herein, the fabrication and characterization of vertical GaN trench‐MOSFETs on ammonothermally grown bulk GaN substrates have been reported. A number of technological processes have been developed, including, among others, low‐resistance ohmic contacts to Ga‐face n‐GaN epitaxial layers, N‐face backside ohmic contact, vertical sidewall trench etching processes, surface preparation, and atomic layer deposition of gate dielectric layers and integrated with fabrication process flow of vertical power devices. The fabricated test structures are characterized by an output drain current of 288 ± 74 mA mm−1, threshold voltage of about 10 V, and field‐effect channel mobility 13.1 ± 5.0 cm2 (Vs)−1 at 10 V drain‐source voltage and up to 65 cm2 (Vs)−1 at 0.1 V drain‐source voltage. In addition, first, experiments toward high current multicell transistor fabrication are carried out. Multicell test devices with hexagonal topology with a total gate width of 11.1 mm and output current over 1 A are successfully fabricated and characterized. [ABSTRACT FROM AUTHOR]

Herein, a DC and microwave performance of 2 μm gate length AlGaN/GaN high‐electron‐mobility transistor (HEMTs) on a Mn‐doped GaN substrate is demonstrated. The maximum drain current is 670 mA with a threshold voltage of −$-$2.5 V and with good pinch‐off characteristics. The breakdown voltage of the HEMT is ≈80 V. The HEMT shows Δ8% current collapse while referenced HEMT on a SiC substrates which is fabricated simultaneously shows large Δ30% current collapse. When the HEMT with a gate width of 100 μm is tuned for the maximum output power at 2.4 GHz with a drain voltage of 30 V, it delivers 500 mW (5 W mm−1) with the maximum drain efficiency of 54%. These output performances are in good agreement with ideal class‐A operation performance. Therefore, it is concluded that the HEMT on Mn‐doped GaN substrates is promising for future microwave and millimeter‐wave high‐power transistors. [ABSTRACT FROM AUTHOR]

AlGaN/GaN high electron mobility transistors (HEMTs) with different GaN channel layers grown on AlN buffer layer are fabricated and investigated in order to optimize the device performances and to study the noise properties. To investigate the strain effect of the GaN channel layer grown on the AlN buffer layer, the positive shift of Raman peak is observed as the GaN channel becomes thinner. The threshold voltages (Vth) of the fabricated devices shift to positive direction according to the decreased GaN channel layer due to the decreased 2‐dimensional electron gas (2DEG) and deteriorated crystal quality of GaN channel layer. All devices demonstrated 1/f noise properties and the dominance of the carrier number fluctuations (CNF) noise mechanism. The largest trap density (Nt) value in the narrowest GaN channel device is because of the degraded crystal quality and the enhanced strain effect of the GaN channel layer. However, the lowest noise levels at the drain current (Id) > 10−6 A for the device with the GaN channel thickness of 30 nm grown on AlN buffer layer are observed to be due to the fully depleted GaN channel layer although its poor crystal quality. [ABSTRACT FROM AUTHOR]

The ultrathin‐barrier (UTB) AlGaN/GaN heterostructure exhibits great promise as a technology for manufacturing high‐performance normally OFF GaN metal–insulator–semiconductor high‐electron‐mobility transistors (MIS–HEMTs) due to its unique gate recess‐free feature. However, a critical challenge in UTB MIS–HEMTs is the recovery of the 2D electron gas in the access region, particularly with regard to achieving low ON resistance. In this study, a new approach is proposed to address this issue by utilizing a low‐thermal‐budget Al2O3 film grown through atomic layer deposition (ALD). By analyzing the capacitance–voltage characteristic and correlating it with the threshold voltage shift versus dielectric thicknesses for SiNx and Al2O3, high density of positive fixed charges (≈2.382 × 1013 cm−2) is confirmed to be induced at the interface between ALD–Al2O3 and GaN (cap), which is also in good agreement with 1D Poisson simulations of energy band diagrams. The positive charges are probably originated from the interface AlAl bonds revealed by X‐Ray photoelectron spectroscopy analysis. [ABSTRACT FROM AUTHOR]

Organic phototransistors, renowned for their exceptional biocompatibility, hold promise in phototherapy for tracking the efficacy of photosensitive drugs within treatment areas. Nevertheless, it has been found that organic semiconductors are less effective in detecting ultraviolet (UV) light because of their narrow bandgap. Here, we show that UV photodetection in phototransistors using donor-acceptor (D-A) polymer semiconductors can be significantly enhanced by incorporating PCBM nanocrystals. This integration results in a band mismatch between the nanocrystals and the D-A polymer at the interface. These nanocrystals also demonstrate a notable capability of modulating threshold voltage under UV light. The devices incorporating nanocrystals exhibit a photoresponsivity of 0.16 A/W, surpassing the photoresponsivity of the devices without nanocrystals by 50%. The specific detection rate of devices with nanocrystals is around 2.00 × 1010 Jones, which is twice as high as that of devices without nanocrystals. The presented findings offer a potential avenue to improve the efficiency of polymer phototransistors for UV detection. [ABSTRACT FROM AUTHOR]

An AlSiO/AlN‐interlayer gate stack formed on c‐plane GaN metal‐oxide‐semiconductor (MOS) devices was previously developed to enhance the interface of the gate insulator. By utilizing this gate stack structure, a channel mobility of over 200 cm2 Vs−1 on c‐plane was obtained. However, the threshold voltage was negative because of the polarization charge at the AlN/GaN interface. This study extends the application of this gate stack structure to the nonpolar m‐plane, which is obtained from a trench sidewall. Both a high channel mobility of 150 cm2 Vs−1 and a threshold voltage of 1.3 V is successfully achieved, normally‐off operation. This achievement holds significant promise for the gate structure of a GaN trench‐gate MOS field‐effect transistor (MOSFET). The limiting factor of the channel mobility is Coulomb scattering in a low electric field, whereas surface roughness scattering is dominant in a higher field. [ABSTRACT FROM AUTHOR]

The Na‐flux method is expected to be a key GaN growth technique for obtaining ideal bulk GaN crystals. Herein, the structural quality of the latest GaN crystals grown using the Na‐flux method and, for the first time, the characteristics of a vertical transistor fabricated on a GaN substrate grown using this method are discussed. Vertical transistors exhibit normally off operation with a gate voltage threshold exceeding 2 V and a maximum drain current of 3.3 A during the on‐state operation. Additionally, it demonstrates a breakdown voltage exceeding 600 V and a low leakage current during off‐state operation. It is also described that the variation in the on‐resistance can be minimized using GaN substrates with minimal off‐angle variations. This is crucial for achieving the large‐current chips required for future demonstration of actual devices. In addition, the reverse I–V characteristics of the parasitic p–n junction diode (PND) structures indicate a reduction in the number of devices with a significant leakage current compared to commercially available GaN substrates. Finally, a circular GaN substrate with a diameter of 161 mm, surpassing 6 inches, grown using the Na‐flux method is demonstrated, making it the largest GaN substrate aside from those produced through the tiling technique. [ABSTRACT FROM AUTHOR]

Quasivertical gallium nitride trench‐gate metal–oxide–semiconductor field‐effect transistors with different etch radio frequency power and the impact of the order of annealing process in tetramethylammonium hydroxide wet treatment have been fabricated and studied. The high‐power device has a threshold voltage of 5.3 V and a maximum saturation current density of 552 A cm−2, whereas the low‐power device has a threshold voltage of 4.5 V and a maximum saturation current density of 650 A cm−2. However, the low‐power device has more severe off‐state leakage due to more fixed charges and defects on the device surface. Furthermore, the annealing process serves as an additional step before wet treatment. Scanning electron mircoscope image indicates that annealing at high temperatures prior to etching can eliminate surface oxide and redistribute surface imperfections, resulting in a smoother sidewall morphology. The relationship between temperature and mobility confirms the impact of the crystal surface feature on device performance. [ABSTRACT FROM AUTHOR]

This paper models and analyzes the Complementary Metal Oxide Semiconductor (CMOS) cross-coupled differential-drive (CCDD) rectifier for Ultra-Low-Power ambient radio-frequency energy harvesters (RFEHs) working in the subthreshold region. In this paper, two closed-form equations of CCDD rectifier output voltage and input resistance in the subthreshold region were derived based on BSIM4 models of NMOS and PMOS. The model give insight to specify circuit parameters according to different inputs, transistor sizes, threshold voltages, numbers of stages, load conditions and compensation voltages, which can be used to optimize the rectifier circuit. There is a good agreement between the simulation results and these models, and these models have a maximum deviation of 10% in comparison with the simulation results in the subthreshold region. The measurement results of a single-stage CCDD rectifier reported in a previous paper were adopted to verify the model. The output voltage and input resistance predicted by these models provide excellent consistency with corresponding measurement results. The model can be employed to optimize the CCDD rectifier without expensive calculation in the design stage. [ABSTRACT FROM AUTHOR]

While voltage-gated sodium channels Nav1.7 and Nav1.8 both contribute to electrogenesis in dorsal root ganglion (DRG) neurons, details of their interactions have remained unexplored. Here, we studied the functional contribution of Nav1.8 in DRG neurons using a dynamic clamp to express Nav1.7L848H, a gain-of-function Nav1.7 mutation that causes inherited erythromelalgia (IEM), a human genetic model of neuropathic pain, and demonstrate a profound functional interaction of Nav1.8 with Nav1.7 close to the threshold for AP generation. At the voltage threshold of -21.9 mV, we observed that Nav1.8 channel open-probability exceeded Nav1.7WT channel open-probability ninefold. Using a kinetic model of Nav1.8, we showed that a reduction of Nav1.8 current by even 25-50% increases rheobase and reduces firing probability in small DRG neurons expressing Nav1.7L848H. Nav1.8 subtraction also reduces the amplitudes of subthreshold membrane potential oscillations in these cells. Our results show that within DRG neurons that express peripheral sodium channel Nav1.7, the Nav1.8 channel amplifies excitability at a broad range of membrane voltages with a predominant effect close to the AP voltage threshold, while Nav1.7 plays a major role at voltages closer to resting membrane potential. Our data show that dynamic-clamp reduction of Nav1.8 conductance by 25-50% can reverse hyperexcitability of DRG neurons expressing a gain-of-function Nav1.7 mutation that causes pain in humans and suggests, more generally, that full inhibition of Nav1.8 may not be required for relief of pain due to DRG neuron hyperexcitability. [ABSTRACT FROM AUTHOR]

Threshold voltage ( V th ) assignment is convenient for leakage optimization due to the exponential relation between leakage power and V th by swapping logic cells without routing effort. However, it poses great challenge in large scale circuit design as an NP-hard problem. Machine learning-based approaches have been proposed to solve this problem, aiming to achieve well tradeoff between leakage power reduction and runtime speed up without new induced timing violation. In this paper, a leakage power optimization framework based on reinforcement learning (RL) with graph neural network (GNN) is first-ever proposed to formulate V th assignment as a RL process by learning timing and physical characteristics of each circuit instance with GNN. Multiple instances are selected in a non-overlapped manner for each RL action iteration to speed up convergence and decouple timing interdependence along circuit path, where the corresponding reward is carefully defined to tradeoff between leakage reduction and potential timing violation. The proposed framework was validated by the Opencores and IWLS 2005 benchmark circuits with TSMC 28 nm technology. Experimental results demonstrate that our work outperforms prior non-analytical and GNN-based methods with better leakage power optimization by additional 5% to 17% reduction, which is highly consistent with the commercial tool. When transferring the trained RL-based framework to unseen circuits, it achieves the roughly identical leakage optimization results as seen circuit and speed up the runtime by 5.7 × to 8.5 × compared with commercial tool. [ABSTRACT FROM AUTHOR]

Purpose: This paper presents a novel low-power, low input offset rail-to-rail comparator that is suitable for a digital dominant successive approximation resistor analog-to-digital converter. The proposed comparator is based on traditional inverters cascaded to amplify analog signals and digital logic level conversion. The absence of a direct path between the high-swing output node and the input node restricts kickback noise. Design/methodology/approach: The proposed circuit is designed and simulated using UMC 28 nm and 40 nm CMOS technology. The simulated power consumption using UMC 40 nm CMOS technology is 6.2084 μW at 1.1 V (330.8nW at 700 mV) supply voltage at the 2.5 MHz clock frequency. Similarly, simulated power consumption using UMC 28 nm technology is 0.04104μW at 900 mV (0.0097μW at 600 mV) and supply voltage operating at 66.66 MHz clock frequency with a resolution of a maximum of 12 bits, therefore, a reduction of more than 90% in power consumption observed by scaling technology node. Findings: The conventional power-efficient clock-controlled latched comparator does not have a static current during the entire operation. The main drawbacks are the limited input range and the the kickback noise. However, a large voltage swing on the drain of a differential pair, due to this current feeding through a parasitic drain gate capacitor to the input node and the presence of source impedance, results in kickback noise. The performance of the ADC can be hampered by excessive kickback noise, which can eventually cause an incorrect comparator output. An inverter-based comparator is reported, where the input range is rail-to-rail and operates at moderate speed. Modern scaled technologies have better matching among transistors, i.e. matching of switching threshold voltage achieved by selecting suitable aspect ratios of transistors (cascaded inverters). Inverter-based dynamic comparators are inherently power-scalable and switching threshold voltage scales with supply voltage variation. Therefore, the amplification operation is not hampered by the reduction of the supply voltage. Originality/value: The proposed architecture is compared with a set of existing hardware architectures to analyse various design metrics, such as low input offset, power scalability to maintain the resolution of the comparator, and low kickback noise. [ABSTRACT FROM AUTHOR]

We report here a study on doping concentration variation on Double Gate Junctionless Field Effect Transistor. Doping concentration for the device is varied from 1010/cm³ to 1019/cm³ and their transfer characteristics and output characteristics were investigated for drain section voltages with 0.1 V, 0.5 V and 1 V. At 1 V drain voltage with doping level 1019 cm-3 a drain current of 1.7 mA has been obtained. Furthermore various electrical parameters like on current, Ion to Iorr ratio, subthreshold swing, threshold voltages are investigated. At 1019 cm and drain potential 1 V current in body is 1.9 mA. On the other hand subthreshold swing obtained at 1019 cm with a drain potential 1 V is 79 mV/Decade. The simulation is done with the help of Cogenda Visual TCAD simulator. By increasing doping concentration better control over drain current can be obtained. Better on current can be achieved at higher doping variation. [ABSTRACT FROM AUTHOR]

The effective work‐function of metal electrode is one of the major factors to determine the threshold voltage of metal/oxide/semiconductor junction. In this work, it is demonstrated experimentally that the effective work‐function of the Aluminum (Al) electrode in Al/SiO2/n‐Si junction increases significantly by ≈1.04 eV with the graphene interlayer inserted at Al/SiO2 interface. The device‐physical analysis of solving Poisson equation analytically is provided when the flat‐band voltage is applied to the junction, supporting that the large tuning of Al effective work‐function may originate from the electric dipole layer formed by the off‐centric distribution of electron orbitals between Al and graphene layer. Our work suggests the feasibility of constructing the dual‐metal gate CMOS circuitry just by using Al electrodes with area‐specific underlying graphene interlayer. [ABSTRACT FROM AUTHOR]

Advanced filamentary devices are crucial for developing low‐power devices to implement high‐speed logic and neuromorphic devices. Among these, HfO2‐based filamentary devices have attracted attention as viable options due to their threshold‐switching characteristics and compatibility with complementary metal‐oxide‐semiconductor (CMOS) technology. However, the unpredictability of conventional filament formation/rupture driven by an electric field challenges consistency and reliability. A paradigm shift from conventional stochastic electric field‐driven ion migration to controllable ion‐based transportation is essential to devise functional low‐power devices capable of controlling the filament process. This work introduces a magnetic field‐assisted threshold switching (MA‐TS) device, which integrates a neodymium magnet and a nickel (Ni) barrier layer to enable controlled dual field‐driven ion transportation. The dual field‐driven process combining the conventional vertical electric field‐driven ion migration with lateral magnetic field‐driven ion transportation, reveals a distinctive aspect of ion movement. The MA‐TS device achieves superior performances characterized by an ultra‐low threshold voltage (≈0 V), minimized leakage current in the off‐state, a variation‐immune hysteresis‐free characteristic, enhanced yield, and revival‐ability (i.e., self‐healing) after a failed TS operation. By overcoming the limitations of conventional filamentary devices, the MA‐TS device opens up a promising avenue for efficient and stable low‐power applications. [ABSTRACT FROM AUTHOR]

Hysteresis window observed in ferroelectric negative capacitance field-effect transistors (NCFETs) have been a persistent challenge in the development of reliable logic circuits, often leading to abnormal operational conditions. Despite its significance, the underlying factors driving this hysteresis phenomenon remain elusive. In this study, we employ the quasi-static L–K equation in conjunction with the Mott–Gurney law to study the impact of VO++ migration on the hysteresis behavior of NCFETs, based on a surface potential-based physical model. Compared with pristine NCFET, the difference of peak voltages in value of 1.3 V was achieved in VO++-involved sample upon reverse and forwards scanning. This result clearly suggests that the relaxation of charged oxygen vacancies significantly affects the threshold voltage under applied sweeping voltages, providing a plausible explanation for the emergence of hysteresis windows in NCFETs. A replacement of the conventional oxide layer with a buffer layer containing high-mobility ions is proposed to adjust the hysteresis window. Importantly, in accordance with the theoretical predictions, the increased ion mobility results in a substantial reduction in the hysteresis window observed in NCFETs. Our proposed physical mechanism, elucidating the space-charge-induced hysteresis behavior, provides fresh insights for mitigating hysteresis effects, thereby advancing the potential applications of NCFETs in logic circuits. [ABSTRACT FROM AUTHOR]

Anionic redox allows the direct formation of O─O bonds from lattice oxygens and provides higher catalytic in the oxygen evolution reaction (OER) than does the conventional metal ion mechanism. While previous theories have predicted and experiments have suggested the possible O─O bond, it has not yet been directly observed in the OER process. In this study, operando soft X‐ray absorption spectroscopy (sXAS) at the O K‐edge and the operando Raman spectra is performed on layered double CoFe hydroxides (LDHs) after intercalation with [Cr(C2O4)3]3−, and revealed a three‐step oxidation process, staring from Co2+ to Co3+, further to Co4+ (3d6L), and ultimately leading to the formation of O─O bonds and O2 evolution above a threshold voltage (1.4 V). In contrast, a gradual oxidation of Fe is observed in CoFe LDHs. The OER activity exhibits a significant enhancement, with the overpotential decreasing from 300 to 248 mV at 10 mA cm−2, following the intercalation of [Cr(C2O4)3]3− into CoFe LDHs, underscoring a crucial role of anionic redox in facilitating water splitting. [ABSTRACT FROM AUTHOR]

Organic mixed ionic‐electronic conductors with tunable doping, low threshold voltages, and air stability are crucial for bioelectronic applications. A homopolymer based on an alkoxy thiophene monomer and its copolymer with a thiophene carrying ethylene glycol side chains are synthesized and converted to self‐doped conjugated polyelectrolytes, P3HOTS‐TMA+, and P3HOTS‐TMA+‐co‐P3MEEET. The self‐doping occurs during the conversion to polyelectrolytes. Both polyelectrolytes show high electrical conductivity without any external dopants. UV–Vis–NIR spectroscopy and spectroelectrochemistry confirm excellent air stability of the doped state. In an organic electrochemical transistor (OECT), the P3HOTS‐TMA+ operates in depletion mode, while P3HOTS‐TMA+‐co‐P3MEEET exhibits accumulation mode of operation with low threshold voltage, both showing fast response times. On the other hand, the non‐doped homopolymer, P3MEEET, shows a high negative threshold voltage in accumulation mode. Thus, copolymerization with the self‐dopable monomer changes the mode of operation as well as the threshold voltage substantially. Ultraviolet photoelectron spectroscopy reveals a considerable reduction of the hole injection barrier for the self‐doped system P3HOTS‐TMA+. Mott‐Schottky analysis shows reduction in charge carrier concentration in the copolymer compared to the homopolymer. Thus, the copolymerization strategy with a self‐dopable monomer is an efficient tool for tuning the degree of doping leading to low threshold voltage in OECTs. [ABSTRACT FROM AUTHOR]

Achieving low threshold voltage (Vth) in organic electrochemical transistors (OECTs) is essential for minimizing power consumption and enhancing sensitivity in bioelectronic devices. However, obtaining OECT materials with ultra‐low Vth, close to 0 V for n‐type conjugated polymers remains challenging. Here, a conjugated polymer FBDOPV‐CNTVT is introduced, which features a rigid backbone structure and high electron deficiency, leading to an exceptionally low lowest unoccupied molecular orbital (LUMO) energy level of −4.67 eV, achieved through dual electron‐withdrawing substitutions. With its ultra‐low LUMO energy level, FBDOPV‐CNTVT exhibits high susceptibility to electrochemical doping, even demonstrating efficient doping near 0 V. Consequently, the OECT device employing FBDOPV‐CNTVT as the active material shows an ultra‐low Vth of 7.5 mV, setting a new record for the Vth of n‐type OECT devices. Furthermore, FBDOPV‐CNTVT exhibits a µC* value of 6.13 F cm−1 V−1 s−1 and retains ≈85% of its current after 2000 s cycling. This study highlights the potential of conjugated polymers with dual electron‐withdrawing substitutions to achieve ultra‐low LUMO energy levels, effectively reducing the Vth of n‐type OECT devices and promising advancements in bioelectronics. [ABSTRACT FROM AUTHOR]

In this study, the influence of the thickness of the channel layer on the electrical properties and stability of tungsten-doped indium oxide (IWO) thin-film transistors (TFTs) was investigated. Although oxide-semiconductor TFTs, particularly indium gallium zinc oxide, are promising, problems related to oxygen vacancies have led to their instability. In contrast, IWO has proven to be a compelling alternative because of its robust resistance to oxygen vacancies. IWO TFTs with varying channel thicknesses (10, 20, and 30 nm) were fabricated, and the device parameters, such as threshold voltage (Vth), subthreshold swing (SS), field-effect mobility (μFE), and on/off current ratio (Ion/Ioff), were analyzed. It was found that as the channel thickness increased, Vth exhibited a negative shift and SS increased, indicating an increase in carrier concentration. This phenomenon is attributed to the bulk trap density, in particular to oxygen vacancies. Negative bias stress tests confirmed the influence of the oxygen vacancies, with thicker channels showing more pronounced shifts. Low-frequency noise measurements were consistent with the carrier number fluctuation model, indicating that defects within the channel region contribute to the observed noise. The study concludes that identifying an optimal channel thickness during device manufacturing is crucial for improved TFT performance, with 20 nm devices characterized by high μFE and comparable trap density to 10 nm. This study provides valuable insight into the nuanced relationship between the channel thickness, trap density, and electrical performance of IWO TFTs. [ABSTRACT FROM AUTHOR]