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7 results on '"T. Mota Frutuoso"'

3. Methodology for Active Junction Profile Extraction in thin film FD-SOI Enabling performance driver identification in 500°C devices for 3D sequential integration

Author

T. Mota Frutuoso, X. Garros, P. Batude, L. Brunet, J. Lacord, B. Sklenard, V. Lapras, C. Fenouillet-Beranger, M. Ribotta, A. Magalhaes-Lucas, J. Kanyandekwe, R. Kies, G. Romano, E. Catapano, M. Casse, J. Lugo-Alvarez, P. Ferrari, F. Gaillard, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Reliable RF and Mixed-signal Systems (TIMA-RMS), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), and IEEE

Subjects
resistance, silicon-on-insulator, three-dimensional displays, VLSI (Very Large Scale Integration), PACS 85.42, capacitance, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, predictive models, performance evaluation
Abstract

International audience; We present, for the first time, a new CV based technique to extract the Active Dopant Profile under the spacer in thin film FDSOI devices (CV-AJP). The methodology is successfully applied to FDSOI devices fabricated at 500°C for 3D sequential integration. It shows that the ION/ IOFF trade-off relies mainly on the chemical dopant introduction below the offset spacer, as the activation level obtained with thermal activation is found to be high enough. The LT device demonstrated in this work, already outperforms the literature. The active profile extraction also allows to draw guidelines for further device performance improvement: using a scaled SiCO spacer (5,5nm) allows to circumvent the negligible dopant diffusion at 500°C without dynamic performance penalty due to its low-k dielectric value.

Published
2022

4. 3D sequential integration: applications and associated key enabling modules (design & technology)

Author

P. Batude, O. Billoint, S. Thuries, P. Malinge, C. Fenouillet-Beranger, A. Peizerat, G. Sicard, P. Vivet, S. Reboh, C. Cavalcante, L. Brunet, M. Ribotta, L. Brevard, X. Garros, T. Mota Frutuoso, B. Sklenard, J. Lacord, J. Kanyandekwe, S. Kerdiles, P. Sideris, C. Theodorou, V. Lapras, M. Mouhdach, G. Gaudin, G. Besnard, I. Radu, F. Ponthenier, A. Farcy, E. Jesse, F. Guyader, T. Matheret, P. Brunet, F. Milesi, L. Le Van-Jodin, A. Sarrazin, B. Perrin, C. Moulin, S. Maitrejean, M. Alepidis, I. Ionica, S. Cristoloveanu, F. Gaillard, M. Vinet, F. Andrieu, J. Arcamone, and E. Ollier

Published
2021

6. RF Performance of Devices Processed in Low-Temperature Sequential Integration

Author

Xavier Garros, Jose Lugo-Alvarez, Laurent Brunet, Perrine Batude, Christoforos G. Theodorou, P. Sideris, Philippe Ferrari, C. Fenouille-Beranger, T. Mota Frutuoso, F. Gaillard, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), and Université Grenoble Alpes (UGA)

Subjects
010302 applied physics, Coupling, Materials science, Transistor, 01 natural sciences, 7. Clean energy, Electronic, Optical and Magnetic Materials, law.invention, Threshold voltage, PMOS logic, [SPI.TRON]Engineering Sciences [physics]/Electronics, CMOS, law, Logic gate, 0103 physical sciences, Figure of merit, Radio frequency, Electrical and Electronic Engineering, Atomic physics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS, [PHYS.PHYS.PHYS-DATA-AN]Physics [physics]/Physics [physics]/Data Analysis, Statistics and Probability [physics.data-an]
Abstract

RF performance and intertier coupling of CMOS processed in 3-D sequential integration are investigated. pMOS transistor fabricated with a 500 °C thermal budget features good RF figures of merit with ${f}_{t} =105$ GHz and ${f}_{\text {max}} =175$ GHz for a gate length of 45 nm and ${V}_{\text {DD}} = -1$ V. Moreover, we demonstrate that the low- ${k}$ SiCO oxide spacer and low polysilicon gate resistance obtained with the low temperature process contribute to ${f}_{\text {max}}$ results that are better than high temperature process (above 1000°). Finally, we illustrate the crosstalk effects and the influence of the low-tier transistor gate voltage ${V}_{\text {G}}$ on the top-tier threshold voltage ${V}_{T}$ . We also show that a polysilicon ground shield integrated under the top-tier transistor substantially attenuates the intertier RF field coupling effects.

Published
2021

7. Impact of spacer interface charges on performance and reliability of low temperature transistors for 3D sequential integration

Author

F. Gaillard, C. Fenouillet-Beranger, X. Garros, Joris Lacord, Jose Lugo-Alvarez, Louis Gerrer, M. Casse, Philippe Ferrari, Laurent Brunet, E. Catapano, Francois Andrieu, and T. Mota Frutuoso

Subjects
Materials science, Silicon, business.industry, Interface (computing), Transistor, Oxide, chemistry.chemical_element, Silicon on insulator, Temperature measurement, law.invention, chemistry.chemical_compound, Reliability (semiconductor), chemistry, law, Optoelectronics, Degradation (geology), business
Abstract

The impact of interface charges under the gate spacer on FDSOI devices integrated in low temperature process are explored. A great number of traps (~1013/cm2) are identified on the interface between the spacer oxide and the silicon film using Terman's method for interface states characterization. Thanks to electrical characterization and TCAD simulations, it is shown that the trapped charges induce the formation of a depleted region in the vicinities of the spacer. Moreover, a strong degradation of performances on underlap channels is observed. The spacer charges influence on reliability measurements is finally explored.

Published
2021

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