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Due to the complexity of device processing, the trade-off between yield and area has resulted in diminishing rate of scaling for the high-density static random access memory (SRAM) cell at advanced CMOS nodes. An introduction of extreme ultraviolet (EUV) and multipatterning has added additional cost to technology in order to realize 3-D device structure and ultrascaled metal routing. In this era, spin-transfer torque (STT)-MRAM technology can provide an alternative to high-density SRAM and for the last level cache (LLC) applications. In this article, we discuss the memory design and technology tradeoff to enable the STT-MRAM as a viable option. We have realized the technology over 300-mm wafer, measuring 1 million samples to build a SPICE model for circuit simulation. Occupying up to 83.3% of an area that of SRAM macro has been designed and simulated for the scaled 5-nm CMOS node. The simulated MRAM macro shows the best read and write access time of 3.1 and 6.2 ns, respectively. Magnetic tunneling junction (MTJ) pillar of 38-nm diameter is realized at 90-nm pitch, measuring resistance area (RA) of 5.2- $\Omega \cdot \mu \text{m}^{2}$ , ${J}_{sw}$ of 5.5 MA/cm2 with improved $\Delta $ avg of 70, and breakdown voltage of 0.99 V. The energy comparison shows increasing gains versus SRAM for the increasing cache sizes crossing over at of 0.3 and 4 MB for the single-cycle read and write operations, respectively.

Spin Transfer Torque Magnetic RAM (STT-MRAM) is being extensively considered as a promising replacement for Last Level Caches (LLC), due to its high density, low leakage and non-volatility. However, writes to STT-MRAM are energy intensive and have a high latency. While the high dynamic energy consumption during writes can be compensated by the low static energy consumption, the high latency results in performance degradation. This work shows that in contrast to SRAM-based LLCs, the performance degradation for STT-MRAM is primarily due to bank contention, when trying to satisfy a read request while the bank is being written. We holistically explore the effects of cache banking and cache contention on energy and performance in the LLC of mobile multicore systems, with in-order cores or with out-of-order cores. The detail of the analysis is enabled by highly accurate cache models, based on a 28nm SRAM industry compiler, and an in-house developed STT-MRAM compiler, which generates full STT-MRAM macro designs with silicon-validated MTJ stack and complete parasitic extraction at the 28nm node. Our results show that there is a clear difference in the energy-performance optimal banking configuration between STT-MRAM caches and SRAM caches. These low contention STT-MRAM cache designs with the optimal number of banks save at least 60% cache energy while losing at most single digit percentages in system performance compared to SRAM cache designs. This show an increased potential of using STT-MRAM as a replacement for SRAM in an LLC.

The increased complexity of CMOS transistor processing has led to limited scaling of high density SRAM cell at advanced technology nodes. STT-MRAM appears to be a promising candidate for replacing last level caches (LLC). This paper addresses design technology co-optimization (DTCO) of STT-MRAM technology and analyzes its viability as a LLC (compared to SRAM) for the high performance computing (HPC) domain (while maintaining a constraint of occupying merely 43.3% of SRAM macro area at identical capacities). This is the first study that breaks down a power, performance and area (PPA) comparison between SRAM and STT-MRAM based LLCs at the 5nm node. The STT-MRAM design and analysis is based on a silicon verified compact model and can be realized using 193i single patterning at the 5nm node. Our STT-MRAM design manages to achieve a nominal access latency

For the first time, we present complete device threshold voltage (VT)-targeting methodology for FinFET SRAM in 10-nm technology, considering capacitance due to metal pattering and device variability to set target read current for different variants of SRAM architecture to determine technology high-density (HD) SRAM cell. The VT-targeting methodology brings into play the worst case read and write margins available for SRAM cell to determine nominal device VT by tuning the work function of metal gate. Analysis shows that for minimum leakage current, 112 SRAM cell is optimum, whereas for the same area of $0.0546~\mu $ $\mathrm{m}^{\mathrm {2}}$ with 50% higher leakage, 122 SRAM outperform by 5% and 20% improved read and write margins, respectively. The 122 SRAM as HD cell reduces the cost of the technology by sharing P-channel field effect transistor (PFET) and N-channel field effect transistor (NFET) VT mask with the high threshold voltage logic devices, whereas the 112 SRAM device shares only NFET VT mask. The 111 SRAM can achieve target performance at lesser area of $0.048~\mu $ $\mathrm{m}^{\mathrm {2}}$ by compromising read stability, which will result in lower yield. At 64-nm pitch, litho-etch litho-etch (LELE) double-patterned gate impacts device performance and alleviates variability; hence the read margin of SRAM cell should consider an additional $1\sigma _{\mathrm {\mathbf {rsnm}}}$ margin to retain the same yield in 10-nm-technology era.

For the first time, we report on 400°C compatible top-pinned perpendicular magnetic tunnel junction (MTJ) stacks with dual MgO free layer for STT-MRAM applications. Using a texture-inducing parallel-coupling barrier layer (TICPB), we enforce the pinning layer and control diffusion, which enables BEOL compatibility while keeping TMR as high as 184%. In addition, we demonstrate that using such synthetic ferro-magnetic stack (SFM) design with TICPB layer allows a free layer off-set control and a switching current of 3.8 MA/cm2 in 25 nm e-CD devices.

STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory) has attracted considerable attention of late since it is the most promising logic compatible nonvolatile memory that is suitable for advanced logic nodes (N28 and beyond) in terms of endurance, speed and power. Embedded STT-MRAM has thus been proposed as a candidate for emerging low standby-power connectivity systems such IoT (Internet-of-Things) and wearables. We utilize the high performance CoFeB based perpendicular MTJ (pMTJ) device to realize a low power and highly dense STT-MRAM array for such systems. This study is carried out on the TSMC 28nm technology node and includes a complete cross-layer design and analysis framework ranging from device modeling to circuit design, layout and system implementation. The process variations and temperature (PT) impact on the MTJ for the STT-MRAM design (and correspondingly the total energy consumption and performance of the system) is also analyzed. We report a ∼85% reduction in the energy consumption compared to the baseline SRAM based system for near negligible performance penalty (

The rising demand for battery-powered devices is the key driver for continued density scaling and improved power in SoCs. Along with advantages, random V T variation and interconnect RC delay is increased due to the continual scaling of physical dimensions, which seriously degrades SRAM performances, limits V MIN , and makes SRAM less energy efficient. Although FinFET technology can offer a respectable source channel effects (SCEs) and superior V T variation, the competing between channel length (Lg), sidewall spacers, and source/drain (S/D) contacts imposed by contacted gate pitch (CGP) scaling remains unchanged. In this paper, we will present a holistic approach for 6T-SRAM designs using gate-all-around (GAA) transistors, which will firmly address process integrations and circuit aspects arising at the 5nm node. Several read and write assist techniques including wordline (WL) delayed overdrive, VDD collapse and negative bitline (BL) will be exclusively investigated to enable low V MIN and high-performance SRAMs.

In this paper, we present a layout and performance analysis of logic and SRAM circuits for vertical and lateral GAA FETs using 5nm (iN5) design rules. Extreme ultra-violet lithography (EUVL) processes are exploited to print the critical features: 32 nm gate pitch and 24 nm metal pitch. Layout architectures and patterning compromises for enabling the 5nm node will be discussed in details. A distinct standard-cell template for vertical FETs is proposed and elaborated for the first time. To assess electrical performances, a BSIM-CMG model has been developed and calibrated with TCAD simulations, which accounts for the quasi-ballistic transport in the nanowire channel. The results show that the inbound power rail layout construct for vertical devices could achieve the highest density while the interleaving diffusion template can maximize the port accessibility. By using a representative critical path circuit of a generic low power SoCs, it is shown that the VFET-based circuit is 40% more energy efficient than LFET designs at iso-performance. Regarding SRAMs, benefits given by vertical channel orientation in VFETs has reduced the SRAM area by 20%~30% compared to lateral SRAMs. A double exposures with EUV canner is needed to reach a minimum tip-to-tip (T2T) of 16 nm for middle-of-line (MOL) layers. To enable HD SRAMs with two metal layers, a fully self-aligned gate contact for LFETs and 2D routing of the top electrode for VFETs are required. The standby leakage of vertical SRAMs is 4~6X lower than LFET-based SRAMs at iso-performance and iso-area. The minimum operating voltage (Vmin) of vertical SRAMs is 170 mV lower than lateral SRAMs. A high-density SRAM bitcell of 0.014 um2 can be obtained for the iN5 technology node, which fully follows the SRAM scaling trend for the 45nm nodes and beyond.

In this paper, we present an intensive study of 6T-SRAM designs for vertical gate-all-around (GAA) transistors (VFETs) and lateral GAA transistors (LFETs) using 5-nm node design rules. Optimizations of the nanowire (NW) diameter and the gate length are also conducted to enhance the SRAM performance. Device $V_{T}$ retargeting has been proposed for improving the minimum operating voltage ( $V_{\min }$ ) of SRAMs. The isoperformance and isoyield have been performed to assess and determine the benefits provided by LFET and VFET architectures, respectively. Our results show that the VFET bitcells are denser than the LFET bitcells by 20%–30%. The SRAM read stability (read static noise margin) is significantly improved using the NW channel. For a $6\sigma $ yield target and an isoarea of SRAM bitcells, $V_{\min }$ of the VFET bitcell is 80 mV lower than LFET designs. Applying the proposed $V_{T}$ retargeting technique can allow the VFET 122 bitcell to operate at 0.57 V without using assist circuits. A standby leakage below 10 pA/cell can be achieved for both architectures. At isoperformance, the standby leakage of VFET bitcells is $2.6\times $ lower than LFET bitcells.

This paper presents a comprehensive benchmarking and co-optimization of 6T SRAM bitcells designed with 5nm vertical and lateral gate-all-around nanowire FET technology for the first time. A variety of 6T SRAM bitcells configurations combined with different device integration scenarios will be discussed. Our results show that an ultra-dense SRAM bitcell (0.01 um2) can be achieved with vertical FET architecture. The bitcell designed with vertical FET are preferably targeted for low power applications while the lateral FET-based SRAM bitcells could provide 4.5x higher in performance, but resulting in a penalty of 17x increasing in the leakage current compared to the vertical designs. A Vmin of 0.45 V could be obtained for 122 SRAM bitcells implemented with vertical devices.

At 7nm and beyond, designers need to support scaling by identifying the most optimal patterning schemes for their designs. Moreover, designers can actively help by exploring scaling options that do not necessarily require aggressive pitch scaling. In this paper we will illustrate how MOL scheme and patterning can be optimized to achieve a dense SRAM cell; how optimizing device performance can lead to smaller standard cells; how the metal interconnect stack needs to be adjusted for unidirectional metals and how a vertical transistor can shift design paradigms. This paper demonstrates that scaling has become a joint design-technology co-optimization effort between process technology and design specialists, that expands beyond just patterning enabled dimensional scaling.

Vertical nanowire logic circuits may enable device density scaling well beyond lateral CMOS layouts limited by gate and contact placement. In this paper, we compared the performance, layout efficiency, SRAM design, and parasitics between vertical (VFETs) gate-all-around (GAA) transistors with lateral (LFETs) targeting 5nm. We reviewed some of the unique considerations of VFET device and circuit influences.

The density requirement expected for the 10nm node continues to increase the pressure on patterning. With the frontend of line adopting a regular layout (mostly unidirectional), most of the complexity needed for a functional chip ends up in the interconnect layer and Metal1. Assuming that Extreme Ultra Violet Lithography (EUVL) will not be ready for the early stage of 10nm production but only for high volume manufacturing, we have studied how ArF immersion lithography can be extended for Metal1 to sustain the development of the technology as well as the early production phase, while at the same time remaining compatible with an EUVL single patterning solution. We show how close interaction between design, process and computational lithography leads to a Metal1 triple patterning solution using Negative Tone Development (NTD), and how the same design solution can be supported by EUVL single patterning. Particular attention will be paid to line end printability performance, both tip to tip and tip to line, as we believe it is a key parameter to define the best compromise between lithography performance and design density.

Design-Technology co-optimization becomes a key knob to enable CMOS scaling. In this work we evaluate the technology options including lithography options as well as device options that are considered to enable N10 scaling by exploring their impact on representative designs such as standard cells, SRAM and analog contexts. This paper illustrates that the design angle needs to be considered early in the development of a technology node. This design assessment and decisions start from lithography constraints and options to power/performance, area and cost, all of which create the Design-Technology Co-Optimization space.

International audience; Current main memory organizations in embedded and mobile application systems are DRAM dominated. The ever-increasing gap between today's processor and memory speeds makes the DRAM subsystem design a major aspect of computer system design. However, the limitations to DRAM scaling and other challenges like refresh provide undesired trade-offs between performance, energy and area to be made by architecture designers. Several emerging NVM options are being explored to at least partly remedy this but today it is very hard to assess the viability of these proposals because the simulations are not fully based on realistic assumptions on the NVM memory technologies and on the system architecture level. In this paper, we propose to use realistic, calibrated STT-MRAM models and a well calibrated cross-layer simulation and exploration framework, named SEAT, to better consider technologies aspects and architecture constraints. We will focus on general purpose/mobile SoC multi-core architectures. We will highlight results for a number of relevant benchmarks, representatives of numerous applications based on actual system architecture. The most energy efficient STT-MRAM based main memory proposal provides an average energy consumption reduction of 27% at the cost of 2x the area and the least energy efficient STT-MRAM based main memory proposal provides an average energy consumption reduction of 8% at the around the same area or lesser when compared to DRAM.

The Fin-FET Technology scaling to sub 7nm node, using 193 immersion scanner is restricted due to reduced margins for process. The cost of the process and complexity of designs is increasing due to multi-patterning to achieve area scaling using 193i scanner. In this paper, we propose a two Fin-cut mask design for Fin-pattering of 112 SRAM (two Fins for pull-down and one Fin for pull-up and pass-gate device) cell using 193i lithography and its comparison with EUVL single print. We also propose two keep masks for middle of line patterning ,with increased height of the SRAM cell using 193i, that results in area of a uniform-Fin SRAM cell area at 7nm technology; whereas EUVL can enable non-uniform SRAM cell at reduced area. Due to unidirectional patterning, margins for VIA0 landing over MOL are drastically reduced at 42nm gate pitch and hence to improve margins, the orientation for 1st metal is proposed to be orthogonal to the gate. This results in improved performance for SRAM and reliability of the technology.