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A 512K*8 flash EEPROM (electrically erasable programmable ROM) which operates from a single 5-V supply was designed and fabricated. A double-poly, single-metal CMOS process with a minimum feature size of 0.9 mu m was developed to manufacture the test vehicle, which resulted in a die size of 95 mm/sup 2/. The storage cell is 8.64 mu m/sup 2/ and consists of a one-transistor cell that uses a remote, scalable, tunnel diode for programming and erasing by Fowler-Nordheim tunneling. Process high-voltage requirements are relaxed by utilizing circuit techniques to alleviate the burden of high voltages. A segmented architecture provides the flexibility to erase any one sector (16 kB) or the entire chip during one cycle by an erase algorithm. The memory can be programmed one byte at a time, or the internal bit-line latches can be used to program a 256-B page in one cycle. A programming time of 10 ms is typical, which results in a write time of 40 mu s/B during page programming. The chip features an access time of 90 ns. >

The authors describe a 256-kbit flash EEPROM (electrically erasable and programmable read-only memory) device which requires only 5 V for program, erase, and read operations and has performance and cost comparable to that of the recently reported dual-power-supply flash EEPROMs, which require 12 V for programming and erase and 5 V for read. The memory cell consists of a floating-gate transistor and a merged-pass-gate transistor. The process is array-contactless EEPROM (ACEE), with buried source/drain for the bit lines with a tunnel oxide module and a 20-V CMOS module. The program and erase operations employ the Fowler-Nordheim current tunneled through 100-AA oxide when the proper electrical voltages are applied to the selected bit. The device and technology parameters are summarized. >

A novel tunnel diode has been developed for high-density 5-V-only flash memories. The memory tunnel diode is remote from the channel, self-aligned, sublithographic, and scalable. This remote tunnel diode provides several advantages over a conventional tunnel diode: higher junction breakdown voltage, reduced substrate current during erase, reduced tunnel oxide area, reduced cell area, and competitive cell endurance. A 256-kb 5-V-only flash memory incorporating this tunnel diode is shown to have excellent operation and reliability characteristics. >

A full 4-Mb flash EEPROM was fabricated in 0.8-mm CMOS and its functionality was verified. Conservative 1.0-mm features were used in the periphery, resulting in a die area of 95 mm2. The device features 5-V-only operation and either full-chip or sector erase. A segmented architecture, remote row decode, and innovative design techniques provide the sector erase feature and high-voltage handling with improved breakdown protection and isolation

A single-transistor advanced contactless EEPROM (ACEE) array technology with an 8.6 mm2 cell developed for a single-power-supply 5-V only 4-Mb flash EEPROM is described. This ACEE technology has 0.8 mm minimum lithographic feature sizes and a novel sublithographic remote tunnel diode structure. Low-voltage isolation between bitlines of the same cell has been achieved by diode isolation at an effective separation of 0.65 mm; the high-voltage isolation between bitlines of adjacent cells depends on LOCOS isolation. The integrated process flow has successfully merged both the ACEE array and process enhancements for 18-V operation (2.0 mm, 18 V N-channel, 15 V P-channel) into a core 5-V 0.8 mm CMOS process with silicided contacts. This cell has been demonstrated on a full-circuit 4-Mb flash EEPROM VLSI vehicle

A one megabit CMOS EPROM with a Floating gate Avalanche injection MOS (FAMOS) cell area of 8.6 µm2has been fabricated at a conservative design rule of 1.2µm This cell, to our knowledge, is the smallest reported EPROM cell. The process utilized an Advanced Contactless EPROM (ACE) technology combined with a High Voltage Enhanced Performance Implanted CMOS (HVEPIC) technology. The combined technique has produced fully functional one MBIT EPROMs with high density (bar size= 35.5 mm2of 55 Kmil2) and enhanced performance (130 ns access time) The HVEPIC/ACE technology features twin well CMOS, buried N+ bitlines, ultra-smooth polysilicon floating gates, oxide-nitride-oxide inter-polysilicon dielectric, double level polysilicon, single level metal, self-aligned TiSi2 and a post source/drain anneal processing temperature limited to 800°C.

A CMOS contactless cell array technology has been developed for a single-power-supply high-density, five-V-only flash memory and for system programmable IC applications. The technology's suitability for VLSI memories has been demonstrated by a 256-kb flash EEPROM (electronically erasable programmable read-only memory) chip. This low-current five-V-only approach has been proved, with cell area and cost comparable to recently reported high-current dual-power-supply flash EEPROMs

A revolutionary EPROM cell technology has been developed. Its suitability to realize high density memories with performance and reIiability comparable to the conventional EPROMS has been demonstrated with a 64K bit density vehicle. This self-aligned contactless cell is in a crosspoint array configuration, and occupies 33 percent less area than a conventional cell at comparable design rules. The planar, contactless technology has enhanced manufacturability, scalability and is ideally suited for memories beyond megabit density.