17 results on '"Suhard S"'
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2. Novell embedded microbump approach for die-to-die and wafer-to-wafer interconnects with variable microbump diameters and down to 5 um interconnect pitch scaling
3. A record GmSAT/SSSAT and PBTI reliability in Si-passivated Ge nFinFETs by improved gate stack surface preparation
4. Development of an all-in one wet single wafer process for 3D-SIC bump integration and its monitoring
5. Integrated clean for TSV: Comparison between dry process and wet processes and their electrical qualification
6. Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells
7. 3D integration challenges for fine pitch back side micro-bumping on ZoneBOND™ wafers
8. Integration of the ZoneBOND™ temporary bonding material in backside processing for 3D applications
9. Perfluoroalkylated Polymer-Supported Palladium Catalyst
10. Integration and dielectric reliability of 30nm ½ pitch structures in Aurora ®LK HM
11. Challenges and novel approaches for photo resist removal and post-etch residue removal for 22 nm interconnects
12. Integration of 20nm half pitch single damascene copper trenches by spacer-defined double patterning (SDDP) on metal hard mask (MHM).
13. Wetting performance on patterned substrates : experimental and numerical study
14. Gate-last vs. gate-first technology for aggressively scaled EOT logic/RF CMOS.
15. Perfluoroalkylated Polymer-Supported Palladium Catalyst.
16. Heterometallic Werner complexes as energetic materials.
17. Sterically-controlled regioselective para-substitutions of aniline.
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