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We evaluate the total ionizing dose (TID) responses of InGaAs nMOS FinFETs with different gate lengths irradiated with 10-keV X-rays under different gate biases. The largest degradation after irradiation occurs at $V_{\mathrm {G}} = -1$ V. Radiation-induced trapped positive charge dominates the TID response of InGaAs FinFET transistors, consistent with previous results for InGaAs multifin capacitors. Shorter gate-length devices show larger radiation-induced charge trapping than longer gate-length devices, most likely due to the electrostatic effects of trapped charge in the surrounding SiO2 isolation and SiO2/Si3N4 spacer oxides. The 1/ $f$ noise measurements indicate a high trap density and a nonuniform defect-energy distribution, consistent with a strong variation of effective border-trap density with surface potential.

In this work, we discuss how the insertion of a LaSiOx layer in between an in-house IL passivation layer and the high-k has moved the III-V gate stack into the target window for future technology nodes. The insertion of this LaSiOx layer in the gate stack has reduced the Dit and Nbt below the target level of 5×1011 /eV.cm2 and 3×1010 /cm2 (target at 10 years operation: ΔVfb

We use capacitance–frequency ( $C$ – $f$ ) measurements to provide lower bound estimates of border-trap densities in multifin MOS capacitors with high-K dielectrics built in Ge and InGaAs fin field effect transistor (FinFET) technologies before and after X-ray irradiation. The $C$ – $f$ method is illustrated for SiO2-based planar MOS capacitors and compared with high-frequency capacitance–voltage measurements. Lower effective border-trap densities are found before and after irradiation for multifin capacitors built in a strained Ge $p$ MOS FinFET technology than for similar devices built using an early-developmental stage InGaAs MOS technology. These results show the utility of $C$ – $f$ measurements in characterizing defect densities in MOS capacitors, particularly when large border-trap densities exist.

This letter proposes a metric to assess the quality of high-k dielectrics on III–V substrates and a benchmarking methodology for the gate stack qualification in the region of MOS device operation above threshold voltage, ${V}_{t}$ . The metric is based on a capacitive equivalent thickness (CET) - normalized frequency dispersion ( $\text{D}_{\mathrm {eff}}$ ) evaluated in the accumulation region of capacitance–voltage (C–V) measurements of III–V MOS devices. ${D} _{\mathrm {eff}}$ is found to be CET independent, which allows for a preliminary assessment of the dielectric quality by using relatively thick layers. Several gate stacks, single layer or bi-layer, including those with Al2O3, and the recently reported ASM-imec interfacial layer (IL) with HfO2 are evaluated and compared against Si MOS devices. Using the proposed technique, a clear difference between the various deposition processes is observed. The results indicate that the quality of a single layer Al2O3 or a bi-layer stack of Al2O3/HfO2 on InGaAs is significantly lower compared with Si gate stacks while the ASM-imec IL yields a gate-stack with good performance on the proposed quality metric. In addition, these results correlate well with the reliability performance of the studied gate stacks.

We present a review of our recent studies of Bias Temperature Instability (BTI) in Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) fabricated with different material systems, highlighting the reliability opportunities and challenges of each novel device family. We discuss first the intrinsic reliability improvement offered by SiGe and Ge p-channel technologies, if a Si cap is used to passivate the channel, in order to fabricate a standard SiO2/HfO2 gate stack. We focus on SiGe gate stack optimizations for maximum BTI reliability, and on a simple physics-based model able to reproduce the experimental trends. This model framework is then used to understand the suboptimal BTI reliability and excessive time-dependent variability induced by oxide defect charging in different high-mobility channel gate stacks, such as Ge/GeOx/high-k and InGaAs/high-k. Finally we discuss how to pursue a reduction of charge trapping in alternative material systems in order to boost the device reliability and minimize time-dependent variability.

Charge trapping in the gate-oxide can cause significant degradation and reduce the operating lifetime of the device. Here, we study the kinetics of charge trapping in the InGaAs/Al 2 O 3 /HfO 2 gate-stack using Capture and Emission Time (CET) maps. The existence of two oxide defect bands, respectively above and below the conduction band of InGaAs, is implied by sensing charge trapping at positive and negative oxide electric fields. Within each band, two distinct populations of defect states are observed. The first defect population with relatively higher capture and emission energy barriers is found to affect the long term reliability of the device since the charge trapping in these defect states is slow, while the second population with relatively smaller capture and emission energy barriers affects the device stability particularly under high frequency operation. We argue that it is essential to characterize and study both defect populations in order to accurately estimate device lifetime under different operating applications.

We review our recent studies of oxide traps in InGaAs MOS gate stacks for novel high-mobility n-channel MOSFETs. We discuss and correlate various trap characterization techniques such as Bias Temperature Instability, defect Capture-Emission-Time maps (applied here to InGaAs devices), Random Telegraph Noise, hysteresis traces, multi-frequency C-V dispersion, all performed on a variety of device test vehicles (capacitors, planar MOSFETs, finFETs, nanowires). Finally we demonstrate guidelines for developing sufficiently reliable IIIV gate stacks.

Graphical abstractDisplay Omitted Charge traps in (100)Ge/Sc2O3/HfO2 stacks are studied by ESR and electrical probing.The utility of Sc2O3 as passivation layer on Ge is studied by conventional ESR.Trapping centers in (100)Ge/Sc2O3 entities are tracked by ESR as g=2.0017 defects.Defect generation in (100)Ge/Sc2O3 entities may be suppressed by sufficient supply of O2.Oxygen deficiency causes thermal degradation of (100)Ge/Sc2O3/HfO2 stacks. The usefulness of employing the rare-earth Sc2O3 high-? (~16) dielectric in passivating Ge surfaces for metal-oxide-semiconductor device application is studied in terms of occurring inherent paramagnetic point defects, operating as detrimental charge traps. To assess their atomic nature, low temperature K-band electron spin resonance (ESR) experiments have been carried out in combination with electrical probing, including capacitance-voltage, internal photoemission and photoconductance observations, on (100)Ge/(GeO2)/Sc2O3/HfO2 stacks grown by atomic layer deposition subjected to various processing steps. In stacks with Ge directly contacted with Sc2O3, without an additional O-supply processing step, ESR reveals the presence of a prominent signal of powder pattern shape, centered at g=2.0017(2). It is ascribed to O-deficiency centers located in the Sc2O3-based dielectric, which from combined electrical analysis are concluded to be at the origin of substantial electron trapping (~6i?1012cm-2) in near-interfacial layers. Generally, the data suggest that O-deficiency caused by oxidation of Ge (O-scavenging) emerges as a crucial parameter in defect generation, leading to the conclusion that the suppression of defect generation will require a sufficient supply of oxygen during critical manufacturing steps.

The gate-stack quality of planar MOSFETs fabricated in Ge-on-Si substrates and passivated by a GeO x interfacial layer is evaluated by low-frequency noise analysis. It is shown that for both n- and p-channel transistors predominantly 1/ $f^{\gamma }$ noise ( $\gamma \sim 1$ ) has been observed, which originates from number and correlated mobility fluctuations. The oxide trap density and mobility scattering coefficient derived from the input-referred voltage noise power spectral density are demonstrated to be significantly higher for nMOSFETs than for pMOSFETs with the same gate-stack, which explains the low electron mobility.

In this paper, we demonstrate for the first time an implant free In 0.53 Ga 0.47 As n-MOSFET that meets the reliability target for advanced technology nodes with a max operating V ov of 0.6 V. In addition, an excellent electron mobility (μ eff, peak =3531 cm2/V-s), low SS lin =71 mV/dec and an EOT of 1.15 nm were obtained. We also report the scaling potential of this stack to 1nm EOT without loss of performance, reliability and further reduction of the sub-threshold swing (SS lin =68mV/dec). On top of the novel IL we presented last year, in this paper we insert a LaSiO x layer between the IL and HfO 2 offering an increased chemical stability of the gate stack. This combination is key and offers both an improved interface quality as well as a reduction of the oxide trap density.

3D Sequential integration has been envisioned to stack transistors in the same front-end process. A crucial challenge is the management of the thermal budget. This work focuses on Si nMOS gate stack challenges, specifically: for a top tier device, by inserting a thin LaSiO x interlayer between SiO 2 and HfO 2 a sufficient PBTI reliability is demonstrated without resorting to unsuitable high temperature anneals. This gate stack also offers good thermal stability for a pMOS over nMOS scenario.

In this work, we show that the reliability of InGaAs channel MOS devices not only depends on density of shallow defect states (i.e., electron traps responsible for PBTI in Si devices), but it is also governed by the density of deep defect states. This limits the operating range of the device. We conclude that it is necessary to characterize both shallow and deep defect densities in order to determine the total operating window (i.e., maximum underdrive and overdrive) of III-V devices for future technologies. We also show that a gate-stack comprising of a new ASM interface layer (ASM-IL), a LaSiO x interlayer and high-k dielectric can achieve the required reliability targets for a low power technology such as III-V.

Deep level traps in lattice-matched In 0.47 Ga 0.53 As epitaxial layers grown by MBE on InP substrates have been studied by Deep Level Transient Spectroscopy (DLTS) on Al 2 O 3 /InGaAs Metal-Oxide-Semiconductor (MOS) capacitors. The impact of different surface passivation steps and a post-gate-deposition Forming Gas Annealing (FGA) has been studied. It is shown that spectra are dominated by a near mid gap electron trap in the depletion region, with activation energy in the range 0.37 eV to 0.42 eV. At the same time, a broad background distribution of interface states is found as well, which is significantly reduced by the FGA. Detailed carrier trapping studies have been carried out to identify the origin of the grown-in electron traps, which are shown to be of point defect behavior.

We demonstrate a Si-passivated Ge nMOS gate stack with Dit of ∼5×1010 cm−2eV−1 around midgap and unnoticeable C-V hysteresis at an operating condition (oxide trap density of ∼1×108 cm−2 at V ov /CET=3.5 MV/cm). Insertion of a 3D-compatible thin ALD LaOx, MgOx and LaSiO layer at the interface between HfO2 and SiO2/Si/Ge improves PBTI reliability thanks to the interface dipole-induced band engineering. The high DIT of Si-passivated Ge nFET is dramatically reduced by ∼40x around midgap using a combination of the LaSiO insertion and a H2 high-pressure anneal (HPA). These key gate stack technologies realize further improvements in mobility (∼50% at peak) and PBTI reliability (V ov =0.32 V for 10 years) of Si-passivated Ge nFETs.

Si cap passivation on Ge shows low border trap response.The Si cap passivation is also suitable for Ge nMOS applications.Low Dit at Ec can be achieved by tuning the amount of Si at the interface.A dry O3 process can be used to control the amount of Si that is oxidized. One route to passivate the Ge/high-? interface is by depositing an epitaxial Si layer on the Ge surface. Subsequently, the Si layer is partially oxidized and a high-? layer is deposited on top. This passivation scheme has proven its efficiency over the last decade for pMOS applications. However, in this paper we demonstrate that this route can also be used for nMOS applications depending on the amount of Si left after the oxidation process. Moreover, the amount of border traps extracted from low frequency capacitance-voltage measurements is low, in contrast to what has been reported on GeO2 passivation. GeO2 passivation results in very low Dit levels at the conduction band edge. Therefore, GeO2 has been put forward as a good candidate for nMOS but it suffers from border traps in the oxide. Si cap passivation can solve both problems: Dit at the interface as well as the border traps in the oxide.

Since the last decade there has been renewed interest in Ge-based technologies for deep submicron CMOS technologies. Whereas good performance data has been reported for p-channel MOSFETs this was not the case for the n-channel counterpart. This manuscript first reviews some key technological aspects for Ge processing, before outlining the status and trends for p-and n-channel Ge MOSFETs in relation to the ITRS specifications. Special attention will be given to GeSn technologies.

The effective passivation of germanium surfaces and interfaces has been claimed to be the key to a substantial progress in developing Ge-based microelectronic devices. This paper compares the currently most promising passivation routes, i.e. oxidation and sulfidation, focusing on the underlying atomic scale processes and highlighting similarities and discrepancies between both approaches. The effect of oxidation and sulfidation on electrically active defects is addressed, and the chemical and structural properties of the passivated surfaces are described in detail.

This paper aims at reviewing the state-of-the art of Ge pMOSFETs for future high-performance CMOS devices. Key in the development is the integration of a Ge channel on a silicon platform and the passivation of the interface between the high-k gate stack and the substrate. The different routes will be critically discussed in view of optimizing the on-current related to a high low-field hole mobility and reducing the off-current and the short-channel effects. Finally, an outlook on future technology developments will be formulated.

We have shown that the poor PBTI reliability of IIIV/high-k gate stacks is universally related to process thermal budget limitations. Low temperature anneal optimization and high-k nitridation reduce oxide defect density. In contrast to a wide distribution of defect levels in Al 2 O 3 , HfO 2 on InGaAs shows a minimum defect density ∼0.2eV below the channel E C . By introducing an interface dipole, a significant reliability boost was demonstrated. While low thermal budget high-k quality and IIIV interface thermal stability constitute challenges, our results show that a reliable IIIV/high-k gate stack can be fabricated.

We report In 0.53 GaAs-channel gate-all-around FETs with channel width down to 7nm and L g down to 36nm, the smallest dimensions reported to date for IIIV devices fabricated on 300mm Si wafer. Furthermore, we systematically study the device scalability. InGaAs S/D improves the peak g m by 25% compared to InAs S/D. A g m of 1310 µS/µm with an SS sat of 82mV/dec is achieved for an L g =46nm device. At this L g , a record I on above 200µA/µm is obtained at I off of 100nA/µm and V ds =0.5V on a 300mm Si platform.

For the first time, two different types of electron traps are clearly identified in Ge nFETs with Type-A controlled by the HfO 2 layer thickness and Type-B by the Si growth induced Ge segregation. Only Type-B are responsible for mobility degradation and they do not saturate with stress time, while the opposite applies to Type A. A PBTI model is proposed and validated for the long term prediction.

Germanium is considered to be a potential semiconductor to replace silicon in future high-performance microelectronic devices. Yet, when compared to Si, very little is known about the surface chemistry of Ge surfaces. In this article, we report on the oxygen adsorption on Ge(100)-(2 × 1) surfaces and the related changes in the density of surface states. In particular, the adsorption geometry is examined both in reciprocal- and real-space using reflection high-energy electron diffraction and scanning tunneling microscopy, respectively. Our findings reveal that the insertion of oxygen atoms into the Ge backbonds is not favored under the investigated reaction conditions, i.e., at a moderate O2 exposure. The O2-exposed surface exhibits a local (1 × 1) surface reconstruction, which implies that dimer bonds are destroyed upon oxygen adsorption. Surface states related to Ge dangling surface bonds present on the clean Ge(100) surface are found to be passivated. In addition, a high density of expelled substrate at...

The last decennia, a lot of effort has been made to introduce new channel materials in a Si process flow. High mobility materials such as Ge need a good gate stack passivation in order to ensure optimal MOSFET operation. Several routes for passivating the Ge gate stack have been explored in the last years. We present here the S-passivation of the Ge gate stack: (NH4)2S is used to create a S-terminated Ge surface. In this paper the S-treatment is discussed. The S-terminated Ge surface is not chemically passive but can still react with air. After gate oxide deposition, the Ge-S bonds are preserved and an adequate passivation is found for pMOS operation.

Monolayer-Si-passivated Ge nFETs with high electron mobility (175 cm2/Vs at Ns=5×1012 cm−2) and superior PBTI reliability (max. Vov = |Vg-Vth| of 0.28V at 125°C) at 0.95-nm-EOT are demonstrated on a 300 mm Si wafer platform. The electron mobility is increased by optimizing the Si thickness while significant improvement in PBTI reliability is realized by band engineering using La-induced interface dipole and defect passivation using laser annealing. This is a significant step forward for the introduction of Ge nFET as high mobility device in advanced technology nodes.

We report record results for III-V gate-all-around devices fabricated on 300mm Si wafers. A gm of 2200 μS/μm with an SSsat of 110 mV/dec is achieved for an Lg=50nm device using a newly developed gate stack interlayer material deposited by ALD. In addition it is shown that high pressure annealing can further improve device performance with an average increase in gm of 22% for a 400 °C anneal.

In this paper we present the study of the S-passivation of the Ge gate stack. S-passivation was achieved by using H"2S exposure on the clean Ge(100) surface. Al"2O"3 was deposited on the Ge/S surface by atomic layer deposition (ALD). The resulting gate stacks were analyzed chemically and electrically. We studied the influence of the ALD oxidant precursor (H"2O versus O"3) on the passivation behavior of the gate stack. We observe that for the same surface passivation, the interface depends largely on the oxidant precursor: H"2O as a precursor results in a gate stack free of Ge-oxide and the gate stack shows low D"i"t at the valence band edge. On the other hand, O"3 as a precursor results in a thin GeO"xS"y interfacial layer with low D"i"t at the mid gap and conduction band edge.

A critical issue for the successful integration of Ge devices into future high-performance technology nodes is the electrical passivation of the Ge surface. We have examined this electrical passivation in terms of interface and border traps for several Ge-based gate stacks, where we varied amongst others the GeO2 thickness, the high-k material and the Post Deposition Anneal (PDA). The GeO2 thickness seems to have the largest impact, and an inverse relation between the density of interface traps Dit and border traps Nbt exists for GeO2 layers up to ~2 nm. We found that the most optimal passivation is achieved by using an (almost) oxide-free surface as this would result in the lowest Nbt. Although such a surface is characterized by a high mid-gap Dit, this can be improved by performing the correct PDA. We conclude that the most promising oxide-free surface is obtained after an H2S treatment.

Recent developments on CMOS-driven III-V and Ge MOS (Metal-oxide-semiconductor) technologies provide new opportunities in advancing the performance envelope of MOS device as well as the relevant electrical characterization techniques. Understanding the capacitance-voltage (CV) and conductance voltage (GV) responses of the III-V/Ge MOS devices can lead to better assessments of the oxide-semiconductor material systems and more accurate performance predictions.

We will present the defect density at In0.53Ga0.47As and InP interfaces with ALD Al2O3 derived by use of the conductance method and from simulation of low frequency CV-curves. Consequences of the interface state distribution for MOS transistor device operation will be highlighted through 1-dimensional electrostatic simulations. The simulation results will be compared as much as possible to different state-of-the-art transistor results presented in literature.

For the next generation CMOS technology nodes, new channel materials, such as Ge and III/V semiconductors, are explored because of their higher intrinsic carrier mobility as compared to Si. One of the key issues for integrating Ge and III-V in CMOS devices is achieving a good electrical passivation of the interface. Dangling bonds at the channel/gate stack interface are trapping charges and reducing the amount of mobile carriers. Passivating interfacial layers between the Ge channel and the high-k dielectric are therefore developed, and control at the atomic level is required during both surface passivation treatment and subsequent deposition of the dielectric. Experimental techniques such as X-ray Photoelectron spectroscopy [1] are used to characterize the interfacial layers and possible relations to electrical defects. Furthermore, theoretical calculations can be used to provide insight in the atomic structure of the interfaces [2] and the specific interactions during gate stack formation.

High mobility channels are currently being explored to replace the Si channel in future technology nodes. However, until now the promising bulk properties are very difficult to translate into reality due to a bad passivation of the interface between the gate stack and the substrate. In this paper we want to emphasize that gate stack passivation is the result of a complex interplay between the surface treatment and the ALD deposition. During ALD deposition on GaAs, the removal of surface oxides is observed. However, this effect does not lead to a good passivation. For Ge, the S-passivation of the interface is studied in combination with different high-κ. It is clear that the Ge/S/Al2O3 interface is superior to the Ge/S/ZrO2 interface.

A new passivation approach integrating the III-V/Ge MOSFET gate stack processes for a complete CMOS solution is proposed. We explore the In0.53Ga0.47As and Ge MOS electrical properties and present the common gate stack (CGS) concept based on the complementary nature of the asymmetric oxide-In0.53Ga0.47As and the oxide-Ge interface state distributions. In addition, this approach requires neither the interfacial passivation layer (IPL) such as Si, nor the native oxide such as the GeO2, between the gate dielectric and the channels. The oxide-semiconductor interface properties of the common gate stack III-V/Ge MOS system have been carefully investigated and MOS transistors have been fabricated to validate the proposed common gate stack concept. It has been demonstrated that the above common gate stack MOS system can achieve high-performance n-channel operation on In0.53Ga0.47As substrates and p-channel operation on Ge substrates.

The use of Ge and III/V materials for future CMOS applications is investigated. Passivation of the Ge surface can be obtained by either GeO2 or a thin Si layer. Short channel Ge pMOS devices with low EOT are fabricated. The passivation of III/V materials is a very challenging topic. Some critical issues and passivation schemes are investigated and the performance of inversion channel MOSFET's on In0.53Ga0.47As with ALD Al2O3 is discussed.

Numerous metal oxides have been studied worldwide as possible high-k gate dielectric candidates for MOS devices on alternative semiconductor materials (Ge, III/V compounds). We will discuss thermal and plasma-enhanced atomic layer deposition (ALD) of a few materials, HfO"2 and Al"2O"3. We will spend some attention to characteristic features of the growth process and specific growth precursors as this is known to influence strongly the quality of the layer bulk as well as the interface. Detailed electrical characterization of MOS capacitors build on such dielectric layers, before and after forming gas anneals, shows that these interface modifications can lead to a marked decrease of the smaller interface state peaks close to the edges of the bandgap, whereas the larger mid-gap peaks are barely touched. The results of atomistic modeling of the oxidation of a GaAs surface help to understand the origin of these mid-gap electronic states, which are responsible for the apparent pinning of the Fermi level.

A good dielectric layer on the GaAs substrate is one of the critical issues to be solved for introducing GaAs as a candidate to replace Si in semiconductor processing. In literature, promising results have been shown for Al2O 3on GaAs substrates. Therefore, atomic layer deposition (ALD) of Al2O3has been studied on GaAs substrates. We have been investigating the influence of the ALD process (thermal vs plasma-enhanced ALD) as well as the influence of the starting surface (no clean vs partial removal of the native oxide). Ellipsometry and total X-ray reflection fluorescence were applied to study the growth of the ALD layers. Angle-resolved X-ray photoelectron spectroscopy was used to determine the composition of the interlayer. Both processes were shown to be roughly independent of the starting surface with a minor dependence for the thermal ALD. Thermally deposited ALD layers exhibited better electrical characteristics based on capacitance measurements. This could be linked to the thinner interlayer observed for thermally deposited Al2 O3. However, the Fermi level was not unpinned in all cases, suggesting that more work needs to be done for passivating the interface between GaAs and the high- k layer. © 2009 The Electrochemical Society.

Si has dominated semiconductor industry for decades. However, new materials are appearing in this field such as Ge, GaAs and InxGa1-xAs. In semiconductor processing several wet chemical steps are used including cleaning, etching and stripping. Knowledge of etch rates in these solutions is of great importance. In this paper, an etch rate study was performed for Ge, GaAs and InxGa1-xAs in several wet chemical cleaning solutions. The chemistries studied include acids (HCl, HF, HNO3, H2SO4, H3PO4, H2O2) and bases (NH4OH) and peroxide based mixtures. It has been found that etch rates are much higher than for Si due to the formation of soluble oxides. Therefore, "fine-tuning" of the chemistries is a prerequiste when introducing these materials in microelectronic industry.

Ge and III-V semiconductors are potential high performance channel materials for future CMOS devices. In this work, we have studied Atomic Layer Deposition (ALD) of high-k dielectric layers on Ge and GaAs substrates. We focus at the effect of the oxidant (H2O, O3, O2, O2 plasma) during gate stack formation. GeO2, obtained by Ge oxidation in O2 or O3, is a promising passivation layer. The germanium oxide thickness can be scaled down below 1 nm, but such thin layers contain Ge in oxidation states lower than 4+. Still, electrical results indicate that small amounts of Ge in oxidation states lower than 4+ are not detrimental for device performance. Partial intermixing was observed for high-k dielectric and GeO2 or GaAsOx, suggesting possible correlations in the ALD growth mechanisms on Ge and GaAs substrates.

In this paper, we present the results of a detailed study done on the correlation between frequency dispersion observed in AC admittance measurements and threshold voltage shifts observed in BTI reliability measurements on III-V MOS devices. We developed a detailed AC admittance model for MOS devices with border traps to study the effect of trap parameters on the AC admittance. We show, with the help of simulations and experiments, a clear correlation between border trap characteristics in AC admittance and BTI behavior. In addition, we propose a simplified and quick method to qualitatively characterize border traps using G/ω as a measure for their density.

Passivation of the channel in the gate stack is the most important problem for introducing another material than silicon into the channel of CMOS devices. In order to compare the mobility values of different passivation techniques, we propose to use a parameter, which is a proportional to the drive current of the transistor. We call this parameter the channel mobility value and it is calculated from the transistor equation. This channel mobility value can be used to benchmark more consistently the different passivation techniques on germanium or other semiconductor materials. A second issue for CMOS scaling on Ge is the poor performance of nMOS devices and there seems no solution in sight for this problem. Therefore we promote the investigation of technologies to allow the introduction of III-V materials on Ge to make nMOS devices in III-V devices complementary with Ge pMOS. A third key issue is the development of a manufacturable and low defect density germanium-on-insulator (GeOI) technology on 200mm and larger substrate sizes.

Ge and III/V semiconductor substrates are recently being investigated as a candidate material for the replacement of Si substrates in advanced micro-electronic devices. The reintroduction of this material requires engineering of the standard IC processing steps. In this paper, we present how the trace analytical techniques of total reflection X-ray fluorescence spectrometry (TXRF) and atomic absorption spectrometry (AAS) contribute to the realization of suitable processes to realize a high quality gate stack on Ge and GaAs substrates. A conventional application for these techniques lays in contamination control on incoming wafers. Besides this, we demonstrate some more advanced applications such as the determination of dopant concentrations (As in Ge), the study of passivation processes (S on Ge) and the characterization of nanometer thin layers (Si on Ge, HfO2 on Si).

The deep-level parameters of a number of technological relevant transition metals—Hf, Ti, Cr, Fe, Co and Ni—in n-type germanium have been studied by deep-level transient spectroscopy (DLTS). The metals have been introduced by ion implantation followed by annealing at 500 °C for 5 min. In most cases the annealing treatment is sufficient to remove the implantation point defects from the substrate, leaving only metal-related electron traps in the spectra. From the fact that for each metal, one (or more) peaks at a different position and with a different activation energy is observed, it is concluded that levels specific for the individual metals have been detected. This is further validated by the observation that the corresponding trap concentration increases with the implantation dose. In some cases, e.g. Hf, we believe that it is the first observation of the impurity-related deep electron traps in germanium.

This work demonstrates the feasibility of an inversion-mode relaxed Ge n-FinFET scaled down to 15-nm fin width and sub-40-nm gate length. CMOS-compatible processing steps such as STI formation, replacement metal gate (RMG), in-situ Phosphorus-doped raised-Source/Drain and a Ni-based contact scheme have been successfully implemented. This first industry-compatible Ge n-FinFET has a G M,SAT,EXT / SS SAT of 250 µS.µm−1 / 130 mV.dec−1 (at the targeted V DS =0.5V) which is on par with accumulation-mode junction-less Ge n-FETs.

We study RTN and PBTI in nanoscale InGaAs FinFETs fabricated on 300mm Si wafers. The average instability is found to be comparable to planar structures, but significantly larger when compared to Si devices. Although the novel devices follow the same time-dependent variability statistics and the corresponding area-scaling as their Si counterparts, a larger stochastic impact of single defects on the device characteristic is found to induce larger aging-related variance. We ascribe this to a more percolative channel conduction induced by still excessive interface and channel defectivity.

Our present understanding of BTI in Si and (Si)Ge based sub 1-nanometer EOT MOSFET devices is reviewed and extended to benchmark other Beyond-Si based devices. We discuss the evolution of NBTI for Si-based pMOS devices as a possible showstopper for further scaling below 1nm EOT. Then we present the BTI reliability framework which was developed for SiGe based MOSFET devices, showing strongly improved BTI reliability, explained by carrier-defect decoupling. Also the important issue of increasing stochastic behavior and time dependent variability is discussed. Based on the presented framework developed for SiGe stacks we benchmark alternative Beyond-Si gate stacks using a metric for carrier-defect decoupling, allowing to screen stacks for acceptable reliability.

Films of regioregular chiral poly[(S)-3-(3,7-dimethyloctyl)thiophene] (see Figure) prepared via spin-coating and characterized by polarized UV-vis spectroscopy show that order along the film normal is present (which is proportional to the spinning rate). Phase-sensitive second-harmonic generation experiments demonstrate this order to be polar. ispartof: Advanced Materials vol:17 issue:6 pages:708- status: published