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SkyLake-SP (Scalable Performance), code name SKX, is the next generation Xeon® server processor fabricated on the Intel® 14nm tri-gate CMOS technology with 11-metal layers [1,2]. The SKX processor family has three core-count configurations. Each SKX core is accompanied by 1MB of dedicated L2 (2nd level cache) and 1.375MB of non-exclusive L3 (3rd level cache). At its maximum configuration of 28 cores, the SKX processor supports 6 DDR4 channels (2666MT/s), 3×20-lanes UPI processor-to-processor links (10.4GT/s) and x48+4 PCIE links (8GT/s). SKX supports per-core power-performance optimization enabled by on-die integrated voltage regulators (FIVR) [3, 4]. A new 2-dimensional synchronous on-die MESH fabric interconnects all the on-die components. Fig. 2.1.1 shows the overall architecture of the SKX processor.

This paper describes a 4.3B transistors, 15-cores, 30-threads enterprise Xeon® processor with a 37.5 MB shared L3 cache implemented in a 22 nm 9M Hi-K metal gate tri-gate process. A modular floorplan methodology enables easy chops to 10 and 6 cores. Multiple clock and voltage domains are used to reduce power consumption. The clock distribution uses a single PLL per column to save power and minimize deskew crossing points. Integrated PCIe Gen3 and Quick Path Interconnect® (QPI) ports operate at 8GT/s. The 4-channel memory interface supports both 1866 MT/s DDR3 and a new memory buffer interface running at 2667 MT/s on the same pins. The core, cache and I/O recovery techniques improve manufacturing yields and enable multiple product flavors from the same silicon die.

An active filter-based on-chip DC-DC voltage converter for application to distributed on-chip power supplies in multivoltage systems is described in this paper. No inductor or output capacitor is required in the proposed converter. The area of the voltage converter is therefore significantly less than that of a conventional low-dropout (LDO) regulator. Hence, the proposed circuit is appropriate for point-of-load voltage regulation for noise sensitive portions of an integrated circuit. The performance of the circuit has been verified with Cadence Spectre simulations and fabricated with a commercial 110 nm complimentary metal oxide semiconductor (CMOS) technology. The area of the voltage regulator is 0.015 mm2 and delivers up to 80 mA of output current. The transient response with no output capacitor ranges from 72 to 192 ns. The parameter sensitivity of the active filter is also described. The advantages and disadvantages of the active filter-based, conventional switching, linear, and switched capacitor voltage converters are compared. The proposed circuit is an alternative to classical LDO voltage regulators, providing a means for distributing multiple local power supplies across an integrated circuit while maintaining high current efficiency and fast response time within a small area.

We propose a low cost scheme for the dynamic compensation in the field of undesired skew and duty cycle variations of local clocks of high performance microprocessors and high end ASICs. Compared to alternate approaches, our solution features lower power consumption, smaller compensation error, and a lower or comparable area overhead.

This paper describes a 2.3 Billion transistors, 8-core, 16-thread, 64-bit Xeon® EX processor with a 24 MB shared L3 cache implemented in a 45 nm nine-metal process. Multiple clock and voltage domains are used to reduce power consumption. Long channel devices and cache sleep mode are used to minimize leakage. Core and cache recovery improve manufacturing yields and enable multiple product flavors from the same silicon die. The disabled blocks are both clock and power gated to minimize their power consumption. Idle power is reduced by shutting off the unterminated I/O links and shedding phases in the voltage regulator to improve the power conversion efficiency.

This paper describes a dual-core 64-b Xeon MP processor implemented in a 65-nm eight-metal process. The 435-mm2 die has 1.328-B transistors. Each core has two threads and a unified 1-MB L2 cache. The 16-MB shared, 16-way set-associative L3 cache implements both sleep and shut-off leakage reduction modes. Long channel transistors are used to reduce subthreshold leakage in cores and uncore (all portions of the die that are outside the cores) control logic. Multiple voltage and clock domains are employed to reduce power

In this paper we present a low cost, on-chip clock jitter digital measurement scheme for high performance microprocessors. It enables in-situ jitter measurement during the test or debug phase. It provides very high measurement resolution and accuracy, despite the possible presence of power supply noise (representing a major source of clock jitter), at low area and power costs. The achieved resolution is scalable with technology node and can in principle be increased as much as desired, at low additional costs in terms of area overhead and power consumption. We show that, for the case of high performance microprocessors employing Ring Oscillators (ROs) to measure process parameter variations, our jitter measurement scheme can be implemented by re-using part of such ROs, thus allowing to measure clock jitter with very limited cost increase compared to process parameter variation measurement only, and with no impact on parameter variation measurement resolution.

The 18-way set-associative, single-ported 9 MB cache for the Itanium 2 processor uses 210 identical 48-kB sub-arrays with a 2.21-/spl mu/m/sup 2/ cell in a 130-nm 6-metal technology. The processor runs at 1.7 GHz at 1.35 V and dissipates 130 W. The 432-mm/sup 2/ die contains 592 M transistors, the largest transistor count reported for a microprocessor. This paper reviews circuit design and implementation details for the L3 cache data and tag arrays. The staged mode ECC scheme avoids a latency increase in the L3 tag. A high V/sub t/ implant improves the read stability and reduces the sub-threshold leakage.

The clock generation and distribution system for the 130-nm Itanium 2 processor operates at 1.5 GHz with a skew of 24 ps. The Itanium 2 processor features 6 MB of on-die L3 cache and has a die size of 374 mm/sup 2/. Fuse-based clock de-skew enables post-silicon clock optimization to gain higher frequency. This paper describes the clock generation, global clock distribution, local clocking, and the clock skew optimization feature.

This 130-nm Itanium 2 processor implements the explicitly parallel instruction computing (EPIC) architecture and features an on-die 6-MB 24-way set-associative level-3 cache. The 374-mm/sup 2/ die contains 410 M transistors and is implemented in a dual-V/sub t/ process with six Cu interconnect layers and FSG dielectric. The processor runs at 1.5 GHz at 1.3 V and dissipates a maximum of 130 W. This paper reviews circuit design and package details, power delivery, the reliability, availability, and serviceability (RAS) features, design for test (DFT), and design for manufacturability (DFM) features, as well as an overview of the design and verification methodology. The fuse-based clock deskew circuit achieves 24-ps skew across the entire die, while the scan-based skew control further reduces it to 7 ps. The 128-bit front-side bus has a bandwidth of 6.4 GB/s and supports up to four processors on a single bus.

The clock design for the first implementation of the IA-64 microprocessor is presented. A clock distribution with an active distributed deskewing technique is used to achieve a low skew of 28 ps. This technique is capable of compensating skews caused by within-die process variations that are becoming a significant factor of the clock design. The global, regional and local clock distributions are described. A multilevel skew budget and local clock timing methodology are used to enable a high-performance design by providing support for intentional clock skew injection and time borrowing. By providing a test access port interface to the deskew architecture and the incorporation of the on-die-clock-shrink, this design is equipped with two very powerful post-silicon timing debug tools that are critical to high-performance microprocessor design and enabled quick time-to-market.

We propose a new design for testability approach for testing clock faults of next generation high performance microprocessors. In fact, it has been shown that conventional manufacturing test is unable to guarantee their detection, although they could compromise the effectiveness of delay fault testing, as well as the microprocessor correct operation in the field. These conditions will of course worsen with technology scaling, due to the expected increase in fault likelihood, included clock faults. To deal with these problems we propose a design for testability approach that, by means of simple modifications to conventional clock buffers, allows clock fault detection through any conventional manufacturing test approach. This is achieved at the cost of very low increase in area and power consumption of clock buffers, and with no additional test cost or impact on the microprocessor performance and in-field operation. We then introduce a possible further modification to clock buffers that, at additional limited costs in terms of area and power consumption, allows their calibration after fabrication in order to compensate for parameter variations possibly occurring during manufacturing, thus minimizing the likelihood of either false test fails, or test misses. As an example, we show the application of our approach to the clock distribution network of the Pentium® 4 microprocessor (Other names and brands may be claimed as property of others). However, it can be applied to the clock distribution of any high performance ASIC, or microprocessor.

An integrated circuit implementation of a fully parallel analog artificial neural network is presented. We include details of the architecture, some of the important design considerations, a description of the circuits and finally actual performance data. The electrically trainable artificial neural network (ETANN) chip incorporates 64 analog neurons and 10,240 analog synapses and utilizes a 1-µm CMOS NVM process. The network calculates the dot product between a 64-element analog input vector and a 64 × 64 nonvolatile (EEPROM based) analog synaptic weight array. These calculations occur at a rate in excess of 1.3 billion interconnections per second. All elements of the computation are stored and calculated in the analog domain and strictly in parallel. A 2:1 input and neuron multiplex mode permits rates in excess of 2 billion interconnections per second and a single-chip effective network size of 64 inputs by 128 outputs. The ETANN incorporates differential signal techniques throughout for improved noise rejection. Current summing is employed for the sum of products calculations. The chip integrates approximately 400 op amps, including variable gain stages of from 20 to 54 dB. Inevitable component to component variations due to the use of minimum dimension elements are found not to be significant for operation in an adaptive environment.

We present a novel low cost scheme for the on-die measurement of either clock jitter, or process parameter variations. By re-using and properly modifying the Ring Oscillators (ROs) that are currently widely employed for process parameter variation measurement in high performance microprocessors, our proposed scheme can be easily set in either the process parameter variation measurement mode, or the clock jitter measurement mode, by acting on an external control signal. This way, during the test or debug phase, clock jitter can also be measured at negligible area and power costs with respect to process parameter variation measurement only. Our scheme is scalable in the provided clock jitter measurement resolution, while allowing the same process parameter variation measurement resolution as the currently employed RO based schemes. Moreover, due to its allowing both process parameter variation and clock jitter measurements, our scheme features accurate clock jitter measurement despite the possible presence of significant process parameter variations.

Modern clock distribution design continues to face challenges in spite of significant advances in the last decade. We can distinguish three primary challenges. The first is the need to support higher clock frequencies based on the strong correlation between frequency and chip performance. Figure 2.1 shows processor clock frequency trend suggesting a continuous exponential increase in clock frequency with variable rates. Second, process technology scaling allows higher level of integration and larger die size leading to higher clock loading and larger distances the clock network needs to traverse. The final challenge is that technology scaling leads to an increase in on-die variations that may degrade clock performance if not properly addressed.

In this paper we present an on-chip clock jitter digital measurement scheme for high performance microprocessors. The scheme enables in-situ jitter measurement of the clock distribution network during the test or the debug phase. It provides very high measurement resolution, despite the possible presence of power supply noise (constituting a major cause of clock jitter) affecting itself. The resolution is higher than a min sized inverter input-output delay, and can on principle be further increased, at some additional costs in terms of area overhead and power consumption. In this paper, a resolution of the 1.8% of the clock period is achieved with limited area and power costs.

This paper describes a 95 W dual-core 64-bit Xeonreg MP processor implemented in a 65 nm 8 metal layer process. Each processor core has a unified 1MB L2 cache and supports the Intelreg Extended Memory 64 Technology and the Hyper-Threading Technology. The shared L3 cache has extensive RAS features including the Intelreg Cache Safe Technology and Error Correction Codes (ECC). The processor is designed and optimized to operate at a 95W thermal design power envelope at the target product frequency. The front-side bus operates at 667 MT/s or 800 MT/s in a 3 load topology that is compatible with existing platforms.

The clock generation and hybrid clock distribution for a dual-core Xeonreg processor with 16MB L3 cache are designed for

The clock generation and distribution system for the third generation Itanium/spl reg/ processor operates at 1.5 GHz with a skew of 24 ps. Clock optimization fuses enable post-silicon speed path balancing for higher performance.

The issues associated with implementing the error backpropagation algorithm on a 64-neuron nonvolatile analog VLSI neural network chip (ETANN) are described. Imperfections in the analog ETANN chip were identified and found to impose constraints on the learning process. A chip-in-the-loop learning technique and an adaptive, reinforced, bake-train-bake scheme are reported. These techniques have shown potential in surmounting the difficulties connected with learning on an analog neural network chip. Experimental results are reported. >

The Itanium processor is Intel's first 64-bit microprocessor [1] and features a highly parallel architecture fabricated using the 0.18um process. This higher integration of features requires a significant silicon real estate and high clock loading. These factors, coupled with more prominent on-die variations because of reduced device geometries, call for special techniques to manage the clock design. The Itanium processor employs very well balanced clock routing along with distributed deskew buffers (DSK) to achieve low skew. The ItaniumTM processor also includes additional features to aid performance tuning and timing debug. This paper highlights the salient features of the Itanium processor clock design and presents clock characterization data from initial silicon.

Width dependence of hot-electron currents in MOSFET's fabricated with LOCOS, non-LOCOS, and a modified LOCOS processes are studied. The experimental results show that the substrate and gate currents are apparently enhanced in narrow width devices. The enhancement, however, is due to different voltage drops across the source-drain series resistance. The voltage drops are usually larger in wider devices. After correcting for the resistance effect, the substrate and gate currents scale with the device width. With this typical LOCOS process, the bird's beak and in-diffusion of field implant dopants do not cause excess hot-electron activities along the channel/field edges as has been suspected. Some other LOCOS process could, of course, produce a different result. Studies using wide test devices must consider the series resistance effect. With this precaution taken, models derived from wide-channel data will be applicable to narrow-channel devices, at least for some processes.

The phenomenon of and the physical mechanisms for the generation of minority carriers in the substrate of NMOS and CMOS are studied. Secondary impact ionization is not responsible. The responsible mechanisms are hot-electron-induced photocarrier generation and, under extreme conditions, forward biasing of the source-substrate junction. The photon generation is believed to be due to the bremsstrahlung of the channel hot electrons. A theoretical model based on the lucky electron concept and the bremsstrahlung mechanism is proposed. The calculated characteristics of photon generation agree well with experimental results. About 2 × 10-5photogenerated minority carriers are generated for every (primary) impact-ionization event in NMOSFET. Photocarrier-induced leakage current can be fitted with either an inverse square dependence on distance or an exponential dependence with an effective decay length of about 780 µm.

The lucky-electron concept is successfully applied to the modeling of channel hot-electron injection in n-channel MOSFET's, although the result can be interpreted in terms of electron temperature as well. This results in a relatively simple expression that can quantitatively predict channel hot-electron injection current in MOSFET's. The model is compared with measurements on a series of n-channel MOSFET's and good agreement is achieved. In the process, new values for many physical parameters such as hot-electron scattering mean-free-path, impact-ionization energy are determined. Of perhaps even greater practical significance is the quantitative correlation between the gate current and the substrate current that this model suggests.