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A 45 nm 8-Core Enterprise Xeon¯ Processor
- Source :
- ISSCC
- Publication Year :
- 2010
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 2010.
-
Abstract
- This paper describes a 2.3 Billion transistors, 8-core, 16-thread, 64-bit Xeon® EX processor with a 24 MB shared L3 cache implemented in a 45 nm nine-metal process. Multiple clock and voltage domains are used to reduce power consumption. Long channel devices and cache sleep mode are used to minimize leakage. Core and cache recovery improve manufacturing yields and enable multiple product flavors from the same silicon die. The disabled blocks are both clock and power gated to minimize their power consumption. Idle power is reduced by shutting off the unterminated I/O links and shedding phases in the voltage regulator to improve the power conversion efficiency.
Details
- ISSN :
- 1558173X and 00189200
- Volume :
- 45
- Database :
- OpenAIRE
- Journal :
- IEEE Journal of Solid-State Circuits
- Accession number :
- edsair.doi...........131466a8ef50023a6828f6c914c22b7c