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In this study, two new structures are proposed for reverse-conducting insulated gate bipolar transistors (RC-IGBT) that effectively prevent snapback by relocating the N-collectors and utilizing silicon–germanium in the collector region of each device. The forward mode of the proposed structures shows IC− VC characteristics without snapback, since the position of the N-collector is changed to prevent electron extraction. In the reverse mode, the silicon–germanium induces currents through tunneling and impacts the ionization mechanisms. Importantly, the proposed structures generate a stable current value even if there are errors in the length of the N-collector during ion implantation, which enhances the reliability of the device. In addition, the proposed structures exhibit similar values for the breakdown voltage at around 700 V and the turn-on and turn-off losses when compared to the conventional RC-IGBT. Thus, this paper improves the reliability of RC-IGBTs by mitigating the snapback effect while maintaining their unique electrical properties. [ABSTRACT FROM AUTHOR]

Gate-all-around (GAA) structures are important for future logic devices and 3D-DRAM. Inner-spacer cavity etching and channel release both require selective etching of Si0.7Ge0.3. Increasing the number of channel-stacking layers is an effective way to improve device current-driving capability and storage density. Previous work investigated ICP selective etching of a three-cycle Si0.7Ge0.3/Si multilayer structure and the related etching effects. This study focuses on the dry etching of a 15-cycle Si0.7Ge0.3/Si multilayer structure and the associated etching effects, using simulation and experimentation. The simulation predicts the random effect of lateral etching depth and the asymmetric effect of silicon nanosheet damage on the edge, both of which are verified by experiments. Furthermore, the study experimentally investigates the influence and mechanism of pressure, power, and other parameters on the etching results. Research on these etching effects and mechanisms will provide important points of reference for the dry selective etching of Si0.7Ge0.3 in GAA structures. [ABSTRACT FROM AUTHOR]

Under the background of the increasing demand for germanium in high-tech, this paper finds out the mechanism of silicon germanium polymerization precipitation by simulating the leaching process of zinc oxide dust containing germanium. By comparing and analyzing the simulation experiments under ultrasonic and conventional conditions, the mechanism of efficient dispersion and depolymerization of germanium silicon precipitation induced by ultrasonic was found out. The results show that in the leaching process of germanium-containing zinc oxide dust, due to the increase of local pH, some silicon ions in the solution will hydrolyze and polymerize to form silicic acid colloid to adsorb germanium in the solution, causing the loss of germanium 14.81%, resulting in low recovery rate of germanium industry. Ultrasonic wave was introduced in the leaching process, and the shock wave and micro-jet released by ultrasonic cavitation continuously impacted the surface of polysilicate colloid. The germanium adsorbed on the surface of the silicic acid colloid is desorbed, and the large particles of silica gel are depolymerized into small particles of silicic acid, which reduces the adsorption of silica gel on germanium. The loss of germanium under ultrasonic conditions can be reduced by 59.35%. This study can effectively realize the efficient recovery of germanium in zinc oxide dust, and provide process and theoretical basis for the sustainable development of germanium industry.

This paper reports on the studies of oxidation kinetics of silicon strained by silicon germanium layers. Experimental results of natural, chemical and thermal oxide formation are presented. The oxidation rates of silicon strained by SiGe layers have been compared with the rates of pure Si oxidation. The oxidation kinetics was studied using the parallel model proposed by Beck and Majkusiak. This model was fitted with good result to the obtained experimental data and the parameter that is most probably responsible for the strain effect was identified, as well as its dependence on Ge content in the SiGe layer.

An overview of critical integration issues for future generation MOSFETs towards 10 nm gate length is presented. Novel materials and innovative structures are discussed. The need for high-k gate dielectrics and a metal gate electrode is discussed. Different techniques for strain-enhanced mobility are discussed. As an example, ultra thin body SOI devices with high mobility SiGe channels are demonstrated.

A spark plasma sintering technology has already become rather common for the fabrication of GexSi1-x nanostructured thermoelectric solid solutions. Such trend is related with a number of opportunities and technological tools that enable precise properties manipulation. The present paper is devoted to discussing the modulation of GexSi1-x spark plasma sintering technique that consists in the use of silicon phosphide as a source of n-type doping within the process of sintering. The composition of the sintered powder is investigated. The synthesis of a solid solution was carried out in the process of sintering. The SiP is a chemically stable non-toxic compound that can replace toxic phosphorus in thermoelectric technology thus reducing the safety requirements of the corresponding technology process. The paper investigates the effect of SiP concentration on thermoelectric characteristics. The impurity distribution is analyzed, and the association of phosphorus atoms into clusters at a very high doping level is shown. The distribution of impurity elements was controlled by EMF analysis in a scanning electron microscope. It was shown that sintering of Ge-Si-SiP powder mixture allowed obtaining the phosphorus doped GexSi1-x material with high electron concentration that demonstrate high level of thermoelectric properties. The obtained thermoelectric characteristics are compared with the world's best nanostructured materials [ABSTRACT FROM AUTHOR]

In this paper we present the results of the numerical simulation using wx-AMPS1D software of a solar cell based on hydrogenated amorphous silicon (a-Si: H / c-SiGe), the top layer has the largest band gap, while the bottom layer has the smallest bandgap. This design allows less energetic photons to pass through the upper layer(s) and be absorbed by the layer below, which increases the overall efficiency of the solar cell to obtain an efficiency high conversion rate. As the results, remarkable improvements on Voc, Jsc and FF have been achieved with the incorporation of n-c-SiGe layer, we achieved an efficiency of 11.93%. [ABSTRACT FROM AUTHOR]

This work describes the development of an amplifier frequency doubler chain (AFDC) operating at around 300 GHz based on SiGe BiCMOS technology. The driver amplifier is based on the differential cascode configuration, which employs coupled-line transformers for compact design. The frequency doubler is based on the class-B topology, which is known for exhibiting a large output power with low DC power consumption. The integrated AFDC, which consists of the frequency doubler and the preceding driver amplifier, exhibited a measured peak output power and DC-to-RF efficiency of −0.9 dBm and 0.97%, respectively, along with a conversion gain of −0.1 dB. It operates from 284 to 328 GHz with a 0-dBm input signal, consuming a total DC power of only 84 mW. The chip size is 720 × 310 μm2, excluding RF and DC pads.

This brief presents a broadband SiGe power amplifier that achieves 30.1 dBm peak $\text{P}_{SAT}$ , 38.6% peak power-added efficiency (PAE), 90.9% large-signal fractional bandwidth (FBW) and a 3 dB bandwidth from 5.4 to 13.8 GHz. A balanced topology with two-stage, four-way combing is utilized to achieve watt-level output power and high-power efficiency in a wide range of operating frequency. Power stage is optimized and simulated from the perspective of high output power. At the output stage, a 90° coupler and two transformers are co-optimized for broadband output power combining as well as power matching. This balanced PA is implemented in a 0.13- $\boldsymbol {\mu }\text{m}$ SiGe BiCMOS process with a chip area (with pads) of 2.31 mm2. [ABSTRACT FROM AUTHOR]

This letter presents a four-way power combined $D$ -band power amplifier (PA) in 0.13- $\mu \text{m}$ SiGe technology. The conventional cascode topology is modified by adding an additional interstage network between the common-emitter (CE) and common-base (CB) devices. Further techniques, such as power combining and adaptive bias circuits, are implemented to boost the power generation and the efficiency of the amplifier. The realized PA exhibits a saturated output power of 19.6 dBm with a maximum power-added-efficiency (PAE) of 9.5% at 130 GHz, which is a leading-edge performance among the reported silicon (Si) $D$ -band PAs in similar technologies. The small-signal gain peaks at 16 dB and the PA has a 3-dB bandwidth of 18 GHz. [ABSTRACT FROM AUTHOR]

A power combined wideband power amplifier (PA) covering the $J$ -band (220–320 GHz) is presented in 130-nm BiCMOS technology. The input power is split by two cascaded 1-to-2 power splitters with amplification stages in-between. The four split signals drive four output stages, which have their outputs combined within a 4-way zero-degree combiner. The splitting and combining networks also incorporate impedance matching. After de-embedding the I/O pads and baluns of 2 dB loss at each side, the PA achieves a gain of 20 dB at the middle of the band and a minimum gain of 17 dB at 320 GHz with I/O return losses below −5 dB. The PA records a saturated output power ranging from 9.5 to 14.5 dBm across the $J$ -band. It consumes 710 mW from a 3 V supply which corresponds to a drain efficiency ($\eta _{d}$) of 3.15% at 270 GHz. The presented PA achieves twice better bandwidth with 1.5 times better $\eta _{d}$ than the state-of-the-art silicon-based amplifiers above 200 GHz. To the authors’ knowledge, this is the first PA covering the whole $J$ -band in silicon technologies. [ABSTRACT FROM AUTHOR]

Intel's efforts to build a practical quantum computer are focused on developing a scalable spin-qubit platform leveraging industrial high-volume semiconductor manufacturing expertise and 300 mm fabrication infrastructure. Here, we provide an overview of the design, fabrication, and demonstration of a new customized quantum test chip, which contains 12-quantum-dot spin-qubit linear arrays, code named Tunnel Falls. These devices are fabricated using immersion and extreme ultraviolet lithography (EUV), along with other standard high-volume manufacturing (HVM) processes as well as production-level process control. We present key device features and fabrication details as well as qubit characterization results confirming device functionality. These results corroborate our fabrication methods and are a crucial step toward scaling of extensible 2D qubit array schemes.

A compact analytical model is proposed along with a parameter extraction methodology to accurately capture the steady-state (DC) sequential tunneling current observed in the subthreshold region of the transfer $I_{DS}-V_{GS}$ characteristics of MOSFETs at cryogenic temperatures. The model is shown to match measurements of $p$ -MOSFETs and $n$ -MOSFETs manufactured in a commercial 22nm FDSOI foundry technology, with reasonable accuracy across bias conditions and temperature (2 K - 50 K). Furthermore, the extracted model parameters are used to analyze the impact of the gate and drain voltages and of layout geometry on the device characteristics.

Polycrystalline SiGe thin films have been formed after thermal annealing of formerly vacuum evaporated a-Ge layers. The a-Ge thin films were deposited onto nanostructured Si substrates via low-cost thermal evaporation method. Then, the films were annealed in a furnace at temperatures ranging from 400 °C to 1000 °C resulting in crystal growth of the SiGe layers. In general, the annealing temperature for polycrystalline SiGe is between 600 °C - 800 °C. The crystalline structure of the SiGe layer is improved as a function of increased temperature. This is shown by the low FWHM of about 5.27 as compared to the commercially available Ge substrates where the FWHM value is about 5.06. This method also produces more relax Ge layer where the strain value is 0.261. [ABSTRACT FROM AUTHOR]

We present a wideband watt-level power amplifier (PA) for the $Ka$ -band designed and implemented in the 0.25- $\mu \text{m}$ SiGe:C BiCMOS technology. The core of the design is a chip with multiple custom PA unit cells (PA-cells), which are interfaced with a power combiner placed on a laminate. The power combiner is based on a principle of the recently proposed multichannel transition with spatial power combining functionality, where an array of strongly coupled microstrip lines (MLs) interface a single substrate integrated waveguide (SIW). The realized watt-level PA combining four differential cascode PA-cells achieves a saturated output power ($P_{{\text {sat}}}$) of 30.8 dBm with 26.7% power-added efficiency (PAE). The 64-QAM modulation tests confirm the competitive PA performance on multi-Gb/s communication signals. The obtained combination of the high PAE and high $P _{{\text {sat}}}$ over a wide frequency band (30%) is an advantageous property of the proposed solution with respect to the previously published designs. This high performance is the result of using the proposed architecture with low-loss (0.6 dB) and wideband (54%) parallel spatial power combiner. Moreover, the presented joint EM–circuit–thermal optimization allows achieving optimal system-level performance by taking into account various critical multiphysics effects occurring in the combined PA. This article describes the design and performance of the whole integrated structure and its individual components. [ABSTRACT FROM AUTHOR]

This study demonstrated the ultralow equivalent oxide thickness (EOT) value of 0.72 nm and the high-quality high- $\kappa $ /Si0.8Ge0.2 interface on p-type Si0.8Ge0.2 with direct deposition of HfO2. The ultrathin interfacial layer (IL) thickness of ~0.4 nm was observed in the high-resolution transmission electron microscope (HRTEM) images. The high-quality interface might result from the high- $\kappa $ /Si0.8Ge0.2 interface mainly consisting of the higher Si oxidation states, verified by X-ray photoelectron spectroscopy (XPS). Thus, this study refutes the necessity of IL formation and paves the way for low-EOT Si0.8Ge0.2 devices. [ABSTRACT FROM AUTHOR]

This work presents a D-band phase shifter which utilizes a one-bit phase inverter (PI), followed by two cascaded reflective-type phase shifters (RTPSs). The PI uses two identical cascode amplifiers and a triaxial balun for compact form factor and to provide identical loading in both states. The RTPSs use SiGe PIN diodes for their resonant loads due to their naturally high-Q and tuning range. The phase shifter is implemented in a 90-nm SiGe BiCMOS technology platform, and achieves insertion loss < 5.5 dB with a 360° phase shift range, for frequencies up to 145 GHz. By using dual voltage control, the insertion loss variation is kept within ±0.9 dB by selecting the appropriate points. This phase shifter achieves competitive performance in terms of insertion loss, power consumption, and amplitude error while operating over a wide bandwidth. [ABSTRACT FROM AUTHOR]

A very detailed investigation of high-speed silicon–germanium (SiGe) heterojunction bipolar transistors (HBTs) showed an underestimation of the measured peak cutoff frequency by simulations with a hydrodynamic (HD) model. It was speculated that this might be due to a breakdown of the HD approximation or unknown additional mechanical stress. We repeated those simulations with the more fundamental Boltzmann transport equation (BTE) based on the same device model (doping profiles, 2-D geometry, parasitics, and so on) and obtained almost similar results showing that this failure was not due to a breakdown of the HD approximation. Since additional uniaxial stress along the direction of the lateral base has been shown to increase the cutoff frequency, we investigated this effect. We found by 2-D device simulations that the increase in the peak cutoff frequency is rather small, and at high stress levels, it even decreases, if the uniaxial stress is applied homogenously. This is due to the reduction of the conductivity of the highly doped collector layer by the stress. If the stress is limited to the intrinsic transistor, the increase in the cutoff frequency is monotonic with growing stress. On the other hand, the collector current for a given base–emitter voltage also increases with stress leading to an overestimation of the collector current compared with the measurements. If this increase is corrected by a slight decrease in the germanium profile, the gain in the peak cutoff frequency is lost. Thus, the underestimation of the peak cutoff frequency cannot be explained by an additional homogeneous uniaxial stress in the intrinsic transistor. [ABSTRACT FROM AUTHOR]

A comprehensive analysis is derived to understand the mechanism of phase errors in cascode CMOS variable gain amplifiers (VGAs). According to the analysis, source–drain parasitic capacitors ($C_{\mathrm {ds}}$) of common gate (CG) transistors in off-region are the main causes for phase errors. An independent cascode current canceling (ICCC) VGA is proposed to relax phase errors by minimizing the effect of $C_{\mathrm {ds}}$ within a broadband. The proposed VGA achieves a 16-dB gain control with a 1.6° phase error and a 0.2-dB gain error from 15 to 25 GHz by 40-nm CMOS technology. Owing to the cascode structure, the peak gain of the VGA is 12 dB with only one stage including input–output pads consuming 16-mW power from 1.1-V voltage. Besides, the VGA can also serve as a 180° phase shifter (PS) due to ICCC structure with a 1.5° phase error and a 0.2-dB gain error from 15 to 25 GHz. The measured −3-dB bandwidth is 5 GHz, and output 1-dB compression point (OP1dB) is over 2.5 dBm in the maximum gain state. The core area is 0.065 mm2 excluding input–output pads. [ABSTRACT FROM AUTHOR]

Optical transceivers with more than 50 GBd are now being deployed, while the use of more than 100 GBd is currently under investigation. CMOS components, such as the analog-to-digital converter (ADC) in the receiver path, can be highly parallelized for higher sampling rates but are difficult to scale toward higher analog bandwidths. Thus, the hybrid integration of front-end circuits with the function of a bandwidth gearbox in other semiconductor technologies is an interesting research topic. In this article, we show an example of a time-interleaved analog demultiplexer (ADeMUX) with four track-and-hold (T/H) circuits based on switched emitter followers (SEFs) in a 90-nm silicon-germanium (SiGe)-Bipolar-CMOS (BiCMOS) technology for parallel operation of four CMOS ADCs. The 50% duty cycle of the clock signal facilitates its generation and can save power consumption in the clock path or enable higher sampling rates compared with the 25% duty-cycle clock of other ADeMUX architectures. We show that using switched preamplifiers in front of the SEFs can double the bandwidth of each T/H lane. Experimental verification shows up to 57-GHz input bandwidth while requiring only 16-GHz input bandwidth for each of the ADCs that can be connected to the four 32-GS/s output channels. The circuit achieves 3–6-bit accuracy and is suitable for 100-GBd signaling and beyond with pulse amplitude modulation. To demonstrate the capability of higher sampling rates, measurement results at 4 $\times $ 50 GS/s = 200 GS/s are provided as well although significant advancement of the measurement environment is needed for a complete evaluation. [ABSTRACT FROM AUTHOR]

Self-heating effect (SHE) is a severe issue arising in the nanoscale field-effect transistors (FETs). It raises the device’s lattice temperature several degrees higher than the ambient temperature and degrades the driving current. The diamond-based dielectric material may be a promising candidate to mitigate the SHE due to its significantly larger thermal conductivity value ($\text{k}_{\mathrm{ th}}= 2000$ W.m−1.K−1) than SiO2 ($\text{k}_{\mathrm{ th}}= 1.4$ W.m−1.K−1). In this paper, we have investigated the potential of crystalline diamond to mitigate the SHE-induced degradation in a partially depleted silicon-on-diamond Nanosheet FET (PDSOD NSFET). The results are compared with the partially depleted silicon-on-insulator (PDSOI) NSFET. Using extensive TCAD simulations, we investigated the impact of varying the ambient temperature and nanosheet thickness on the performance metrics of PDSOD and PDSOI NSFET. Thus, our analysis reveals that PDSOD NSFET is a viable alternative to alleviate the SHE-induced thermal degradation for the same footprint area of SiO2 used in PDSOI NSFET. [ABSTRACT FROM AUTHOR]

Many different methods have been proposed in the literature for the extraction of the thermal resistance of heterojunction bipolar transistors (HBTs). This review presents a detailed evaluation and discussion of several widely used methods. Special emphasis is put on a generalized analysis of the underlying assumptions, suitable operating point range, and necessary measurement effort of each method. The accuracy of each method is determined by applying it to data based on circuit simulations of advanced SiGe and III-V HBT technologies. Experimental data from those technologies are used to highlight practical issues. A guideline for the selection of the most suitable method in practice is also given. [ABSTRACT FROM AUTHOR]

In this work, a new buried oxide nanosheet field-effect transistor (BO-NSFET) structure is proposed for the first time as a strategy for improving the leakage of 3-nm stacked nanosheet field-effect transistors (NSFETs) by locally inserting an oxide material only under the gate region. NSFETs with punchthrough stoppers (PTSs) doping of the substrate region have been widely adopted to reduce substrate leakage; however, band-to-band tunneling (BTBT) under negative bias remains a serious problem in such devices. By only inserting the oxide material under the gate region, the electric field from the gate to the drain–substrate junction is dispersed. Furthermore, since there is no oxide material under the source and drain (S/D) region, there is no stress reduction along the channel direction coming from the silicon-on-insulator (SOI) structure. We performed technology computer-aided design (TCAD) simulations, and the results show that the proposed structure effectively reduces both the tunneling current in the NSFET with PTS structure and the OFF-current in the NSFET without PTS structure, compared with those of conventional NSFETs. [ABSTRACT FROM AUTHOR]

Methodologies for characterization of the lateral indentation of silicon-germanium (SiGe) nanosheets using different non-destructive and in-line compatible metrology techniques are presented and discussed. Gate-all-around nanosheet device structures with a total of three sacrificial SiGe sheets were fabricated and different etch process conditions used to induce indent depth variations. Scatterometry with spectral interferometry and x-ray fluorescence in conjunction with advanced interpretation and machine learning algorithms were used to quantify the SiGe indentation. Solutions for two approaches, average indent (represented by a single parameter) as well as sheet-specific indent, are presented. Both scatterometry with spectral interferometry as well as x-ray fluorescence measurements are suitable techniques to quantify the average indent through a single parameter. Furthermore, machine learning algorithms enable a fast solution path by combining x-ray fluorescence difference data with scatterometry spectra, therefore avoiding the need for a full optical model solution. A similar machine learning model approach can be employed for sheet-specific indent monitoring; however, reference data from cross-section transmission electron microscopy image analyses are required for training. It was found that scatterometry with spectral interferometry spectra and a traditional optical model in combination with advanced algorithms can achieve a very good match to sheet-specific reference data. [ABSTRACT FROM AUTHOR]

A novel vertical C-shaped-channel nanosheet field-effect-transistor (VCNFET) featured with precise control of channel-thickness and gate-length, and a unique integration flow of Dual Side Process (DSP) are proposed in this work. The VCNFETs were fabricated by high quality Si/SiGe epitaxy, atomic layer etching with nanometer-scale process control and self-aligned high-k metal gate (HKMG). The integration flow is compatible with mainstream CMOS technology. Thanks to the precise control of channel thickness and doping profiles, perfect SS of 61 mV/dec, small DIBL of 8 mV/V, and remarkably large $\text{I}_{\text {on}}/\text {I}_{\text {off}}$ ratio of ${6.28}\times {10}^{{9}}$ were achieved. The device performance and it’s optimization were also investigated with the reduction of the external resistance and numerical simulations. [ABSTRACT FROM AUTHOR]

This letter presents a differential two-stage cascode $D$ -band low-noise amplifier (LNA) using IHP’s $0.13~\mu \text{m}$ SiGe BiCMOS technology. Both gain-peaking and noise-reduction techniques are applied, and a proper interstage matching for an improved linearity is implemented and thereby, the best FoM is achieved among the reported silicon-based $D$ -band LNAs up to date. The small-signal gain is 20 dB at 140 GHz with a 3-dB bandwidth of 31 GHz. The LNA exhibits a simulated noise figure of 5.9 dB and an input-referred 1-dB compression point of −19.7 dBm, which demonstrates a leading-edge performance. The total occupied chip area is 0.4 mm2 including the pads, and the LNA core occupies only 0.1 mm2. The proposed differential LNA consumes a total of 31.8 mW from a 2-V supply. [ABSTRACT FROM AUTHOR]

An efficient, broadband SiGe HBT cascode nonuniform distributed power amplifier (NDPA) is presented for low-cost, fully integrated Si-based phased arrays. Optimum load impedances at each SiGe HBT cascode in a four-stage NDPA core are obtained by scaling the characteristic impedance ($Z_{0}$) of the collector transmission lines (TLs) and tapering the SiGe HBT emitter area simultaneously. A novel compact, lumped-element two-section $\lambda $ /4 output impedance transformer (OIT) is proposed to lower the NDPA load impedance ($Z_{L}$) from 50 to 25 $\Omega $ over more than one decade bandwidth (BW). Each $\lambda $ /4 impedance transformer is realized by four cascaded CLC $\pi $ -networks integrated into a single three-turn symmetric inductor in order to achieve compact size, high passive efficiency, and high LC cutoff frequency ($f_{c}$). The systematic design approach of a lumped-element $\lambda $ /4 impedance transformer with an arbitrary $Z_{0}$ is described in detail. The prototype NDPA was fabricated in 0.13- $\mu \text{m}$ SiGe HBT BiCMOS technology. The proposed SiGe HBT cascode NDPA supports both high linearity (HL) and high gain (HG) modes, each suited to a specific application. The NDPA attains a peak power gain of 10.3/12.5 dB, a saturated output power ($P_{\mathrm {out}}$) of 21.3/21.5 dBm, and a power added efficiency (PAE) of 12.2%/12.5%–21.6%/22.0% for HL/HG modes, with a 3-dB BW from 1.5 to 24.0 GHz. The NDPA delivers 13.0-dBm average $P_{\mathrm {out}}$ with a PAE of 10.0% at 6-Gbit/s data rate 64 QAM modulation. [ABSTRACT FROM AUTHOR]

This letter presents an on-chip ultra-wideband (UWB) bandpass filter (BPF) in 0.18- $\mu \text{m}$ SiGe BiCMOS Process. The proposed UWB BPF is constituted by cascaded quasi-elliptic response high-pass filter (HPF) and low-pass filter (LPF). A series LC circuit is introduced in the classical fifth-order lumped-element HPF, so that a transmission zero (TZ) is generated to form quasi-elliptic response. The microstrip line LPF with two series of open stubs can generate another two TZs, which also result in quasi-elliptic response. Step-to-step design procedure is given to guide the UWB BPF design. The measured result shows that the fabricated UWB BPF covers the frequency range of 10 – 50 GHz with the in-band return loss better than 13.5 dB, and the minimum in-band insertion loss is 1.99 dB. The core size of fabricated UWB BPF is 382 $\mu \text{m}\,\,\times 428\,\,\mu \text{m}$ excluding testing pads. [ABSTRACT FROM AUTHOR]

This letter presents a 220–261-GHz frequency multiplier-by-18 chain in a 130-nm SiGe BiCMOS technology. It consists of three amplifiers (12–15, 110–135, and 216–270 GHz), two frequency triplers (36–45 and 108–135 GHz), a third-order Chebyshev bandpass filter (36–45 GHz), and a modified Gilbert-cell-based frequency doubler (216–270 GHz). The peak output power is about 8 dBm at 240 GHz with a 3-dB bandwidth of 41 GHz for an input power of −7 dBm. The unwanted harmonics are suppressed more than 25 dBc over the frequency range of interest. It consumes a dc current of 114.7 mA from a supply voltage of 3.3 V in the quiescent operation and drains a current of 130 mA for an input power of −7 dBm, which results in a drain efficiency of 1.47%. The total circuit occupies an area of 0.58 mm 2 (1.35 mm $\times0.43$ mm). [ABSTRACT FROM AUTHOR]

The advantages and the tradeoffs associated with the use of inverse-mode (IM) silicon–germanium (SiGe) heterojunction bipolar transistors (HBTs) biasing circuitry in radio-frequency (RF) voltage-controlled oscillators (VCOs) have been investigated and the performance of proposed VCOs (IM VCOs) is compared with VCOs with conventional forward-mode (FM) SiGe-HBTs (FM VCOs). Where the high-frequency performance of IM VCOs is inevitably degraded due to unfavorable device optimization unlike FM VCOs, IM VCOs provide acceptable low-GHz VCO circuit performance. In terms of single-event effects (SEEs), the IM VCOs show reduced transient peaks and duration in comparison with conventional FM VCOs. In addition, the performance of the VCOs is analyzed in terms of transient error vector magnitude (TEVM) in an RF receiver (RX) using quadrature phase-shift keying (QPSK) modulation under a radiation environment. The IM VCOs in the RX circuit show better reliability under SEEs, offering 28.2% lower TEVM at a 64 Mb/s data rate, than that of the RX circuit with conventional FM VCOs. Therefore, the application of IM SiGe-HBT biasing circuits for RF VCOs can be a viable SEE-hardening technique for space-based RF systems. The VCO prototype was fabricated using IHP 130-nm SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. [ABSTRACT FROM AUTHOR]

Deep learning and artificial intelligence, in general, is advancing scientific discovery and technological inventions through its ability to extract inherently hidden features and map it to output in a highly complex multi-dimensional space. Synthesis of electromagnetic (EM) structures with nearly arbitrary with desired functional properties is such an example of a high dimensional optimization space. In this article, we employ deep convolutional neural network (CNN) to allow robust and rapid prediction of scattering properties of nearly arbitrary planar electromagnetic structures on chip. Utilizing this, the work reports an mm-wave PA in 90-nm SiGe with a novel deep learning-enabled inverse design of low-loss, broadband output matching network that achieves a PAE of 16%–24.7%, a saturation power of 16.7–19.5 dBm across Psat, 3 dB bandwidth of 30–94 GHz (103.2%), while supporting both single-carrier high-speed modulation and concurrent multiband multi-Gb/s non-constant amplitude modulation. The Psat, 3 dB bandwidth covers from 5G band up to W-band and is higher than all reported mm-wave silicon PAs which have peak PAE > 20% and demonstrates for the first time concurrent multiband (triple-band) transmission with superior performance at multi-Gb/s. [ABSTRACT FROM AUTHOR]

This work presents a compact, concurrent dual-band (36/64 GHz) linear power amplifier in 90 nm SiGe technology. To simultaneously overcome the gain and power limitation of conventional common-emitter (CE) silicon device at mm-wave, the stacked common-base (SCB) topology in SiGe is studied and utilized as PA cell. A highly efficient dual-band output network enables the optimum load-line matching for two widely separated frequencies. The proposed PA achieves 20/18.8 dBm $P_{\mathrm {sat}}$ , 25/22.5% PAE at 36/64 GHz supporting two concurrent 32 QAM signals (total data rate of 9 Gb/s) with 9.5/7.8 dBm linear average power respectively, and concurrent PAE of 8.9%. To the best of the authors’ knowledge, this prototype achieves highest dual frequency output power, PAE, and one of the first concurrent dual-band modulation among silicon-based mm-wave PAs, while still maintaining a highly compact footprint. [ABSTRACT FROM AUTHOR]

The high frequency and noise performance ($T_{\mathrm {MIN}}$ , NFMIN, $R_{n}$ , and $Z_{\mathrm {sopt}}$) of SiGe heterojunction bipolar transistors (HBTs) are characterized for the first time from dc and $S$ -parameter measurements up to 70 GHz and from 2 to 400 K. Significantly improved current gain ~10 000, minimum noise temperature, $T_{\mathrm {MIN}}$ (< 1 K below 8.5 GHz), MAG, $f_{T}$ (458 GHz), and $f_{\mathrm {MAX}}$ (534 GHz) are observed at 2 K compared to 300 K, with no evidence of impurity deionization. It is found that the optimum noise figure current density, $J_{\mathrm {OPT}}$ , increases with temperature, following the crossover between shot noise and thermal noise. In contrast, the peak- $f_{T}$ and peak- $f_{\mathrm {MAX}}$ current densities increase by more than 50% at 2 K, likely due to the higher $v_{\mathrm {sat}}$. A decrease in BVCEO, expected due to the higher current gain, and negative output conductance are observed in the 2–200 K range in the dc output characteristics at large currents above the peak- $f_{T}$ current. [ABSTRACT FROM AUTHOR]

Low-voltage and low-power frequency multiplier blocks used in millimeter-wave RF frontends suffer from high conversion loss leading to lower overall efficiency. In this letter, an alternative approach in the design of a low-power ${V}$ -band frequency doubler (FD) block without requiring an additional buffer stage is presented. The transconductance stage of a conventional Gilbert multiplier is replaced by a passive trifilar transformer serving as a power splitting, matching, and biasing network. The switching quad transistors are biased with the lowest possible dc current which still provides a positive conversion gain. Experimental results show that the circuit implemented in a 130-nm SiGe BiCMOS technology achieves 14% total efficiency at 58 GHz for an input power of 0 dBm while consuming only 7.2 mW of dc power. The measured saturated output power is 2 dBm and the measured fundamental rejection ratio (FRR) is 49 dBc. To the best of the authors’ knowledge, the lowest power consumption while maintaining a positive conversion gain among high FDs based on silicon is reported. [ABSTRACT FROM AUTHOR]

This letter presents a 16–24-GHz decibel-linear low-gain-error variable gain amplifier (VGA) in 130-nm SiGe technology. Negative feedback resistor is used in current source to expand the gain variation range and improve decibel-linearity. The nonproportion metal-oxide-semiconductor (MOS) array is introduced to reduce the gain variation error. This design achieves a 15–0 dB gain variation range at 1-dB gain step with root mean square (rms) gain-error less than 0.3 dB. The measured OP1dB is greater than 9.5 dBm between the 1-dB bandwidth of 16–24 GHz and this VGA consumes 8.8 mA from a 1.6-V supply. [ABSTRACT FROM AUTHOR]

Noise probably the single most important performance metric of the high-speed transimpedance amplifier (TIA), which directly sets the sensitivity of optical receiver. The transimpedance limit which dictates the maximum achievable transimpedance gain of the TIA also turns out to fundamentally limit the TIA noise performance. In this tutorial, we analyze and explore two circuit design approaches to overcome the transimpedance limit. The first approach (Type I) realizes a divide-and-conquer methodology to separate the noise-bandwidth problem and solve them individually. The second approach (Type II) employs a multi-stage stagger-tuned amplifier. Both approaches can overcome the transimpedance limit, forming an effective toolkit for the design of low-noise high-speed TIA for high-sensitivity CMOS optical receivers in current and future applications. [ABSTRACT FROM AUTHOR]

The total-ionizing-dose response of third-generation SiGe HBTs was investigated at elevated temperatures (80 °C and 130 °C) and compared with the response at 30 °C. The devices show less damage to irradiation at higher temperatures. Annealing experiments and TCAD simulations are used to investigate the degradation mechanism. The reduced degradation in forward mode at elevated temperatures is caused by increased annealing of interface traps primarily due to diffusion and reactions of H2 within the oxide/nitride EB spacer. The degradation is modest at all measured temperatures, allowing these devices to be suitable for radiation-rich environments where elevated temperatures are expected. [ABSTRACT FROM AUTHOR]

The individual and mixed radiation experiments of gamma rays and neutrons were performed to evaluate the irradiation synergistic effects (ISEs) of ionizing dose and displacement damage on SiGe heterojunction bipolar transistors (HBTs). These results indicate that the SiGe HBTs in this work experience a significant sensitivity of ISEs and the degradation of base current induced by mixed irradiation was more severe than that of simple artificial sum of individual irradiation. The degradation of SiGe HBTs induced by mixed radiation does not vary with $V_{\mathrm {BE}}$ linearly, but is significant at low injection and weakened at high injection. [ABSTRACT FROM AUTHOR]

A wide tuning range, low-phase-noise SiGe BiCMOS LC voltage-controlled oscillator (VCO) covering both the Ku- and Ka-bands is presented in this letter. The proposed VCO using a cross-coupled topology creates the fundamental harmonic from 14.35 to 17.86 GHz and the second harmonic, which is drawn from the common-mode point through a matched buffer, covering from 28.7 to 35.72 GHz. A transformer-coupled tank, which takes advantage of tank parasitics to create harmonic resonances, is used to reduce the phase noise (PN). The 5-bit binary-weighted capacitor bank is connected to the transformer secondary to create a wide tuning range, which is measured from 14.35 to 17.86 GHz (21.1%) and 28.7 to 35.72 GHz. Brilliant PN of −115.5 and −109 dBc/Hz at 1-MHz offset is measured at 14.53- and 29.1-GHz carrier frequencies individually. The proposed VCO with an extra output of the second harmonic exhibits little PN deterioration. [ABSTRACT FROM AUTHOR]

This article introduces a millimeter-wave (mm-wave) multi-band transmit (Tx) phased-array design supp- orting the fifth-generation (5G) new radio frequency range 2 (NR FR2) bands. An eight-element phased-array module is presented employing two wideband 16–52 GHz $4{\times }1$ Tx beamformer chips and tapered slot Vivaldi antenna array. The beamformer chips are designed in a SiGe BiCMOS process and flipped on a printed circuit board (PCB). The SiGe integrated circuit (IC) has four differential radio frequency (RF) beamforming channels each consisting of an active balun, analog adder-based phase shifter (PS), variable gain amplifier (VGA), and a two-stage class-AB power amplifier (PA). The RF input signal is distributed to the four channels using a compact Wilkinson network. The measured peak gain is 28.3 dB with 13.5–14.7 dBm output $P_{1{\mathrm {dB}}}$ and 14–15.4 dBm $P_{{\mathrm {sat}}}$ at 20–50 GHz. Each channel dissipates 250 mW from 2 V and 3-V supplies at $P_{1\,{\mathrm{ dB}}}$. The beamformer chip is tested using 64-QAM waveforms and achieves a data rate of 2.4 Gb/s at 5.2% rms EVM and 9.6-dBm average power. The eight-element phased-array module shows a broadband performance with excellent patterns and ±60° scanning capability and with a peak effective isotropic radiated power (EIRP) of 32–34 dBm at 19.5–51 GHz. At an EIRP of 21–22 dBm, 400-MHz 256-QAM 5G-NR compliant waveforms are transmitted with < 2.98% EVM demonstrating 5G NR FR2 operation. To the author’s knowledge, this work achieves the highest bandwidth phased array with a peak EIRP of 34 dBm enabling the construction of multi-standard/multi-band 5G phased-array systems. [ABSTRACT FROM AUTHOR]

This paper provides the details of a study on the effects of electron irradiation on two Low Noise Amplifiers (LNA), the Gallium-Arsenide (GaAs) pseudomorphic high electron mobility transistor (pHEMT) based and the Silicon-Germanium (SiGe) Heterojunction Bipolar Transistor (HBT)-based. Previous studies have shown that the properties of GaAs and SiGe HBT’s are very tolerant of gamma, neutron, and proton irradiation without additional radiation hardening. Nowadays, commercials on the shelves (COTS) LNAs have been used in CubeSat space communication systems which may be connected to other communication networks for the implementation of the space-aerial- terrestrial integrated 5G network (SATIN) systems projects, for satellites, launched into Low and Medium Earth Orbits. Previous studies suggest that the electron radiation in space may degrade the LNAs’ performance and might even lead to its failure. Located at the front end of the communication receiver system, this paper conducted such investigation to evaluate the performance under the radiation of the GaAs and SiGe LNAs considering the physics of the technology of each LNA, respectively. The results indicate that both SiGe and GaAs technologies are affected after electron irradiation. As a result, this degradation of the LNAs’ performance affected the communications system performance of the inter-satellite radio link. After the assessment of the quality performance of the communication link at the system level, it has been found that the inter-satellite space link will be at risk under high space radiation dose and the link BER degrades proportionally to the radiation dose level.

This paper presents the calibration of the novel kinetic velocity model (KVM) in the drift-diffusion (DD) transport approach, which can account for the ballistic effect in short-channel devices. The KVM considers a thermionic emission limit and a free carrier acceleration limit for the mobility. We develop a methodology to extract the parameters for the KVM and for the high-field saturation velocity model for SiGe nanowires over the whole mole fraction range. The calibrated DD simulations with KVM show good agreement with Boltzmann transport equation results in terms of on-state current and carrier-weighted velocity distribution over a wide range of gate lengths for both linear and saturation regimes.

The degradation characteristics of silicon-germanium heterojunction bipolar transistors (SiGe HBTs) under different bias modes (forward, cutoff and saturation) during irradiation were reported after multiple pulsed neutron-gamma irradiation at room temperature. The radiation-sensitive parameters of the test samples, including base current IB, collector current IC and DC current gain $\beta $ , were measured and compared before and after every reactor n- $\gamma $ pulse irradiation. The test results show that IB increased with increasing fluence, and IC slightly increased in the low base-emitter voltage VBE region (approximately from 0.4 V to 0.5 V) and decreased in the high-VBE region (approximately VBE >0.5 V). Moreover, the degradation degree of the test samples was different under different bias conditions. The performance of the test samples under cutoff bias mode displayed the most serious degradation, while those under forward bias mode suffered minimum damage. Meanwhile, the time-dependent annealing characteristics of the DC current gain for SiGe HBTs at various bias conditions were compared and analyzed.

This work presents a 300-GHz low-noise amplifier (LNA) in a SiGe:C 130-nm BiCMOS technology, featuring $f_{t}/f_{\text {max}}$ of 470/700 GHz. The designed amplifier uses three cascaded stages in a pseudo-differential cascode topology with input and output baluns facilitating single-ended measurements. The first stage is matched trading off noise and gain performance, while a T-type output matching network is used for broadband matching. The interstage matching is performed using center tap transformers. On-wafer measurements show that the designed LNA has a peak small-signal gain of 10.8 dB at 325 GHz, along with a 3-dB bandwidth of 68 GHz and an input 1-dB compression point of −15.6 dBm at 287.5 GHz. The simulated noise figure is better than 12.7 dB over the required band. The circuit occupies 0.26-mm2 silicon area and consumes 119 mW from a 3.3-V supply. [ABSTRACT FROM AUTHOR]

This article demonstrates the influence of high-temperature annealing on an interfacial layer (IL) grown by O2 plasma on Si0.5Ge0.5 substrates. The X-ray photoelectron spectroscopy results revealed that under an annealing temperature of 1000 °C, the concentration of germanium oxide in the IL decreased, and an IL with pure silicon oxide (~100%) was produced. With a decrease in germanium oxide concentration, the SiGe metal oxide semiconductor capacitor exhibited an excellent interface trap density of $1.6\times10$ 12 cm−2eV−1 with negligible hysteresis. Furthermore, compared with 1000 °C IL annealing, 800 °C IL annealing was more suitable for preferential SiO2 growth without relaxation and dislocation in the SiGe layer, as observed using a transmission electron microscope. [ABSTRACT FROM AUTHOR]

Integrated silicon microwave pin diodes are exposed to 10-keV X-rays up to a dose of 2 Mrad(SiO2) and 14-MeV fast neutrons up to a fluence of $2.2\,\,\boldsymbol {\times }\,\,10\,\,^{\mathrm{ 13}}$ cm−2. Changes in both dc leakage current and small-signal circuit components are examined. Degradation in performance due to total-ionizing dose (TID) is shown to be suppressed by non-quasi-static (NQS) effects during radio frequency (RF) operation. Tolerance to displacement damage from fast neutrons is also observed, which is explained using technology computer-aided design (TCAD) simulations. Overall, the characterized pin diodes are tolerant to cumulative radiation at levels consistent with space applications such as geosynchronous weather satellites. [ABSTRACT FROM AUTHOR]

This work presents a 15–57 GHz multiband/ multistandard phased-array architecture for the fifth-generation (5G) new radio (NR) frequency range 2 (FR2) bands. An eight-element phased-array receive module is demonstrated based on two four-channel wideband beamformer chips designed in the SiGe BiCMOS process and flipped on a low-cost printed circuit board. The SiGe Rx chip employs RF beamforming and is designed to interface to a wideband differential Vivaldi antenna array. Each channel consists of a low-noise amplifier (LNA), active phase shifter with 5-bit resolution, variable gain amplifier (VGA), and differential-to-single-ended stage. The four channels are combined using a wideband two-stage on-chip Wilkinson network. The beamformer has a peak electronic gain of 24–25 dB and a 4.7–6.2 dB noise figure (NF) with a −29 to −24 dBm input $P_{\boldsymbol {1\,dB}}$ at 20–40 GHz. The eight-element phased-array module also achieved ultra-wideband frequency response with flat gain and low-system NF. The phased array scans ±55° with $ < -12$ -dB sidelobes demonstrating multiband operation. A 1.2-m over-the-air (OTA) link measurement using the eight-element Rx module supports 400-MHz 256-QAM OFDMA modulation with < 2.76% error vector magnitude (EVM) at multiple 5G NR FR2 bands. To the author’s knowledge, this work achieves the widest bandwidth phased array enabling the construction of multistandard systems. [ABSTRACT FROM AUTHOR]

A highly integrated fundamentally operated direct-conversion quadrature (IQ) TX/RX chipset with a tunable carrier of 215–240 GHz for high-speed wireless communication is presented. The TX/RX front-ends are fabricated in the 0.13- $\mu \text{m}$ SiGe HBT technology and combined with wire-bonded chip-on-board (COB) packaging for high-speed baseband (BB) signaling. For test purposes, the chipset features a dedicated dual-polarization architecture with a suitable on-chip antenna to allow controlled variation in I-to-Q channel leakage resulting from frequency-dependent upper sideband (USB)/lower sideband (LSB) asymmetry in the RF path of the jointly operated TX and RX and the corresponding analysis of its impact on system error vector magnitude (EVM) of the complete link. The analysis is aided by system-level BB-referred problem formulation with similarity to the classical IQ error in the local oscillator (LO) and BB paths. While operated in a loop-back configuration, the front-ends support the LO-dependent BB-referred channel bandwidth (BW) of 16–20 GHz at the board level with the typical free-space-related double sideband (DSB) Psat/OP1 of 7/3.5 dBm and single sideband (SSB) conversion gain (CG)/noise figure (NF) of 7.5/17.5 dB for the TX and RX, respectively. Under regular working conditions, data rates above 80 Gb/s are demonstrated for 16-quadrature amplitude modulation (QAM) modulation in a 0.6-m line-of-sight wireless characterization setup, with the maximum of 100 Gb/s at 225 GHz. The achievable speeds are limited by frequency-dependent USB/LSB asymmetry in the RF path resulting in systematic error vector floor independently of the underlying SNR and IQ error. With elimination of the asymmetry-incurred I-to-Q leakage from the RF path, the potential of increasing the data rates to at least 120–140 Gb/s is shown, indicating the severeness of this RF impairment for wide modulation bandwidth. [ABSTRACT FROM AUTHOR]

This brief presents a wideband, low insertion loss, high attenuation range digital step attenuator (DSA) implemented using SiGe HBTs. In a switched-type topology, the off-state capacitances ($\text{C}_{OFF}$) in both reference and attenuation states cause different poles and zeros, which trigger amplitude and phase errors and limit the operating bandwidth. To achieve wide bandwidth, methods to relocate poles and zeros to the highest possible frequencies in both states are investigated. In the reference state, minimizing the size of the shunt switching transistors extends the bandwidth. In the attenuation state, switching in a capacitor at the base of an anti-parallel (AP) SiGe HBT pair series switch reduces the effective $\text{C}_{OFF}$ , enhancing the bandwidth. The proposed techniques facilitate the realization of a 16-dB attenuator cell to support wide bandwidth and offer lower insertion loss than conventional cascaded 8-dB cell designs. Fabricated in 130-nm SiGe BiCMOS technology, the proposed DSA with an attenuation range of 31.5 dB in 0.5 dB steps operates from DC to 67 GHz and achieves an insertion loss lower than 7.8 dB. The RMS amplitude error is less than 0.4 dB above 1 GHz, while the RMS phase variation is less than 13.1°. [ABSTRACT FROM AUTHOR]