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A high-Ge-content Si1–yGey/compositionally graded Si1–xGex-stacked structure grown on Si(001) is now considered to be an important platform for the realization of advanced nanometer-scale complementary metal oxide semiconductor devices with high-mobility channel materials, such as III–V materials and Ge, and monolithically integrated photonic modules. The performance of such advanced devices is critically influenced by crystalline inhomogeneity in the stacked structure; therefore, precise characterization of the crystallinity is important. In particular, the development of a characterization method not only for in-plane crystallinity but also for in-depth crystallinity is strongly required. This is because the crystalline quality of the constant composition Si1–yGey is sensitively dependent on that of the compositionally graded Si1–xGex layers underneath. Here, we have demonstrated in-depth tomographic mapping of a high-Ge-content Si1–yGey/compositionally graded Si1–xGex-stacked structure using position-d...

Resistive switching (RS) was demonstrated in four-terminal planar memristive devices fabricated on reduced TiO2 (TiO2−x) single crystal substrates. In the device, a pair of diagonally opposing electrode terminals is used to modify the distribution of oxygen vacancies in the region between another pair of diagonally opposing electrode terminals. This allowed microscopic visual observations of the oxygen vacancy distribution based on electrocoloring. The visual contrast observed in the TiO2−x reflects the oxygen vacancy concentration in the electrically active zone of the device, which can be modified by application of various external voltages to the electrodes. The current that flows in the device is significantly dependent on the modified oxygen vacancy distribution and the resultant resistance is switchable when the polarization of the applied external voltage is reversed. The crystallographic orientation of the TiO2−x substrate has a strong influence on the reversible RS phenomenon. Mechanisms behind the voltage-driven resistance change are elaborated with the aid of microscopic analysis for both crystalline and electronic structures in the electrically active zone of the device. Suppression of the formation of irreversible conductive structures comprised of accumulated oxygen vacancies is a key to establishing reversible RS in the device.

We present a carrier-doped Si nanoarchitecture for thermoelectric material, consisting of a stacked structure of carrier-doped Si layer/Si nanocrystals (NCs) with oriented crystal. The NCs and carrier-doped Si layers act as phonon scattering centers and carrier transport layers, respectively. The NCs were covered with ultrathin SiO2 films. Solid-phase epitaxy (SPE) of the Si layers on the amorphous ultrathin SiO2 films was achieved using nanowindows in the ultrathin SiO2 films. By such integration of the ultrathin SiO2 film technique for epitaxial growth of NCs and the SPE method, we fabricated a Ga-doped Si nanoarchitecture and achieved carrier doping of 1018 cm−3 to 1019 cm−3. The thermal conductivity was reduced to a value similar to that of amorphous Si. The thermal resistance per stacking layer in the nanoarchitecture was 7 to 10 times higher than that of connected Si NCs, which exhibited thermal conductivity 200 times smaller than that of bulk Si. This large thermal resistance in the nanoarchitecture may result from precipitation of Ga atoms at the ultrathin SiO2 film interfaces. These Ga atoms played two roles: as dopants for electrical conductivity enhancement and as phonon scatters for thermal conductivity reduction. This nanoarchitecture demonstrates the possibility of achieving high electrical conductivity and low thermal conductivity.

A Si-based nanomaterial is proposed for use as a thermoelectric material. Ultrasmall epitaxial Ge nanodots (NDs) with an ultrahigh density are introduced into Si films as phonon scatterers using an ultrathin SiO2 film technique. The nanomaterial has the stacked structure Si/Ge NDs/Si on Si substrates. Reflection high-energy electron diffraction reveals epitaxial growth of the Ge NDs and Si layers in all of the stacking stages. Sharp interfaces of the Ge NDs/Si in the stacked structures were observed by high-angle annular field scanning transmission electron microscopy. The Ge NDs were controlled in terms of their composition and strain: main parts of the NDs did not alloy with Si, and the elastic strain was relaxed. These features were confirmed by Raman scattering and x-ray diffraction measurements. The fabrication techniques used to make the simple Si-based stacked structure with strain-relaxed almost pure Ge NDs are useful to develop thermoelectric nanomaterials.

We have investigated the crystalline morphology such as lattice plane curvature and lattice plane tilting in (20–21) GaN films on (22–43) patterned sapphire substrates (PSS) by using X-ray rocking curve (XRC) measurements. The results of the symmetric XRC for the GaN (20–21) plane showed anisotropic lattice plane curvature between the [−1014] and [−12–10] directions. This is due to the large difference of the thermal expansion coefficient in the [0001] direction between GaN and sapphire. From the results of asymmetric XRC for the GaN (20–22) and (12–31) diffractions, it is found that lattice plane tilting is highly dependent on the film thickness and the growth condition. The −c-plane-suppressed growth process with tuning the V/III ratio for the (20–21) GaN films on the (22–43) PSS is very effective to suppress the generation of basal plane stacking faults as confirmed by TEM analysis.

We have investigated the microscopic crystalline morphology such as lattice plane tilting and defects in semipolar (20–21) GaN films grown on (22–43) patterned sapphire substrates (PSS) by using position-dependent ω–2θ map measurement of X-ray microdiffraction (XRMD) combined with transmission electron microscopy (TEM). The results of the position-dependent ω–2θ map measurement for the GaN (20–21) plane showed periodic variation of the diffraction spot shapes depending on the patterning pitch of the PSS. Broadening of the diffraction spots in the terrace area and single diffraction spots in the grooved one were also observed. These results indicate that the lattice plane tilting of the GaN film depends on the PSS structure and the presence of the defective GaN film on the terrace area where basal plane stacking-fault generation occurred, as confirmed by TEM.

The microscopic crystalline structure (MCS) such as domain texturing, lattice tilting fluctuation and strain fluctuation in thick AlN films grown on trench-patterned AlN/α-Al2O3 templates was clarified by utilizing position-dependent X-ray microdiffraction measurements in combination with transmission electron microscopy observations. The results clearly demonstrate that the trench-patterned templates have a strong influence on the MCS in the thick AlN films. The MCS is anisotropic between the [ 11 2 ¯ 0 ] and [ 1 1 ¯ 00 ] directions. Periodic domain texturing was observed along the [ 11 2 ¯ 0 ] direction, corresponding to the periodicity of the patterning pitch of the template. Submicron crystal domains are tilted at different angles to the [ 11 2 ¯ 0 ] direction, and the crystal domain tilting becomes larger in the void-containing trench regions than in the terrace regions. This generates the periodicity in lattice tilting fluctuation and strain fluctuation along the [ 11 2 ¯ 0 ] direction. These were found to be caused primarily by two factors; one of which being the elastic strain relaxation that depends on the growth direction in the terrace regions, and the other being the inhomogeneity in distribution and morphology of dislocations that have Burgers vectors with a screw component in the void-containing trench regions.

A non-precious metal catalyst (NPMC) promoting a four-electron oxygen reduction reaction (ORR) was synthesized by heat treatment of myoglobin (Mb) containing a heme (iron protoporphyrin IX) as a source of iron, nitrogen, and carbon atoms. Samples of the mixture of Mb and carbon black (Vulcan XC72R: VC) were pyrolyzed at 740, 840, 940, 1040 or 1140°C under N2flow. The microstructures of the carbonized Mb catalysts were characterized by XRD, Raman spectroscopy, XPS, and TEM. Results indicate that the iron-containing active site is embedded within the surface structure in an amorphous domain of the carbon materials. The catalyst ink in a 0.05 wt% Nafion solution in isopropanol was coated onto a glassy carbon electrode and the ORR activity of Mb-based NPMCs was evaluated in a rotating disk electrode experiment in an O2-saturated 0.1 M HClO4solution at 25°C. The catalyst synthesized at 940°C has the highest ORR activity in terms of the onset potential and the current density. In contrast, pyrolytic temperatures above 940°C decrease the activity, suggesting that the active structure of the catalyst apparently decomposes at higher temperatures. The Koutecky–Levich plots indicate that the Mb-based catalyst prepared at 940°C catalyzes four-electron ORR (n = ca. 4). The catalysts prepared at other temperatures have n values of 3.6 at 740°C, 3.7 at 840°C, and 2.9 at 1040°C. The ORR of Mb/VC is diffusion-controlled at potentials lower than 0.3 V (vs. RHE) and the onset potential is 0.84 ± 0.01 V.

We investigated local strain distribution in a cross-sectional area throughout the thickness of a thick aluminum nitride (AlN) film epitaxially grown on a trench-patterned AlN/α-Al2O3 template using X-ray microdiffraction measurements for AlN and Bragg reflections. The results show that the presence of voids caused by the trench pattern strongly influences on the distribution of the strain components in the and directions, which are perpendicular to the trench lines. Discrepancy between strain values obtained from the two Bragg reflections was shown to be the result of twisting of the crystal domains about the axis in the thick AlN film.

We have investigated dislocation behavior in the surface area of surface-oxygen-concentration controlled Si wafers treated by a high temperature rapid thermal oxidation (HT-RTO). The HT-RTO process allows us to precisely control the interstitial oxygen concentration ([O i ]) in the surface area of the Si wafers. Sizes of rosette patterns, generated by nano-indentation and subsequent thermal annealing at 900 °C for 1 h, were measured for the Si wafers with various [O i ]. It was found that the rosette size decreases in proportion to the − 0.25 power of [O i ] in the surface area of the Si wafers, which were higher than [O i ] of 1 × 10 17 atoms/cm 3 . On the other hand, [O i ] of lower than 1 × 10 17 atoms/cm 3 did not affect the rosette size very much. These experimental results demonstrate the ability of the HT-RTO process to suppress the dislocation movements in the surface area of the Si wafer.

We have investigated crystalline morphology such as wafer curvature, mosaicity, and lattice tilting of an AlN film grown on a triangular-striped AlN/α-Al2O3 template by X-ray rocking curve (XRC) and reciprocal space map (RSM) measurements. The result of XRC for the AlN (0002) plane showed the difference of the value in the wafer curvature between the [11–20] and [1–100] directions. This indicates the anisotropic strain relaxation preferentially along [11–20] direction due to the triangular-striped structure and the voids in the AlN film. From the results of asymmetric RSMs for AlN 11–24 and 1–104 diffractions, the broadening of the reciprocal lattice spots in elliptical shape was observed. These results reflect anisotropic crystalline morphology in the AlN film. The elliptical diffraction spot for AlN 11–24 predominantly indicates the lattice tilting fluctuation around the [1–100] axes while that for AlN 1–104 indicates the lattice spacing fluctuation. Anisotropic crystalline morphology in the AlN film grown on the triangular-striped template has been clarified in combination with XRC and asymmetric RSMs.

X-ray microdiffraction (XRMD) measurements using the AlN 2 2 ¯ 01 and 1 2 ¯ 10 Bragg reflections were performed to determine the cross-sectional distribution of local residual strain and twisting of crystal domains for a thick AlN film grown on a trench-patterned AlN/α-Al 2 O 3 template. The distribution of the strain components in the [0001] and [ 11 2 ¯ 0 ] directions, which are perpendicular to the trench lines, was strongly influenced by the presence of voids caused by the trench pattern. The strains in the [ 1 1 ¯ 00 ] and [ 11 2 ¯ 0 ] directions determined using the two Bragg reflections were found to be significantly different, and this was shown to be the result of twisting of the crystal domains about the [0001] axis under the influence of anisotropic shear stress in the prismatic planes.

We have examined the epitaxial growth of Ge1-x-ySixSny layers on Ge substrates with a Sn content of 3~15% with low temperature molecular beam epitaxy method. The Ge1-x-ySixSny layers are psuedomorphically grown on Ge substrates with high crystalline quality. The surface morphology of the Ge1-x-ySixSny layers with a Sn content below 7% shows very flat and uniform, although surface roughening occurs in the sample with a Sn content as high as 15% provably due to the Sn precipitation. We also roughly estimated the energy band structure with liner approximation calculation. The energy bandgap of Ge1-x-ySixSny alloy prepared in this study is expected to be 0.8~1.0 eV at the L or X point.

Wafer bonding is an attractive process to creat new structures and materials, alternative to conventional bulk-Si substrates, in the form of substrates for the advanced metal-oxide-semiconductor field effect transistors (MOSFETs). A germanium on insulator (GOI) substrate attracts much attention because it makes the best use of the higher carrier mobility advantages compared with Si, and is suitable to further downscaling of Ge MOSFET dimensions. However, careful consideration is given especially to the bonded interface between Ge and buried oxide, which should have a device grade quality. In this work, we fabricate GOI substrates by using a wafer bonding method. Atomic structures, chemistry, and electrical properties of the Ge/BOX interface are also characterized.

The high electrical and drastically-low thermal conductivities, a vital goal for high performance thermoelectric (TE) materials, are achieved in Si-based nanoarchitecture composed of Si channel layers and epitaxial Ge nanodots (NDs) with ultrahigh areal density (~1012 cm−2). In this nanoarchitecture, the ultrasmall NDs and Si channel layers play roles of phonon scattering sources and electrical conduction channels, respectively. Electron conductivity in n-type nanoacrhitecture shows high values comparable to those of epitaxial Si films despite the existence of epitaxial NDs. This is because Ge NDs mainly scattered not electrons but phonons selectively, which could be attributed to the small conduction band offset at the epitaxially-grown Si/Ge interface and high transmission probability through stacking faults. These results demonstrate an independent control of thermal and electrical conduction for phonon-glass electron-crystal TE materials by nanostructure designing and the energetic and structural interface control.

a b s t r a c t We have investigated the effect of the irradiation of atomic deuterium (D) on the initial growth of Sn and Ge1−xSnx on Ge(0 0 1) substrates by using scanning tunneling microscopy (STM) comparing to the effect of the irradiation of atomic hydrogen (H). We found that the surfactant effect appears and the surface roughness is reduced when the surface coverage of D or H is higher than 69%. The efficiency for reducing the surface roughness increased with the coverage of D and H. Moreover, we found that D atoms effectively work as a surfactant on the Ge surface compared to H atoms under the same irradiation condition. Utilizing D as a surfactant is expected to improve the termination process of Ge surface. © 2012 Elsevier B.V. All rights reserved.

We have investigated the Ga and Sn content dependence of the crystallinity and electrical properties of Ga-doped Ge1-xSnx layers that are heteroepitaxially grown on Ge(001) substrates. The doping of Ga to levels as high as the solubility limit of Ga at the growth temperature leads to the introduction of dislocations, due to the increase in the strain of the Ge1-xSnx layers. We achieved the growth of a fully strained Ge0.922Sn0.078 layer on Ge with a Ga concentration of 5.5 × 1019 /cm3 without any dislocations and stacking faults. The resistivity of the Ga-doped Ge1-xSnx layer decreased as the Sn content was increased. This decrease was due to an increase in the carrier concentration, with an increase in the activation level of Ga atoms in the Ge1-xSnx epitaxial layers being induced by the introduction of Sn. As a result, we found that the resistivity for the Ge0.950Sn0.050 layer annealed at 600°C for 1 min is 3.6 times less than that of the Ga-doped Ge/Ge sample.

We investigated the crystalline structures of Ge1 − xSnx heteroepitaxial layers with Sn contents greater than 20% grown on InP and Ge substrates. Considering the lattice mismatch between the Ge1 − xSnx layers and the substrates, we achieved epitaxial growth of Ge1−xSnx layers with very high Sn content by suppressing the Sn precipitation; in addition, we improved upon the crystalline quality of Ge1 − xSnx heteroepitaxial layers. As a result, we could successfully form a 130 nm-thick Ge1 − xSnx heteroepitaxial layer on an InP substrate with a Sn content as high as 27% without Sn precipitation. We also improved the crystalline quality of Ge1 − xSnx layers by annealing at a temperature as low as 290 °C.

In this paper, we reports our recent studies of the electrical and crystalline properties of heteroepitaxial Ge1-xSnx layers with various Sn content of 0~25%. We examined Ga-doping in strained Ge1-xSnx layers for developing source/drain stressor in CMOS applications and investigated the effect of Sn on the doping profile. The impact of Sn on carrier properties has been also studied with the Hall measurement of Ge1-xSnx/SOI structures. Also, we achieved the epitaxial growth of Ge1-xSnx layers with a Sn content as high as 25% on InP considering misfit between the epitaxial layer and substrate.

We have demonstrated the formation of Ni(Ge 1− y Sn y ) layers on Ge 1− x Sn x layers by using solid-phase reaction for samples with Sn contents ranging from 2.0% to 6.5%. We have also investigated solid-phase reaction products in Ni/Ge 1− x Sn x /Ge samples after annealing and the crystalline properties of nickel–tin–germanide layer/Ge 1− x Sn x contact structures. After annealing at temperatures ranging from 350 to 550 °C, the formation of polycrystalline Ni(Ge 1− y Sn y ) layers has been observed on epitaxial Ge 1− x Sn x layers with Sn contents ranging from 2.0% to 6.5%. We also observed anisotropic crystal deformation of NiGe with the incorporation of Sn atoms into substitutional sites in NiGe. In the case of the Ni/Ge 1− x Sn x /Ge sample with a Sn content of 3.6%, the formation of an epitaxial Ni 2 (Ge 1− z Sn z ) layer on the Ge 1− x Sn x layer was found. The formation of β-Sn crystallites was observed after annealing at above 450 °C in samples with a high Sn content of 6.5%. This β-Sn formation is due to the precipitation of Sn atoms. In all samples annealed at 350 °C, the morphology of Ni–Ge–Sn layers is smooth and uniform. However, the surface roughness and interface roughness increase for an annealing temperature of 550 °C. In particular, in the sample with a Sn content of 6.5%, the temperature at which agglomeration noticeably occurs is as low as 450 °C.

We formed high-density Ge quantum dots (QDs) on an ultrathin SiO2 layer by controlling the early stages of low-pressure chemical vapor deposition (LPCVD) with a germane gas (GeH4) assisted by a remote plasma of pure H2. We then characterized the electronic charged states of the QDs by an AFM/Kelvin probe technique. The formation of single crystalline Ge-QDs with an areal dot density of ∼2.0 × 1011 cm−2 was confirmed after examining the surface morphology and lattice by atomic force microscopy and transmission electron microscopy, respectively. It has been suggested that an increase in the flux of deposition precursors due to efficient decomposition of GeH4 by a supply of hydrogen radicals and the dehydration reaction of surface OH bonds plays a role in nucleation of Ge-QDs on SiO2. Surface passivation with hydrogen may also promote the surface migration of deposition precursors during LPCVD. The surface potential of the dots changed in a stepwise manner with respect to the tip bias due to multistep electron injection into and extraction from the Ge-QDs.

Ultra thin Si cap growth by Reduced Pressure Chemical Vapor Deposition on relaxed Ge substrates is detailed in this paper for Ge pMOSFET (Metal Oxide Semiconductor Field Effect Transistors) passivation purposes. A cross calibration of different measurement techniques is first proposed to perfectly monitor Si monolayers thickness deposited on Ge substrates. Different characteristics, impacting Ge pMOSFETs device performances, are next detailed for various Si cap growth processes using different Si precursors: DiChloroSilane (DCS), silane and trisilane. The critical Si thickness of plastic relaxation has been determined at 12 monolayers. Presence of point defects has been identified for very low growth temperature as 350 °C. Ge–Si intermixing, caused by a Ge segregation mechanism, is strongly reduced by the use of trisilane as Si precursor at low temperatures.

We have investigated how to realize a strain-relaxed Ge 1− x Sn x layer with large in-plane lattice constant as a buffer layer for a tensile-strained Ge layer. This paper reports the dependence of strain relaxation behavior in Ge 1− x Sn x layers on the misfit strain at the interface between Ge 1− x Sn x layers and substrates. We examined control of the misfit strain by growth of Ge 1− x Sn x layers on bulk-Si and virtual Ge substrates. Large misfit strain between the Ge 1− x Sn x layer and the Si substrate leads to strain relaxation during growth and high degree of strain relaxation after annealing. However, it also leads to interfacial mixing and surface roughening with annealing. As a result, the Ge 1− x Sn x layer having a Sn content of 9.2% was achieved, and it has a potential to induce a tensile strain of 0.99% in Ge layer.

In this paper, we propose the fabrication of whole strained Ge complementary metal–oxide-semiconductor (CMOS) with Ge 1− x Sn x materials as stressors to outperform the state-of-the-art uniaxial compressive strained Si CMOS. Ge 1− x Sn x materials have larger lattice constant than that of Ge, which can apply the strain into Ge channel region. Firstly, we have demonstrated p-type doped Ge 1− x Sn x growth by using either B implantation or in situ Ga doping technique. In the B-implanted Ge 1− x Sn x formation case, fully strained B-doped Ge 1− x Sn x layers with no Sn precipitation can be obtained even after solid phase epitaxial regrowth (SPER). However, the serious dislocation generation in the layer was occurred during SPER. This is caused by the point defects introduced by B implantation. In order to avoid this crystal damage, we have also demonstrated in situ Ga-doped Ge 1− x Sn x growth. In this case, we can achieve fully strained Ga-doped Ge 1− x Sn x growth without Sn precipitation and any defect generation. Secondary, we have demonstrated the formation of Ni(Ge 1− y Sn y ) layers for metal/semiconductor contact and investigated the crystalline qualities. The formation of polycrystalline Ni(Ge 1− y Sn y ) layers on Ge 1− x Sn x layers with Sn contents ranging from 2.0% to 6.5% after annealing at from 350 °C to 550 °C can be achieved. Additionally, in the case of the Ni/Ge 1− x Sn x /Ge sample with a Sn content of 3.5%, an epitaxial Ni 2 (Ge 1− y Sn y ) layer on a Ge 1− x Sn x layer was formed. However, the surface roughness due to the agglomeration of Ni(Ge 1− x Sn x ) increases with increasing the Sn content and the annealing temperature. Therefore, a low thermal budget must be required for the formation of Ni(Ge 1− x Sn x ) with high Sn content.

In order to outperform current uniaxial compressively strained Silicon channel pMOSFET technology (with embedded SiGe source/drain), switching to strained Ge channel is mandatory. GeSn materials, having larger lattice parameter than Ge, are proposed in this article as embedded source/drain stressors for Ge channels. Our simulation results indicate that a minimum of 5% Sn is required in the GeSn source/drain to build a competitive strained Ge pMOSFETs with respect to strained Si channels. Therefore the compatibility of GeSn (with 2-8% Sn) materials with source/drain engineering processes (B implantation and activation and NiGeSn formation) has been studied. A low thermal budget has been determined for those processes on GeSn alloys: temperatures must be lower than 600^oC for B activation and lower than 450^oC for NiGeSn formation.

We have investigated the growth and crystalline structures of Ge1-xSnx buffer and tensile-strained Ge layers for future use in CMOS technology. We have demonstrated that strain relaxed Ge1-xSnx layers with an Sn content of 12.3% and 9.2% can be grown on Ge and Si substrates, respectively. We achieved a tensile-strain value of 0.71 % in Ge layers on a Ge0.932Sn0.068 buffer layer. We have also investigated the effects of Sn incorporation into Ge on the electrical properties of Ge1-xSnx heteroepitaxial layers.

We have investigated the three-dimensional configuration of lattice distortions, including lattice plane tilt and twist, in a high-Ge-content constant-composition Silsubg0.3l/subgGelsubg0.7l/subg (CC-SG)/compositionally graded SiGe strain-relaxed buffer (graded SRB)/Si(001) stacked structure. Position-dependent ω-2θ- mapping (or three-dimensional reciprocal space mapping) by synchrotron-based nanobeam X-ray diffraction revealed the in-plane distributions of both local tilt and twist within an area of 10×10 μm on the sample surface. Depth-resolved crystal information was extracted analytically on the basis of structural features in the graded SRB layer. As a result, a series of tomographic maps that show the three-dimensional distributions of tilt and twist around the CC-SG/graded SRB interface were obtained. Tomographic analysis indicates that the orientation of lattice planes in the graded SRB abruptly changes at a specific depth and at a specific interval. The misfit dislocation distribution observed using transmission electron microscopy is not homogeneous but concentrated at a specific depth, which accounts for the abrupt changes of lattice plane tilt and twist. Our tomographic results clearly verify the dislocation morphology in the SiGe stacked structure, which demonstrates that this analysis method can be a powerful tool for quantitative and non-destructive elucidation of a three-dimensional lattice structure with high spatial resolution.

We have investigated the dependence of strain relaxation behavior of Ge1-xSnx layers on the misfit strain at the interface between Ge1-xSnx layers and substrates. When the large misfit strain was induced, surface roughening and degradation of the crystallinity occurred during the Ge1-xSnx growth. We found that the universal dependency of the strain relaxation behavior, which is independent on kinds of substrates. As a result, the Ge1-xSnx layer having a Sn content of 12.3% was achieved, which has a potential to induce a tensile strain of 1.28% in a Ge layer.

In this paper, we propose the fabrication of whole strained Ge complementary metal-oxide-semiconductor (CMOS) with Ge1-xSnx materials as embedded stressors to outperform the state-of-the-art strained Si CMOS. Ge1-xSnx materials have larger lattice constant than that of Ge, which can apply the strain into Ge channel region. Compatibility of Ge1-xSnx (with 2-8% Sn) materials with source/drain engineering processes (B implantation and activation, in situ Ga doping, and Ni(Ge1-ySny) formation) is characterized. A low thermal budget has been determined for those processes on Ge1-xSnx alloys: temperatures must be lower than 600{degree sign}C for B activation and lower than 450{degree sign}C for Ni(Ge1-ySny) formation.

We have investigated the growth and characteristics of heteroepitaxial Ge1-xSnx layers on various substrates. The low temperature growth and the large misfit strain between Ge1-xSnx and Si leads to the high density of defects such as vacancy in Ge1-xSnx layers. They effectively enhance the propagation of misfit dislocations and the strain relaxation with suppressing the precipitation of Sn atoms from Ge1-xSnx layers. We succeeded in growing strain-relaxed Ge1-xSnx layers with a Sn content over 9% by controlling the dislocation structure on Si substrates. We also characterized the Hall mobility of Ge1-xSnx layers and found that the incorporation of Sn into Ge effectively reduced the concentration of holes related with vacancy defects, and improved on the hole mobility.

We have performed Ti valence state analysis of our four-terminal rutile TiO2− x single-crystal memristors using scanning transmission electron microscopy–electron energy loss spectroscopy (STEM–EELS). Analysis of Ti-L2,3 edge EELS spectra revealed that the electrocolored region formed by the application of voltage includes a valence state reflecting highly reduced TiO2− x due to the accumulation of oxygen vacancies. Such a valence state mainly exists within ~50 nm from the crystal surface and extends along specific crystal directions. These electrically reduced surface layers are considered to directly contribute to the resistive switching (RS) in the four-terminal device. The present results add new insights into the microscopic mechanisms of the RS phenomena and should contribute to further development and improvements of TiO2− x based memristive devices.

The mechanisms associated with electrical conduction through individual threading dislocations (TDs) in a Na-flux GaN crystal grown with a multipoint-seed-GaN technique were investigated by conductive atomic force microscopy (C-AFM). To focus on individual TDs, dislocation-related etch pits (DREPs) were formed on the Na-flux GaN surface by wet chemical etching, after which microscopic Pt electrodes were locally fabricated on the DREPs to form conformal contacts to the Na-flux GaN crystal, using electron beam assisted deposition. The C-AFM data clearly demonstrate that the leakage current flows through the individual TD sites. It is also evident that the leakage current and the electrical conduction mechanism vary significantly based on the area within the Na-flux GaN crystal where the TDs are formed. These regions include the c-growth sector (cGS) in which the GaN grows in the [0001] direction on top of the point-seed with a c-plane growth front, the facet-growth sector (FGS) in which the GaN grows with {...

To further boost the CMOS device performance, Ge has been successfully integrated on shallow trench isolated Si substrates for pMOSFET fabrication. However, the high threading dislocation densities (TDDs) in epitaxial Ge layers on Si cause mobility degradation and increase in junction leakage. In this work, we studied the fabrication of Ge virtual substrates with low TDDs by Ge selective growth and high temperature anneal followed by chemical mechanical polishing (CMP). With this approach, the TDDs in both submicron and wider trenches were simultaneously reduced below 1 × 107 cm− 2 for 300 nm thick Ge layers. The resulting surface root-mean-square (RMS) roughness is about 0.15 nm. This fabrication scheme provides high quality Ge virtual substrates for pMOSFET devices as well as for III–V selective epitaxial growth in nMOSFET areas. A confined dislocation network was observed at about 50 nm above the Ge/Si interface. This dislocation network was generated as a result of effective threading dislocation glide and annihilation. The separation between the confined threading dislocations was found in the order of 100 nm.

The core-shell nanostructure of epitaxial Fe3O4 nanocrystals over Ge nuclei showed a large Off/On resistance ratio (∼100), which was the largest value in Fe3O4 materials. The nanocrystals with an average diameter of ∼20 nm were grown epitaxially on Si substrates, whose areal density was high (∼1011 cm−2), and each nanocrystal was isolated from each other. The electrical measurement of the individual isolated nanocrystals by conductive-atomic force microscopy showed the bipolar-type resistive switching in local voltage-current curves, depending on the Fe-O composition. It was also revealed that activation sites for resistive switching were the Fe3O4/Ge interfaces, where electric-field-induced compositional variation caused large resistive changes. This demonstrated the possibility of developing resistance random access memory devices based on ubiquitous materials.

This work quantitatively assessed the three-dimensional distribution of crystal lattice distortions in an epitaxial AlN thick film grown on a trench-patterned template, using nanobeam X-ray diffraction. Position-dependent ω-2θ-φ mapping clearly demonstrated local tilting, spacing and twisting of lattice planes as well as fluctuations in these phenomena on a sub-micrometer scale comparable to the pitch of the trench-and-terrace patterning. Analysis of the crystal lattice distortion in the depth direction was performed using a newly developed method in which the X-ray nanobeam diffracted from the sample surface to specific depths can be selectively detected by employing a Pt wire profiler. This technique generated depth-resolved ω-2θ-φ maps confirming that fluctuations in lattice plane tilting and spacing greatly depend on the dislocation distribution and the history of the AlN epitaxial growth on the trench-patterned structure. It was also found that both fluctuations were reduced on approaching the AlN su...

We evaluated the combination of vapor phase doping and sub-melt laser anneal as a novel doping strategy for the fabrication of source and drain extension junctions in sub-32 nm CMOS technology, aiming at both planar and non-planar device applications. High quality ultra shallow junctions with abrupt profiles in Si substrates were demonstrated on 300 mm Si substrates. The excellent results obtained for the sheet resistance and the junction depth with boron allowed us to fulfill the requirements for the 32 nm as well as for the 22 nm technology nodes in the PMOS case by choosing appropriate laser anneal conditions. For instance, using 3 laser scans at 1300 °C, we measured an active dopant concentration of about 2.1 × 10 20 cm − 3 and a junction depth of 12 nm. With arsenic for NMOS, ultra shallow junctions were achieved as well. However, as also seen for other junction fabrication schemes, low dopant activation level and active dose (in the range of 1–4 × 10 13 cm − 2 ) were observed although dopant concentration versus depth profiles indicate that the dopant atoms were properly driven into the substrate during the anneal step. The electrical deactivation of a large part of the in-diffused dopants was responsible for the high sheet resistance values.

Low temperature epitaxial growth of group-IV alloys is a key process step to realize the advanced Si-based devices. In order to keep high growth rate below 600 °C, trisilane (Si 3 H 8 ) was used for their growth as an alternative Si precursor gas. Then, we compared the use of Si 3 H 8 versus SiH 4 for Si 1− x Ge x growth in H 2 and N 2 as carrier gas by low temperature chemical vapor deposition. By using Si 3 H 8 and controlling GeH 4 flow rate, Si 1− x Ge x growth with high growth rate and wide range of Ge concentration has been achieved compared to SiH 4 -based process. The growth rate and Ge concentration in Si 1− x Ge x with Si 3 H 8 grown at 600 °C ranged from 11 to 74 nm/min and from 0 to 40%, respectively. The obtained growth rates with Si 3 H 8 are between 1.5 and 6 times higher than for SiH 4 at a given growth condition. Si 3 H 8 -based in-situ B- and C-doped Si 1− x Ge x growth with high growth rate was also demonstrated.

Further improving CMOS performance beyond the 22 nm generation likely requires the use of high mobility channel materials. Complementary integration of different materials on Si can be realized with selective epitaxial growth. We present two fabrication schemes for Ge virtual substrates on standard Si STI wafers. This reduces the fabrication cost of these virtual substrates as it omits the complicated isolation scheme in blanket Ge. The low topography enables integration of ultra thin high-K gate dielectrics. The fabrication schemes are compatible with uni-axial stress techniques. Both modules include an anneal at 850 {degree sign}C to reduce the threading dislocation density down to 4x108 cm-2 and 1x107 cm-2, respectively. We are able to fabricate high quality Ge virtual substrates for pMOS devices as well as suitable starting surfaces for selective epitaxial III/V growth. The latter one will be illustrated by preliminary results of selective epitaxial InGaAs growth on virtual Ge substrates.

We have grown a tensile-strained Ge layer on a strain-relaxed compositionally step-graded Ge 1-x Sn x buffer layer using virtual Ge substrates. The degree of strain relaxation along [110] direction of the top Ge 0.945 Sn 0.055 buffer layer is achieved up to 85% and the resultant (110) lattice spacing of the Ge 0.945 Sn 0.055 buffer layer is estimated to be 0.4028 nm. A pseudomorphic Ge layer is successfully grown on the Ge 0.945 Sn 0.055 buffer layer, yielding a tensile strain of 0.68% with respect to the (110) lattice spacing of non-strained Ge. This value exceeds those obtained by other methods based on the thermal expansion coefficient difference and strain-relaxed Ge 1-x Sn x buffer layer directly grown on Si(001) substrates.

Atomic layer doping of phosphorus (P) and arsenic (As) into Si was performed using the vapor phase doping (VPD) technique. For increasing deposition time and precursor gas flow rate, the P and As doses tend to saturate at about 0.8 and 1.0 monolayer of Si, respectively. Therefore, these processes are self-limited in both cases. When a Si cap layer is grown on the P-covered Si(001), high P concentration of 3.7 × 1020 cm-3 at the heterointerface in the Si-cap/P/Si-substrate layer stacks is achieved. Due to As desorption and segregation toward the Si surface during the temperature ramp up and during the Si-cap growth, the As concentration at the heterointerface in the Si-cap/As/Si-substrate layer stacks was lower compared to the P case. These results allowed us to evaluate the feasibility of the VPD process to fabricate precisely controlled doping profiles.

DiMethylAminoGermaniumTriChloride (DiMAGeCl) is evaluated as a C-dopant source for selective SiGe and Ge epitaxy using Chemical Vapor Deposition. We determine the C-level as a function of temperature and pressure and we examine the applicability of DiMAGeCl for the growth of high quality Ge on Si.

New structures and materials alternative to conventional bulk-Si(001) substrates are now under consideration for their application to CMOS channel layers on a Si platform. However, mismatch of lattice parameter between the alternative channel material and the Si substrate inevitably causes defect introduction which is one of crucial issues when implementing the formation of channels on Si. In this work, we perform interface and defect engineering for group IV semiconductor materials; Si with hybrid crystal orientation, Ge, and Sn. Engineered channel crystals formed with the wafer direct bonding and heteroepitaxy technologies are characterized in terms of crystalline quality and strain.

We have investigated the initial growth of Sn and Ge1−xSnx layers on Ge(0 0 1) surface by using scanning tunneling microscopy. After the growth of a 0.035 ML-thick Sn layer at room temperature, Sn clusters lining vertically to a dimer row was observed. In the case of the 0.035–0.018 ML-thick Sn growth at 250 °C, the characteristic surface reconstruction with the step-edge undulation like a comb was observed. In the growth of a Ge0.994Sn0.006 layer at 250 °C, the multilayer polynuclear growth with a lot of two-dimensional small domain was observed. These surface reconstructions should be accounted for by the large compressive stress induced in the surface layer due to the incorporation of Sn atoms.

Quadrupole deformation parameters, | β 2 , ( p , p ′ ) | , have been deduced for 36,38,40Si from measured inelastic proton-scattering cross sections. Due to the strong Z = 14 subshell gap, low-lying quadrupole collectivity in these nuclei is attributed to the excitation of valence neutrons. Enhanced collectivity at N = 26 indicates a reduced N = 28 shell gap at large neutron excess in this chain of isotopes. Data are compared to large-scale shell-model calculations and prior Coulomb excitation measurements on 36,38Si.

Phonon transport in Si films was controlled using epitaxially-grown ultrasmall Ge nanodots (NDs) with ultrahigh density for the purpose of developing Si-based thermoelectric materials. The Si/Ge ND stacked structures, which were formed by the ultrathin SiO2 film technique, exhibited lower thermal conductivities than those of the conventional nanostructured SiGe bulk alloys, despite the stacked structures having a smaller Ge fraction. This came from the large thermal resistance caused by phonon scattering at the Si/Ge ND interfaces. The phonon scattering can be controlled by the Ge ND structure, which was independent of Si layer structure for carrier transport. These results demonstrate the effectiveness of ultrasmall epitaxial Ge NDs as phonon scattering sources, opening up a route for the realisation of Si-based thermoelectric materials.

We have performed growth and structure evaluation of strain-relaxed Ge1−xSnx buffer layers grown on Si(0 0 1), virtual Ge(0 0 1) and bulk Ge(0 0 1) substrates. In the case of Si(0 0 1), amorphous Ge1−xSnx phases are partially formed as well as many threading dislocations in Ge0.98Sn0.02 layers. Employing virtual Ge substrates to reduce the lattice mismatch at the interface leads to epitaxial Ge0.978Sn0.022 layers with a flat surface. Most of threading dislocations in the Ge0.978Sn0.022 layer comes from pre-existing ones in the virtual Ge substrate and propagates laterally, leaving misfit segments at the Ge0.978Sn0.022/virtual Ge interface, after post-deposition annealing (PDA). This simultaneously results in the reduction of threading dislocation density and the promotion of strain relaxation. In the case of bulk Ge(0 0 1), although low threading dislocation density can be achieved, less than 106 cm−2, the film exhibits surface undulation and a lesser degree of strain relaxation even after PDA.

The initial growth process of Si1−x−yGexCy epitaxial thin films on Si(1 0 0) surfaces has been investigated by scanning tunneling microscopy. We attempted sequential alternate deposition of one-monolayer(ML)-thick Si0.793Ge0.207 and 0.048-ML-thick C layer grown at 600 °C in order to control C adsorption sites for the formation of epitaxial Si0.769Ge0.183C0.048 layer. In the conventional co-deposition case of Si, Ge, and C at 600 °C, it was observed that the local phase separation to Si–Ge and Si–C occurred on the surface due to the C condensation. Three-dimensional (3D) islands were formed as a result of the disturbance of conformal growth induced by defects formed on the surface. On the other hand, in the alternate deposition case, it was observed that the homogeneous distribution of Si, Ge, and C atoms led to suppression of the local phase separation, the 3D island growth, and the defect formation. As a result, the critical thickness of the two-dimensional (2D) Si1−x−yGexCy growth could be increased.

The initial growth of Si 1− x − y Ge x C y film with Si 1− x Ge x interlayer on Si(1 0 0) surface is investigated by scanning tunneling microscopy and reflection high energy electron diffraction. The increase in the Ge fraction of Si 1− x Ge x interlayers raises the critical thickness of the transition from two-dimensional (2D) to three-dimensional (3D) growth of Si 1− x − y Ge x C y layers, and is effective to suppress the surface-roughening of Si 1− x − y Ge x C y layers. The atomic-scale valley structure separating 2D-islands of the Si 1− x − y Ge x C y layers are observed on the surface, which is deduced to be the structure for the compressive-strain relaxation of Si 1− x − y Ge x C y layers on the Si substrate as well as missing dimmer rows.

An exfoliative toxin produced by Staphylococcus aureus is the causative agent of staphylococcal scalded-skin syndrome (SSSS) in young children. Recently, we reported that only few isolates of S. aureus from bovine mastitis contained the eta gene encoding exfoliative toxin A (ETA) and produced ETA in vitro. In this study, we isolated temperate phages from two ETA-positive bovine isolates of S. aureus by treatment with mitomycin C. Polymerase chain reaction (PCR) assay of the phage genomes suggested that the temperate phages carried the structural gene for ETA. Moreover, the nucleotide sequence analysis of the PCR products revealed that the eta gene was located very close to an amidase gene on the phage genomes. The nucleotide sequence for the amidase gene of the bovine phage (bovine phi ETA) differed at nine positions from that of the amidase gene of phi ETA from a human isolate reported by Yamaguchi et al. [Mol. Microbiol. 38 (2000) 694], suggesting that eta-converting phages are heterogeneous. Bovine phi ETA had a head with a hexagonal outline and a non-contractile and flexible tail. Bovine phi ETA was able to lysogenize ETA-negative bovine isolates of S. aureus, and the lysogenized S. aureus isolates had the ability to produce ETA. These results suggest the possibility of horizontal transmission of the eta gene by temperate bacteriophages among bovine isolates of S. aureus.