Search

An investigation was carried out into the instability of the crystal/melt interface in Si-rich SiGe, and the effects of the Ge concentration and growth velocity on the periodicity of zigzag facets at the interface were determined. It was found that the periodicity at the onset of instability became shorter with the increasing growth velocity and Ge concentration. [ABSTRACT FROM AUTHOR]

Depending on the detailed geometry, gate voltage, and circuitry, nanoscale Si/SiGe cross junctions at low temperatures exhibit full-wave rectification arising from different mechanisms like change in the number of current-carrying modes, stationary ballistic charging of a current-free voltage lead, and hot-electron thermopower. We study the rectifier structures on high-mobility Si/SiGe heterostructures consisting of a straight voltage stem and oblique current-injecting leads. Local gate electrodes are used to control the electron density in the voltage or current channel. Compared to three-terminal Y-branch junctions, the four-terminal cross junction eliminates the mode effect. A gradual increase of output voltage as gate-voltage is reduced until threshold voltage is identified as contribution of hot-electron thermopower. Heating the initially cold reservoir from a second orthogonal cross junction eliminates the electron temperature gradient and suppresses the thermopower. Even if the operation as six-terminal device re-induces a mode-controlled contribution, we demonstrate that it is negligible. As expected, the ballistic signal can be reliably separated from other mechanisms by measurements under positive gate voltage. The ballistic voltage can be described by a parabolic function of the injected current and is proportional to the cosine of the injection angle. [ABSTRACT FROM AUTHOR]

The interface trap density (Dit) of SiGe metal-oxide-semiconductor (MOS) interfaces is analyzed by the conductance method to evaluate the effect of electron cyclotron resonance plasma postnitridation on SiGe interfaces with various Ge compositions. We find that it is important to evaluate Dit of a high-Ge-content SiGe MOS interface by the conductance method to eliminate the effect of the large series resistance and capacitance due to the SiGe/Si hetero-interface. In conjunction with the high-temperature measurement in the conductance method, an equivalent circuit corresponding to the SiGe/Si hetero-interface enables us to eliminate the effect of the series resistance and capacitance of the hetero-interface. Thus, we successfully evaluated Dit at SiGe MOS interfaces with a Ge composition of up to 0.49 and the impact of plasma post-nitridation on the high-Ge-content SiGe interfaces. Although Dit increases with the Ge composition, plasma post-nitridation is effective even for a high-Ge-content SiGe interface. Dit of the Al2O3/Si0.51Ge0.49 interface was reduced from 7.8×1012 cm2 eV1 to 2.4×1012 cm2 eV1 by plasma post-nitridation. Thus, we reveal that plasma post-nitridation is useful to achieve superior Al2O3/SiGe MOS interfaces regardless of the Ge composition. [ABSTRACT FROM AUTHOR]

The conduction and valence band offsets between a strained silicon-germanium layer and a silicongermanium substrate are reported for arbitrary substrate and channel crystal orientations. The offsets are calculated both for the case of biaxial stress, corresponding approximately to the stress state of a thin strained channel in a planar field-effect transistor (FET), and for uniaxial stress, which is the approximate stress state for strained channels in a FinFET configuration. Significant orientation dependence is found for the conduction band offset, overall leading to the strongest electron quantum confinement in biaxial-tensile stressed channels on {100}-oriented substrates, and uniaxialtensile stressed channels in the ⟨100⟩ and ⟨101⟩ directions. For biaxially stressed layers on {111} substrates, the conduction band offset is significantly smaller than for {100} or {110} directions. For the valence band offset, the dependence on crystal orientation is found to be small. [ABSTRACT FROM AUTHOR]

Silicon dioxide is used to electrically isolate CMOS devices such as fin field effect transistors by filling gaps between the devices (also known as shallow trench isolation). The gap fill oxide typically requires a high temperature anneal in excess of 1000 °C to achieve adequate electrical properties and oxide densification to make the oxide compatible with subsequent fabrication steps such as fin reveal etch. However, the transition from Si-based devices to high mobility channel materials such as SiGe and III-V semiconductors imposes more severe thermal limitations on the processes used for device fabrication, including gap fill oxide annealing. This study provides a framework to quantify and model the effect of anneal temperature and time on the densification of a flowable silicon dioxide as measured by wet etch rate. The experimental wet etch rates allowed the determination of the activation energy and anneal time dependence for oxide densification. Dopant and self-diffusion can degrade the channel material above a critical temperature. We present a model of self-diffusion of Ge and Si in SiGe materials. Together these data allowed us to map the thermal process space for acceptable oxide wet etch rate and self-diffusion. The methodology is also applicable to III-V devices, which require even lower thermal budget. The results highlight the need for nonthermal oxide densification methods such as ultraviolet (UV) and plasma treatments. We demonstrate that several plasma treatments, in place of high temperature annealing, improved the properties of flowable oxide. In addition, UV curing prior to thermal annealing enables acceptable densification with dramatically reduced anneal temperature. [ABSTRACT FROM AUTHOR]

In addition to the massive application in the electronics industry for decades, silicon has been considered as one of the best candidates for the photonics industry. However, a high-efficiency, broadband light source is still a challenge. In this paper, we theoretically propose a Si/Ge based platform consisting of plasmonic nanocavity array to realize the tunable, broadband, and high-efficiency Si/Ge hot luminescence from infrared to visible region with large luminescence enhancement (about 103). It is demonstrated that the large luminescence enhancement is due to the resonance between the intrinsic hot luminescence and the plasmonic nanocavity modes with ultra-small effective mode volumes. And, the size and Ge composition of Si1-xGex nanowire can be tuned to realize the tunable and broadband luminescence. This study gives rise to many applications in silicon photonics, like ultrafast optical communications, sensors, and on-chip spectral measurements. [ABSTRACT FROM AUTHOR]

The electrochemical capacitance voltage technique has been used on highly boron doped SiGe and Si layers. Although the boron concentration is constant over the space charge depth, the 1/C2 versus voltage curves are not linear. They indeed present a negative curvature. This can be explained by the existence of deep acceptors which ionise under a high electric field (large inverse voltage) and not at a low inverse voltage. The measured doping concentration in the electrochemical capacitance voltage increases strongly as the inverse voltage increases. Thanks to a comparison with the boron concentration measured by secondary ions mass spectrometry, we show that the relevant doping concentrations in device layers are obtained for small inverse voltage in agreement with the existence of deep acceptors. At the large inverse voltage, the measured doping can be more than twice larger than the boron concentration measured with a secondary ion mass spectroscopy. [ABSTRACT FROM AUTHOR]

We report the formation of very uniform and smooth Ni(Pt)Si on epitaxially grown SiGe using Si gas cluster ion beam treatment after metal-rich silicide formation. The gas cluster ion implantation process was optimized to infuse Si into the metal-rich silicide layer and lowered the NiSi nucleation temperature significantly according to in situ X-ray diffraction measurements. This novel method which leads to more uniform films can also be used to control silicide depth in ultrashallow junctions, especially for high Ge containing devices, where silicidation is problematic as it leads to much rougher interfaces. [ABSTRACT FROM AUTHOR]

The cross-plane thermal conductivity κ of multilayers of SiGe nanodots separated either by Si or SiGe can be decreased by reducing the period length or by increasing the nanodot density. It is, however, not clear how far κ can be reduced by using these strategies. In addition, the role of SiGe nanodots on the reduction of j is still not fully understood. In this work, we addressed these issues by studying experimentally the cross-plane j of Ge/Si superlattices with period lengths down to 1.5 nm. Although κ tends to preserve the decreasing trend with reducing the period length, for periods shorter than 2 nm we observed a drastic drop of the average thermal resistance per period. This finding indicates a weakening of the effect of the interfaces on phonon scattering and implies a lower limit for κ. To assess the role played by the nanodots in the reduction of j we studied Ge/Si superlattices with nanodot densities varying from 0 to ~8x1010 cm-2 and a fixed Si spacer thickness of 2.7 nm. The experimental results suggest that SiGe nanodots with "pyramid"-shape have an effect comparable to nominally planar wetting layers on the cross-plane thermal transport. Finally, the comparison of superlattices with nanodots separated by Si1-xGex (with x from 0 to 0.2) shows that spacer alloying is beneficial in reducing the κ by ~20%. The results presented in this work are expected to be relevant to micro/nanoscale energy conversion which requires minimizing the thermal conductivity of superlattice-based thin film thermoelectrics. [ABSTRACT FROM AUTHOR]

Using first principles calculations, we have studied the dielectric properties of crystalline α- and β-phase silicon germanium nitrides and silicon carbon nitrides, A3-ξBξN4 (A = Si, B = Ge or C, ξ=0,1,2,3). In silicon germanium nitrides, both the high-frequency and static dielectric constants increase monotonically with increasing germanium concentration, providing a straightforward way to tune the dielectric constant of these materials. In the case of silicon carbon nitrides, the high-frequency dielectric constant increases monotonically with increasing carbon concentration, but a more complex trend is observed for the static dielectric constant, which can be understood in terms of competition between changes in the unit-cell volume and the average oscillator strength. The computed static dielectric constants of C3N4, Si3N4, and Ge3N4 are 7.13, 7.69, and 9.74, respectively. [ABSTRACT FROM AUTHOR]

The phonon transport properties and the lattice thermal conductivity of silicon germanium alloy crystals have been investigated based on phonon gas model by using classical molecular dynamics simulations. The attenuation of the mode-dependent phonon relaxation time due to alloying and its dependence on the alloy fraction were quantified by projecting the molecular dynamics phase space trajectory onto the normal mode of the alloyed crystal. By empirically approximating the group velocities from the extended dispersion relations, the lattice thermal conductivity was calculated based on the phonon gas model under relaxation time approximation. The obtained reduction in the lattice thermal conductivity caused by alloying agrees well with that of the experiment and direct non-equilibrium molecular dynamics calculations. The phonon-mean-free-path dependent contribution to thermal conductivity suggests that the effect of nanostructuring can have non-monotonic dependence on the alloy fraction. [ABSTRACT FROM AUTHOR]

In this Letter, high-performance vertical NiO/β-Ga2O3 p–n heterojunction diodes without any electric field managements were reported. The devices show a low leakage current density and a high rectification ratio over 1010 (at ±3 V) even operated at temperature of 400 K, indicating their excellent thermal stability and operation capability at high temperature. Given a type-II band alignment of NiO/β-Ga2O3, carrier transport is dominated by the interface recombination at forward bias, while the defect-mediated variable range hopping conduction is identified upon strong reverse electric field. By using the double-layer design of NiO with a reduced hole concentration of 5.1 × 1017 cm−3, the diode demonstrates an improved breakdown voltage (Vb) of 1.86 kV and a specific on-resistance (Ron,sp) of 10.6 mΩ cm2, whose power figure of merit (Vb2/Ron,sp) has reached 0.33 GW/cm2. The high breakdown voltage and low leakage current are outperforming other reported Ga2O3 based p–n heterojunctions and Schottky barrier diodes without field plate and edge termination structures. TCAD simulation indicates that the improved Vb is mainly attributed to the suppression of electric field crowding due to the decreased hole concentration in NiO. Such bipolar heterojunction is expected to be an alternative to increase the breakdown characteristics of β-Ga2O3 power devices. [ABSTRACT FROM AUTHOR]

GeTe is an important narrow bandgap semiconductor material and has found application in the fields of phase change storage as well as spintronics devices. However, it has not been studied for application in the field of infrared photovoltaic detectors working at room temperature. Herein, GeTe nanofilms were grown by magnetron sputtering technique and characterized to investigate its physical, electrical, and optical properties. A high-performance infrared photovoltaic detector based on GeTe/Si heterojunction with the detectivity of 8 × 1011 Jones at 850 nm light irradiation at room temperature was demonstrated. [ABSTRACT FROM AUTHOR]

We study and fabricate graphene nanowalls/silicon hybrid heterojunction photoconductive detector to provide process technology of the device and theoretical foundation for the purpose of preparation of high-performance photodetectors. The graphene nanowalls (GNWs) film is patterned by double-layered photoresist-based photolithography and reactive ion etching (RIE) process to achieve high quality GNWs channel and fabricate three different GNWs/Si heterojunction photoconductive detectors with n-doped, intrinsic and p-doped silicon substrates (n-Si, i-Si, p-Si), respectively. The GNWs film not only acts as a photoconductive channel for carrier transport, but also constructs a Schottky heterojunction with the silicon to participate in the separation and transport of photogenerated carriers. Since the injection of holes needs to pass through the Schottky junction region, the height of the Schottky barrier determines the injection ability of photogenerated carriers, which directly affects the photoconductive gain of the GNWs and silicon. In addition, under low bias V DS , the GNWs/n-Si photoresponse current is maximum and the GNWs/p-Si photoresponse current is minimum. The photoresponse is attributed to the barrier heights of the GNWs/n-Si, GNWs/i-Si, and GNWs/p-Si with values of 0.73 eV, 0.69 eV, and 0.63 eV, respectively. The higher the barrier, the more the number of photogenerated carriers injected into the GNWs will be, and the photoresponse current is large as well. Image 1022774 [ABSTRACT FROM AUTHOR]

This article presents a wideband self-interference (SI) canceling full-duplex (FD) receiver. In-band linearity requirement for an FD receiver is studied. It is shown that an FD receiver requires a minimum IB-IIP3 which if not provided, results in sensitivity degradation. To provide the required out-of-band linearity, an eight-phase passive mixer-first architecture is chosen for the receiver. In order to achieve SI cancellation, quadrature components from TX replica are created, their magnitudes are scaled, and the approximated SI is injected to the receiver. The cancellation occurs after downconversion, in an RF to baseband (BB) cancellation domain. As a proof of concept, a prototype is fabricated and measured in a 65-nm CMOS process. More than 35-dB cancellation is measured for 10-MHz bandwidth (BW) 64-QAM modulated signals in a single RF downconverted domain. The noise figure (NF) in half-duplex (HD) and FD mode is 3.3 and 5.3 dB, respectively, with only 2-dB degradation for switching from HD to FD. The receiver has adjustable 30-to-50-dB conversion gain, consumes 20–58-mW power, and achieves IB-IIP3 of +6 dBm. The cancellation path achieves more than 35-dBm IIP3. [ABSTRACT FROM AUTHOR]

In this study, an ultra-compact meandered grounding resonator is proposed to design two millimetre wave bandpass filters (BPFs) in a standard 0.13-µm silicon-germanium (Bi)-complementary metal oxide semiconductor (CMOS) technology. The fundamental second-order prototype, namely BPF-I, consists of a pair of proposed resonators and a pair of grounded metalinsulator- metal (MIM) capacitors. To better understand the principle of the second-order BPF-I, an equivalent LC-circuit model and theoretical analysis method are presented in this study. Based on BPF-I, the second-order BPF-II is proposed by adding the additional two pairs of MIM capacitors to improve the frequency selectivity, by means of introducing a transmission zero at lower stopband. Finally, both of the two second-order BPFs are fabricated. The measured results show a good agreement with the full-wave simulation results. The insertion loss of the first BPF-I is 1.79 dB at the centre frequency of 46.6 GHz, and the fractional bandwidth is up to 96.5%. The second BPF-II has a centre frequency at 46.8 GHz with a fractional bandwidth of 94.1%. The minimum insertion loss is 2.08 dB and the lower stopband attenuation is up to 42.7 dB. Moreover, the die sizes of the two compact BPFs, excluding the test pads, are only 0.0197 mm2 (0.104 × 0.190 mm2). [ABSTRACT FROM AUTHOR]

Indium phosphide (InP)‐based transistors play an important role in high‐speed circuit and high‐frequency analog circuit applications. Over the past few decades, terahertz heterojunction bipolar transistor (HBT) is increasingly developed. As a result, many reports of HBTs operating at terahertz region have flourished. Since the high‐frequency circuit design faces the challenge from the lack of precise transistor models, this paper reviews the development of high‐frequency modeling technologies of InP HBT at terahertz region. Processes in the development of small‐signal models at terahertz frequencies, precise parasitic parameters extraction method, improvements in measurement, and the de‐embedding technologies open up more opportunities for precise representation of InP HBTs. Finally, some excellent terahertz circuits based on InP HBT are reviewed. [ABSTRACT FROM AUTHOR]

Heterojunction PN diode and inverter circuits are fabricated and presented, combining two‐dimensional WSe2 nanoflake and amorphous InGaZnO (a‐IGZO) thin film on a glass substrate. A heterojunction p‐WSe2/n‐IGZO diode exhibits rectifying characteristics and effectively responds to red light (λ = 620 nm) under a reverse bias. The combination of a heterojunction PN diode and IGZO field effect transistor (FET) leads to a diode‐load inverter showing a peak voltage gain of about 12 at a supply voltage of 5 V. The same integration from the PN diode and n‐FET displays the capability of visible light detection when a reverse‐bias voltage is applied to the PN diode. Furthermore, after oxygen plasma treatment on the PN diode, it shows dramatically enhanced on/off rectification ratio of ≈5 × 105 due to the hole doping effect on the WSe2 nanoflake. Such an improved PN diode leads to an alternating current rectifier circuit as integrated with IGZO FET. [ABSTRACT FROM AUTHOR]

With the shortage of energy and the development of technology, self-powered devices are promptly needed and aroused much concern in the world. However, restricted to the working principle, external biases are usually needed to get high longitudinal photocurrent responses for the current prototype devices. Here, the lateral photovoltaic effect (LPE) is first introduced to study the lateral photocurrent (LPC) responses in the Cu(In,Ga)Se2 (CIGS) heterostructure. It is found that the CIGS heterojunction can be developed to both an LPC-based self-powered position-sensitive detector (PSD) and photodetector. This PSD shows ultralarge LPC responses in a wide spectral range with a position sensitivity of up to 4.66 mA/mm (at 532 nm) and can work in different contact distances as large as 10.2 mm with excellent linearities. Moreover, the LPC responses can be considerably improved by modulating the thickness of the indium tin oxides (ITOs) layer, which can be mainly attributed to the ITO thickness-dependent external quantum efficiency of the CIGS devices. For the photodetector, the responsivity reaches up to 0.197 A/W but exhibits a nearly reverse laser power- and contact distance-dependent changing tendency with the position sensitivity due to their different definitions. [ABSTRACT FROM AUTHOR]

We propose and demonstrate a new single heterojunction structure for dual-band detection based on type-II InAs/GaSb superlattices grown by metal-organic chemical vapor deposition. The structure simply consists of a p-type mid-wavelength contact layer, an n-type mid-wavelength absorber and an n-type long-wavelength absorber. At a small reverse bias, the presence of a potential barrier in the valence band between the two adjacent absorbers allows the mid-wavelength channel to work only; at a higher bias where the potential barrier no longer exists, photo-generated holes in the long-wavelength absorber are able to transport through the mid-wavelength absorber and reach the p-contact, making both channels to work. At −0.1 V and 77 K, the mid-wavelength channel exhibited a 50% cut-off wavelength of 3.5 $\mu \text{m}$ , a dark current density of $2.4\times 10^{{-9}}$ A/cm2, and a peak specific detectivity of $1.4\times 10^{{13}}$ cm $\cdot $ Hz1/2/W; while at −0.3 V the long-wavelength channel exhibited a 50% cut-off wavelength of 8.0 $\mu \text{m}$ , a dark current density of $5.1\times 10^{-7}$ A/cm2, and a peak specific detectivity of $3.6\times 10^{12}$ cm $\cdot $ Hz1/2/W. [ABSTRACT FROM AUTHOR]

As a classical clustering model, Gaussian Mixture Model (GMM) can be the footstone of dominant machine learning methods like transfer learning. Evolving GMM is an approximation to the classical GMM under time-critical or memory-critical application scenarios. Such applications often have constraints on time-to-answer or high data volume, and raise high computation demand. A prominent approach to address the demand is GPGPU-powered computing. However, the existing evolving GMM algorithms are confronted with a dilemma between clustering accuracy and parallelism. Point-wise algorithms achieve high accuracy but exhibit limited parallelism due to point-evolutionary pattern. Block-wise algorithms tend to exhibit higher parallelism. Whereas, it is challenging to achieve high accuracy under a block-evolutionary pattern due to the fact that it is difficult to track evolving process of the mixture model in fine granularity. Consequently, the existing block-wise algorithm suffers from significant accuracy degradation, compared to its batch-mode counterpart: the standard EM algorithm. To cope with this dilemma, we focus on the accuracy issue and develop an improved block-evolutionary GMM algorithm for GPGPU-powered computing systems. Our algorithm leverages evolving history of the model to estimate the latest model order in each incremental clustering step. With this model order as a constraint, we can perform similarity test in an elastic manner. Finally, we analyze the evolving history of both mixture components and the data points, and propose our method to merge similar components. Experiments on real images show that our algorithm significantly improves accuracy of the original general purpose bock-wise algorithm. The accuracy of our algorithm is at least comparable to that of the standard EM algorithm and even outperforms the latter under certain scenarios. [ABSTRACT FROM AUTHOR]

Background: An efficient biodegradation-strengthening approach was developed to improve penicillin G degradation from industrial bacterial residue in an expanded bed adsorption bioreactor (EBAB) is reported in this paper. Results: Paracoccus sp. strain KDSPL-02 was isolated based on its ability to use penicillin G as the sole carbon and nitrogen source. Strain identification was based on analyses of morphology, physio-biochemical characteristics, and 16S rDNA sequences. The effects of temperature, pH, PVA-sodium alginate concentration, calcium chloride concentration and initial penicillin G concentration were investigated. Repeated operations of immobilized cells with EBAB, At initial penicillin concentrations below 2.0 g L− 1, the continuous mode could reach more than 20 times, and the degradation rate reached 100%. Conclusions: The present study suggests that the EBAB system can be utilized for the simple and economical biodegradation of penicillin G from industrial bacterial residue. [ABSTRACT FROM AUTHOR]

Optical interconnects are promising alternatives to copper-based wirings in on-chip communications. Recent advances in integrated group-IV nanophotonics should address a range of challenges related with speed, energy consumption, and cost. Monolithically integrated germanium pin photodetectors on silicon-on-insulator (SOI) waveguides are indispensable devices in this buoyant research field. Here, we comprehensively investigate the opto-electrical properties of hetero-structured pin photodetectors. All photodetectors were fabricated on top of 200-mm SOI substrates using industrial-scale semiconductor manufacturing processes. Under a low-bias voltage supply of 1 V, pin photodetectors exhibit dark-currents from 5 nA to 100 nA, dark current densities from 0.404 A/cm2 to 0.808 A/cm2, responsivities in a range of 0.17 A/W to 1.16 A/W, and cut-off frequencies from 7 GHz to 35 GHz, respectively. Such achievements make them promising for use in power-efficient optical links operating at 40 Gbps, with a device energy dissipation of only few fJ per bit. [ABSTRACT FROM AUTHOR]

In order to improve the heat dissipation capability of high-power press-pack insulated gate bipolar transistor (PP-IGBT), the nanosilver paste was utilized to package a single 3.3-kV/50-A PP-IGBT chip; we called it sintered pack IGBT (SP-IGBT) in this letter and revealed the reliability of such a device based on a power cycling test (PCT). The test results show that the ON-state voltage (Vce) of SP-IGBT sharply increased to 9.5 V after 5500 cycles, and then the device emerged with a special short-circuit failure. The huge heat generated at the moment of device failure caused the sintered nanosilver layer to melt and then squeezed it out by the external pressure, and the melt silver paste directly connected the collector molybdenum layer to the emitter of SP-IGBT die, which is different from the short-circuit failure of fully PP-IGBT due to being electrically broken down. The failed device is analyzed by scanning electron microscope (SEM) and energy dispersive spectrometer (EDS), the failure mechanism is explained by a finite-element analysis, and such work is helpful for the package crafts improvement on the press-pack power modules. [ABSTRACT FROM AUTHOR]

The possibility of generating ultrabroadband chaotic oscillations within a frequency range up to 60 GHz with a bipolar SiGe heterojunction transistor is demonstrated. The uppermost frequency of this range is determined by the cutoff frequency of the active generator element. Such a possibility appears after the generator structure is complemented with an additional nonlinear circuit, in which chaotic oscillations can be developed up to the aforementioned frequency. Some results of the experimental study of one generator configuration based on lumped elements are presented. [ABSTRACT FROM AUTHOR]

In this paper, we propose and study a model of a source of ultra-wideband chaotic oscillations of the 30–50 GHz range in an IC version based on a 130-nm silicon-germanium technology. [ABSTRACT FROM AUTHOR]

Voids were formed in silicon (Si) and silicon germanium/silicon (Si1-xGex/Si) samples containing 5% or 9% Ge (at. %) by 30 keV, 5 × 1016 cm-2 helium (He+) implantation followed by annealing in nitrogen (N2) or dry oxygen (O2) atmospheres in the temperature range 960-1110 °C. Si1-xGex thicknesses were 60 nm and 20 nm for 5% and 9% Ge, respectively. He+ implantation energy was set such that in Si1-xGex/Si samples voids were formed inside the Si substrate. An increase in annealing temperature resulted in an increase in the average void diameter and decrease in the average void density. Due to the presence of implantation damage and the relatively high temperature anneals, Ge diffusion occurs, which results in a stress gradient in the sample that interacts with the void layer. The presence of Ge also results in weaker Si-Ge bonds (compared to Si-Si bonds). This leads to an increase in the rate of cavity migration providing a likely explanation for the increase in the average void diameter and decrease in the average void density in Si1-xGex/Si samples when compared to the similarly prepared Si samples. No impact on the void evolution process was observed as a result of changing the anneal atmosphere from N2 to dry O2. [ABSTRACT FROM AUTHOR]

This paper reports wafer-level backside process technology, established with the intent to ensure stable operation of InP ICs in the submillimeter wavelength band, which generally suffer from ground bounce and substrate resonance. Our process consists of thinning a 3-in InP wafer, forming dense vias with interval cooling steps, backside metallization with single-level wiring and crack-free dicing. We investigate the effects of the backside process on InP-based heterojunction bipolar transistors and high electron mobility transistors. The results show that the backside process contributes to stable operation up to the 300-GHz range without any degradation of transistor characteristics. [ABSTRACT FROM AUTHOR]

Recent days, for low power applications, germanium (Ge) is considered to be a good alternative of Silicon (Si) as channel material for TFETs to boost the on current. This study reports on the reliability of Ge-pTFET in presence of temperature variability. The reliability is studied through comparative analysis of Analog and Small-signal parameters. The variation in lattice temperature is a crucial issue for reliability of any device since it modulates the band gap narrowing at the tunneling junctions and hence tunneling characteristics of the device. In this work, the impact of temperature variation is systematically analyzed in Ge-pTFET in terms of Non-Quasi-static small-signal-model parameters along with Analog Figure-of-Merits. Also, linearity performance is investigated by means of IIP3 and 1-dB compression point for the variation of temperature, ranges from 200 K to 400 K. Finally, the impact of temperature variation is analyzed in mixed mode circuit simulations for the applications of cascode amplifier circuit and common source amplifier circuit. [ABSTRACT FROM AUTHOR]

In this paper, we will introduce a new designed direct conversion terahertz detector. Characteristics of this new detector have been compared with a prefabricated design in order to obtain better performance of our new proposed design. We have introduced an exponentially graded base SiGe-HBT instead of linearly graded ones, and have used a single transistor with two base contacts, which is equivalent to two transistors in common emitter configuration. New proposed detector has been analyzed by both compact circuit and two dimensional carrier transport models. Responsivity and minimum noise equivalent power of new detector are about 4.9 A/W and 6.5 pW/Hz1/2 at 700 GHz respectively, while these characteristics for the prefabricated detector, are about 1 A/W and 50 pW/Hz1/2. Also about 231μW/pixel decrement in power consumption for the same responsivity, and a same bandwidth have been achieved. [ABSTRACT FROM AUTHOR]

• Self-powered and transparent (˜47%) SnO 2 /SnS 2 photodetector is designed. • In 2 O 3 (50 nm) interlayer facilitates two staggered gap (type- II) heterojunctions. • Increases photocurrent (11.6–14.7 μA) and reduces dark current (6.9–2.8 μA). • With a high rise and fall time of 59 and 79 μs, respectively. Light signals are widely employed in communications, military, health and space exploration applications, driving demand for self-powered photodetectors and sensors. Generally, the built-in potential in the heterojunction interface facilitates self-powered operation. However, this interface often contains defect states due to lattice mismatch and large differences in work function, which increases the dark current even under zero bias condition. In this article, we report the design of a self-powered and transparent (˜47%) photodetector using a SnO 2 /SnS 2 heterojunction. In addition, we successfully demonstrate a reduction in dark current (6.9–2.8 μA) with a simultaneous increase in photocurrent (11.6–14.7 μA) by introducing an In 2 O 3 interlayer in the SnO 2 /SnS 2 heterojunction, while maintaining the average transparency of ˜47%. In addition, the fabricated device exhibited high rise and fall times of 59 and 79 μs, respectively. An energy band diagram based on the material work functions illustrates the creation of two staggered gap (Type- II) heterojunctions due to the embedded In 2 O 3 nanolayer. This feasible band alignment facilitates the smooth transport of the photogenerated charge carriers. The interlayer also aids lattice matching while reducing defect states in the interface. The interface engineering by using a nanoscale layer embedment would effectively facilitate the feature of photoelectric device without degrading device transparency. This clearly demonstrates that the functional use of interlayer strongly enhances the device performances to suggest the further possible improvement in the transparent optoelectronics. [ABSTRACT FROM AUTHOR]

A SiC trench MOSFET with a merged heterojunction diode is proposed and numerically analysed here. The merged heterojunction diode can effectively suppress the turn-on of the parasitic body diode in the proposed SiC trench MOSFET. In addition, a P + shield layer surrounding the gate oxide layer can dramatically alleviate the gate oxide corner from the concentration of the electric field and improve the static and dynamic performances of the proposed device. As a result, not only the breakdown voltage is increased by 24% but also the miller charge and the switching losses of the proposed structure are reduced by 43 and 48.6%, respectively, when compared with those of the conventional SiC trench MOSFET with a grounded P + shield layer. Moreover, the short-circuit capability and its failure mechanism are numerically studied for the proposed structure. Finally, a feasible fabrication procedure is provided to realise the fabrication of this new device. [ABSTRACT FROM AUTHOR]

In this paper, a package concept based on low-temperature cofired ceramic (LTCC) technology is illustrated. The concept is specifically designed for frequencies beyond 100 GHz, taking into consideration the inherent LTCC manufacturing defects, e.g., shrinkage, layer misalignment, and warping. Simple techniques are used for package assembly which can be automated using standard industrial processes. The proposed concept is implemented by integrating a 122-GHz silicon-germanium (SiGe) radar transceiver chip in an LTCC-based package. The off-chip components of the package, operating at 122 GHz, include a transmit (Tx) and a receive (Rx) aperture-coupled patch antenna array, a stripline to grounded coplanar waveguide signal transition feeding each of the antenna arrays, and three parallel, self-matched ground-signal-ground wirebonds connecting the SiGe radar transceiver chip and the LTCC package on Tx and Rx side. The simulation and measurement results of the Tx and Rx antenna arrays along with the signal transitions in the frequency range of 110–140 GHz are shown. The radar front end (RFE) is encapsulated using an epoxy molding compound, Polytec TC 430-T with suitable dielectric characteristics in the desired frequency range. The encapsulated RFE is surface mounted on a baseband printed circuit board, thereby realizing a fully functional 122-GHz frequency modulated continuous wave (FMCW) radar. The FMCW radar is used to measure the distance of a target, and the measurement results are compared with those of a commercial 122-GHz RFE. [ABSTRACT FROM AUTHOR]

We measure the strain of a channel between Si/Ge stressors in a tri-gate p-channel metal–oxide semiconductor device, known as a fin field-effect transistor (FinFET), by utilizing moiré fringes in scanning transmission electron microscopy (STEM). These fringes reveal a pseudomagnified Si lattice, resulting from undersampling of the crystalline lattice with the nodes of the scanning grid of STEM. A practical device sample is prepared using a focused ion-beam instrument. The sample lamella is cut along the X direction to allow observation of the strained channel between Si/Ge stressors. The measurement of channel strain in a FinFET is not easy, since the channel is sandwiched between top and bottom layers of gate electrodes and insulators. For the strain measurement, we use the moiré fringes of the Si[220] lattice. These moiré fringes extract only the targeted lattice and act as a real spatial frequency filter. Other fringes with different directions and/or spacings are thereby filtered out. The strain along the channel between the Si/Ge stressors is measured to be −0.9%, with the whole procedure taking less than 5 min, including data acquisition time, using a dedicated program. As the fringe contrast is weak owing to disturbances by the gate and insulator layers, a microscope is equipped with an aberration corrector in the probe-forming system to enhance the contrast. The proposed method offers a high-throughput strain measurement, since it is performed in the image acquisition mode, and is easily incorporated into the standard workflow for critical dimension measurements. [ABSTRACT FROM AUTHOR]

Copyright of Dilemas Contemporáneos: Educación, Política y Valores is the property of Dilemas Contemporaneos: Educacion, Politica y Valores and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Advanced channel formation technologies called HEtero-layer-lift-off utilizing SiGe heteroepitaxy have been realized for fabricating ultrathin body (UTB) Ge-on-insulator (GeOI) structures. Insertion of SiGe etching stop layer was found to be effective for reducing GeOI body thickness ($T_{\mathrm {body}}$) fluctuation. Backside Si passivation for Ge/buried oxide interface has been verified to suppress backside Coulomb scattering and help to induce volume inversion effect. With improvement of backside interfacial quality and precise control of GeOI $T_{\mathrm {body}}$ , primary carrier scattering factors in GeOI channel have been effectively reduced, resulting in significant improvement of hole mobility. High hole mobility of ~150 cm2/Vs in UTB GeOI pMOSFETs without strain technology has been demonstrated, which also outperformed Si universal mobility by 1.5 times even under $T_{\mathrm {body}}$ of 9 nm. With low-thermal-budget process compatibility, UTB GeOI platform is very promising for future Ge large-scale integrated circuits devices used in monolithic 3-D integration scheme. [ABSTRACT FROM AUTHOR]

The performance of a p-channel FinFET comprising a heterogeneous silicon (Si) and silicon-germanium (Si0.9Ge0.1) channel region is evaluated using three-dimensional TCAD simulations and benchmarked against a conventional p-channel Si FinFET. The results show that the hetero-channel design provides for larger ON-state current while maintaining comparable electrostatic integrity as the conventional design due to the valence band offset between Si0.9Ge0.1 and Si. The enhanced performance is achieved with a relatively low Ge mole fraction (10%) in the channel region for ease of manufacture. Therefore, the hetero-channel FinFET is promising for future low-power applications. [ABSTRACT FROM AUTHOR]

This paper describes a design approach for stack connected transistor amplifiers used in the realization of two highly compact SiGe:C BiCMOS amplifiers. The first, realized in a 250 nm process, is designed to operate at Ka band and occupies an area of 0.24 mm2. It is capable of delivering a saturated output power of 16.8 dBm with an output 1 dB compression point of up to 15 dBm. It achieves a small signal gain higher than 15 dB and has a measured power added efficiency of 15%. The second is realized in a 130 nm process and operates at W band. Occupying an area of only 0.02 mm2, it has a small signal gain of 14 dB with a 33 GHz 3 dB bandwidth centered around 89 GHz. It consumes 104 mW from a 5 V supply and delivers a saturated output power of 9 dBm between 92 and 102 GHz in simulation. [ABSTRACT FROM AUTHOR]

The single-event transient response of a high-voltage complementary SiGe-on-silicon-on-insulator technology is investigated along with its temperature dependence using a pulse laser. The p-n-p silicon-germanium heterojunction bipolar transistor (SiGe HBT) shows a larger transient peak amplitude compared to the n-p-n SiGe HBT, which is largely related to the differences in total device volume and peak germanium content between the p-n-p and n-p-n devices. The effects of temperature on the transient response are also investigated using heaters and sensors mounted directly on the device-under-test package. The collector transient peak amplitude shows a negative temperature coefficient for a $V {_{\text {CB}}}$ of 0-V condition, for both the n-p-n and p-n-p devices. However, the temperature dependence of the transient peak amplitude becomes significantly weaker at $V {_{\text {CB}}}>0$ V. Calibrated TCAD simulations were performed to better understand the temperature dependence, and the simulations indicated that the electric field and mobility at higher $V {_{\text {CB}}}$ have a reduced temperature dependence than at a $V {_{\text {CB}}}$ of 0 V. The effects of self-heating are also explored using TCAD simulations and show that even under aggressive self-heating conditions, there is only less than 10% reduction in transient peak amplitude with the self-heating models turned on. The results shown suggest that this particular SiGe technology can be used for environments where highly energetic particles and high temperatures are encountered simultaneously. [ABSTRACT FROM AUTHOR]

Silicon waveguide (WG) integrated p-i-n germanium photodiodes (PDs) from a monolithic electronic–photonic integrated circuit technology were exposed to ionizing radiation from a 10-keV X-ray source to investigate total ionizing dose effects. Existing work on radiation effects in PDs, which is almost entirely based on normal-incidence PDs (rather than WG-integrated PDs), is reviewed to provide context and a framework for understanding the measurement results. Back-end-of-line considerations suggest the enhancement of the ionizing dose due to high- $Z$ materials near the PD. PD performance was characterized in terms of dark current, S-parameters, dc photocurrent response, and optical-to-electrical conversion frequency response, shortly before and after irradiation. No significant degradation was observed, indicating that these devices may be suitable for applications in harsh radiation environments. [ABSTRACT FROM AUTHOR]

Abstract: Plasmonic enhancement of the photoluminescence in hybrid structures with SiGe quantum dots and Ag nanoislands was found. Ag nanoislands grown on the top of the multilayer structures with SiGe quantum dots (QDs) support a surface plasmon resonance that can be tuned to the QD emission wavelength by changing of Ag nanoparticle parameters. Photoluminescence measurements of the hybrid metal-semiconductor nanostructures revealed a fourfold increase of the integral intensity of SiGe QD emission in the spectral range from 0.8 to 1 eV. [ABSTRACT FROM AUTHOR]

Abstract Multi-finger silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) are attractive to the radiation-intense environment. This paper investigates the performance of proton-radiated SiGe power HBTs with different finger numbers (8, 24, 40, and 80 emitter fingers) at room and cryogenic temperatures. Different proton radiation fluences (1 × 1012 p/cm2, 2 × 1013 p/cm2, and 5 × 1013 p/cm2) and ambient temperatures (300 K and 77 K) were used to study the irradiation performance of the HBTs. Results show that the number of emitter fingers has a significant impact on the performance of the SiGe power HBTs for different temperatures and irradiation conditions. Underlying mechanisms have been discussed. This study provides guidelines on designing and using SiGe power HBTs for integrated circuits in radiation environments at room and cryogenic temperatures. Highlights • This work investigates the performance of proton-radiated SiGe power HBTs with different finger numbers at 300 K and 77 K. • The degradation mechanism was analyzed via measurement of direct current and alternating current properties. • Results show that the number of emitter fingers is the main affecting factor of electrical properties for radiated HBTs. [ABSTRACT FROM AUTHOR]

TFETs are promising candidates for future low-power logic applications because of their potential for outperforming conventional MOSFETs under reduced supply voltage (${V} _{\textsf {DD}}$). Among all material systems currently being explored, group IV semiconductor SiGe holds the most potential due to its very large scale integration (VLSI) compatibility, mature synthesis techniques, and tunable bandgap, making it more likely to be adopted for future VLSI technologies. It has been shown experimentally that the on-state current (${I} _{\textsf {on}}$) of SiGe TFETs improves significantly with the increasing Ge content. However, increasing the Ge content leads to excessive leakage in the off-state and poses a challenge to the pseudomorphic growth of SiGe. In this paper, the concept of Ge-pocket TFET with a counter-doped pocket is proposed. By confining Ge to the pocket region, the proposed structure circumvents those problems. Both the steep subthreshold swing and high ${I} _{\textsf {on}}$ can be achieved. The proposed TFET also demonstrates excellent scalability in terms of physical gate length (${L} _{\textsf {gate}}$) and ${V} _{\textsf {DD}}$ , which makes it a promising replacement of conventional MOSFETs for low-power logic applications. [ABSTRACT FROM AUTHOR]

In this work, all group-IV band-to-band lasers based on SiGeSn/GeSn/SiGeSn multi-quantum-well structures were demonstrated. Lasing performance was investigated via two 4-well samples. The thinner GeSn well sample exhibits a maximum lasing temperature of 20 K and a threshold of 55 kW/cm2 at 10 K, while the thicker well sample features a higher maximum operating temperature of 90 K and lower lasing thresholds of 25 and 62 kW/cm2 at 10 and 77 K, respectively. The distinct results were tentatively interpreted mainly by the difference of gain volume. This result provides guidance for the future GeSn quantum well laser optimization for higher performance. [ABSTRACT FROM AUTHOR]

This paper presents the total dose effects of gamma ray and swift heavy ion irradiation on silicon-germanium heterojunction bipolar transistors (SiGe HBTs). The direct current (DC) characteristics, such as forward-Gummel, reverse-Gummel and current ideality factors before and after irradiation are analyzed and used to quantify the dose tolerance. Experiment results show that the performance degradation depends on the dose rate and bias condition during gamma ray irradiation. Compared to gamma ray irradiation, more serious base current degradation exists in the transistors exposed to 25 MeV Si ion. The base current in forward- and reverse-Gummel mode are found to show a distinct sensitivity to gamma ray and swift heavy ion irradiation. An increase in emitter current appears in the reverse-Gummel test after heavy ion irradiation. The underlying physical mechanisms are analyzed and investigated in detail. [ABSTRACT FROM AUTHOR]

Several industrial applications require specific electronic systems installed in harsh environments to perform measurements, monitoring, and control tasks such as in space exploration, aerospace missions, automotive industries, down-hole oil and gas industry, and geothermal power plants. The extreme environment could be surrounding high-, low-, and wide-range temperature, intense radiation, or even a combination of above conditions. We review, in this paper, the main leading applications that demand advanced technologies to fit the unconventional requirements of extreme operating conditions, discussing their main merits and limits compared to established and emerging technologies in this field, including silicon (Si), silicon on insulator (SOI), silicon germanium (SiGe), silicon carbide (SiC) as well as III–V semiconductors particularly the gallium nitride (GaN) semiconductor. In spite of successfully exceeding extreme conditions borders by developing advanced semiconductor devices dedicated for harsh environments, especially in high-temperature applications, the packaging challenges are still limiting the reliability of the developed technologies. Those challenges are examined in this review in terms of limitations and proposed solutions. [ABSTRACT FROM AUTHOR]

A number of millimeter-wave (mm-wave) integrated radar sensors above 100 GHz were proposed in the past five years. The comparability between these radar systems is limited due to different semiconductor processes, synthesizer topologies, and external periphery. Especially, the issue of using a monostatic or bistatic radar monolithic microwave integrated circuit (MMIC) for single-chip sensors is not discussed in detail. This paper provides a comparison between the different properties of bistatic and monostatic MMICs based on two realized almost identical silicon germanium (SiGe)-MMICs at 154 GHz. In the monostatic case, the influence of the transmit–receive coupler on the performance of the system is explained. In the bistatic case, the illumination of a focusing lens and the leakage from transmitter to receiver are investigated. All properties are verified by measurements. The system performance of the monostatic and bistatic MMIC are compared by the calculated link and noise budget. The detection performance and the signal-to-noise ratio performance are evaluated in two radar measurements. Limitations and suggestions for improvement are given for monostatic and bistatic mm-wave frequency-modulated continuous-wave radar MMICs. [ABSTRACT FROM AUTHOR]

This paper presents a 32-element phased array centered at 64 GHz using multiple SiGe chips on a single printed-circuit board. The antenna element is a series-fed patch array, which provides directivity in the elevation plane. The transmit array results in an effective isotropic radiated power of 42± 2 dBm at 63–65.5 GHz, while the receive array provides an electronic gain of 24 dB and a system noise figure <7.7 dB, including antenna loss, T/R switch, beamformer, and transceiver. The arrays can be scanned to ±50° in the azimuth using a 5-bit phase shifter on the SiGe chip without degradation in sidelobes and maintaining a near-ideal pattern. A communication link between two phased arrays at 100, 300, and 800 m is also demonstrated, and employs one array on the transmit side and another array on the receive side, together with external mixers and IF amplifiers. The link performance was measured for different scan angles and modulation formats. Data rates of 0.5–2 Gb/s using 16-QAM and QPSK waveforms are demonstrated at 100–800 m, with 2-Gb/s data rate at 300 m and ~500-Mb/s data rate at 800 m. To the best of our knowledge, this is the first system-level demonstration of a silicon-based Gb/s 60-GHz phased array over hundreds of meters. Application areas are in point-to-multipoint links, back-haul and front-haul links, and reconfigurable mesh networks for advanced communication systems. [ABSTRACT FROM AUTHOR]