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An analysis of NanoSheet (NS) transistor parasitic resistance components is presented and correlated to the resistance readout on Si wafers. With this model, it is possible to identify which components cause the parasitic resistance increases as CPP (contacted poly-Si pitch) further scales from 48 nm to 44 nm pitch. In this study, an alternative MOL (middle of line) metallization scheme is implemented to reduce circuit RC delay. This model helps to further reduce the transistor parasitic resistance from NFET/PFET S/D (source/drain) epitaxy or silicide. As CPP scales, NS PFET parasitic resistance reduction is more challenging and requires optimization in S/D epitaxy, silicide and metallization. Based on parasitic resistance modeling, we present a new wrap-around contact structure which eliminates the vertical epi resistance component, hence reducing overall device resistance.

The drive to deliver increasingly powerful and feature-rich integrated circuits has made technology node scaling—the process of reducing transistor dimensions and increasing their density in microchips—a key challenge in the microelectronics industry. Historically, advances in optical lithography patterning have played a central role in allowing this trend to continue. Directed self-assembly of block copolymers is a promising alternative patterning technique that offers sub-lithographic resolution and reduced process complexity. However, the feasibility of applying this approach to the fabrication of critical device layers in future technology nodes has never been verified. Here we compare the use of directed self-assembly and conventional patterning methods in the fabrication of 7 nanometre node FinFETs, using an industrially relevant and high-volume manufacturing-compliant test vehicle. Electrical validation shows comparable device performance, suggesting that directed self-assembly could offer a simplified patterning technique for future semiconductor technology. A comparison between the use of directed self-assembly and conventional patterning methods in the fabrication of 7 nm node FinFETs shows similar device performance, suggesting directed self-assembly could offer a simplified patterning technique for future semiconductor technology nodes.

In this paper, full bottom dielectric isolation (BDI) is first demonstrated on horizontally stacked Nanosheet device structures with Lmetal 12 nm. The comparison of full BDI scheme vs punch through stopper (PTS) scheme has been systematically studied. By comparing off-state leakage current, short channel behavior and effective capacitance (Ceff) for both schemes, we show that BDI could potentially provide: 1) good immunity of sub-channel leakage due to process variation (from parasitic "fat-Fin" which is unique in Nanosheet structure); 2) power-performance co-optimization.

We demonstrate a novel self-aligned gate contact (SAGC) scheme with conventional oxide/nitride materials that allows superior process integration for scaling while simplifying the SRAM cross-couple wiring. We show that the key feature to avoid both gate-contact (CB) to source-drain local interconnect (LI) shorts and the LI-contact (CA) to gate shorts is the shape of the LI cap. A trapezoid-shaped oxide (SiO 2 ) LI cap with an appropriate taper angle eliminates shorting between the contacts in the gate and source-drain region. We further demonstrate that this oxide LI cap is fully compatible with Cobalt (Co) metallization with a novel selective tungsten (W) growth process. Additionally, this process enables the SRAM cross-couple (XC) in the same metallization level, eliminating the need for an upper level wiring and greatly simplifying routing in the SRAM cell.

In this paper, we present for the first time a “Gate-Cut-Last” integration scheme completed within the Replacement Metal Gate (RMG) module. This novel gate cut (CT) technique allows the scaling of gate extension length past the end fin which reduces parasitic capacitance, leakage and performance variation. In addition, we demonstrate that CT-in-RMG is a promising alternative integration process that can enable scaling for future logic technology nodes. Device, circuit and reliability results are shown to compare this novel CT-in-RMG process to the conventional gate cut method.

Self-aligned contact (SAC) is required for 7 nm node to reduce susceptibility of contact-to-gate short failures. This requires forming a SAC cap on metal-recessed gate. The SAC cap formation is usually achieved by removing nitride on the field by planarization techniques such CMP (chemical mechanical polishing) or GCIB (gas cluster ion beam) processes. Significant gate stack height variation can be observed lot-to-lot and wafer-to-wafer due to accumulated variations from multiple steps, including several CMP steps, before the SAC cap module, especially during early research and development prior to full optimization of the steps before the SAC cap module. GCIB potentially offers a method by which the early development stage variation due to CMP steps can be reduced, allowing integration and device learning during the early stages of a program. This study shows a comparison of SAC cap formation by CMP only vs. GCIB with integrated metrology enabled location specific processing. By using GCIB with feed-forward scatterometry measurements taken from a 2D measurement pad we have been able to significantly improve both lot-to-lot and wafer-to-wafer variation on early development wafers. This has led to improvement in within wafer SAC cap thickness non-uniformity, wafer to wafer and lot to lot device yield for gate-contact over a CMP-only process flow.

We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.

We discuss the transition to Ti based silicides for source-drain (SD) contacts for 3D FinFET devices starting from the 14nm node & beyond. Reductions in n-FET & p-FET contact resistances are reported with the optimization of metallization process & dopant concentrations. The optimization of SiGe epitaxy and addition of a thin interfacial NiPt(10%) are found to significantly improve p-FET contact performance.

A novel surface passivation technique using silicon nitride (SN) by - treatment has been demonstrated on -gated Ge pMOSFETs. It is found that ultrathin SN passivation is more effective to suppress the Ge out diffusion than ultrathin Si passivation. Improved interface quality and device performance were achieved for the device with the SN passivation. Fluorine (F) incorporation by postgate treatment was also implemented to further enhance the performance. Furthermore, bias temperature instability (BTI) characteristics were systematically investigated on interface engineered (Si-, SN-, or -passivated) Ge pMOSFETs by both conventional dc - and fast pulse measurement. The impact of thickness and postgate treatment processes (F incorporation) on BTI and device performance was also studied, and it is found that BTI and device performance can be improved by reducing the thickness or incorporating F.

As the continual scaling of the modern complementary metal oxide semiconductor field effect transistors (MOSFTEs), silicon (Si) is approaching its fundamental limits. A high mobility channel MOSFET with high permittivity (high-k) gate dielectric is attractive because of both the enhanced carrier mobility and device scaling capability. Germanium (Ge) is a promising channel material due to its lower effective carrier masses compared to those of silicon, which gives it a higher bulk electron and hole mobility. However, the lack of a stable Ge oxide makes it a big challenge to achieve high interface quality, which determines critical performance characteristics of MOS capacitors and transistors. Fortunately, the emergence of high-k dielectric gives opportunity to fabricate devices having both merits of high-k and Ge. To have a high quality high-k gate stack on Ge substrate, minimizing the GeOx at the surface between the high-k and substrate is a critical issue, because germanium oxide is thermally unstable, water soluble and of poor electrical properties. To minimize the GeOx, interface engineering is needed in forming high quality gate stack. Generally, there are two kinds of approaches have been explored: one is to implement careful surface passivation before the formation of high-k gate stack and the other is to explore further passivation process after the high-k gate stack formation, which we call it “post-gate” treatments. In this talk, we will first review various surface passivation technologies developed recently for making high quality high-k gate stack on germanium substrate for MOSFETs applications, these including surface nitridation, silane passivation, sulfur passivation using (NH4)S wet chemical, and GeO2 passivation layer. Different physical characterization methods and electrical results of MOS devices have been employed to understand and compare these surface passivation effects. In addition to the surface passivation, two kinds of “post-gate” treatments will also be addressed, including the forming gas anneal (FGA) containing H2 and F plasma treatment. The FGA on Ge MOS devices is not as effective as that on Si MOS devices, but the combination of FGA and F plasma treatment can significantly improve the quality of high-k/Ge gate stack. As a result, after harnessing surface passivation and post-gate treatments, a record-high drain current is demonstrated for Ge p-channel MOSFETs. Finally, a few characterization techniques will be compared to evaluate the Ge interface quality, including the charge pumping method, with some preliminary study on BTI and charge trapping properties on Ge MOSFETs. 215th ECS Meeting, Abstract #822, © The Electrochemical Society

A post-gate CF4-plasma treatment process is proposed and demonstrated on Ge MOS devices and the effects of F incorporation have been extensively studied on both high-k/Ge gate stacks without any surface passivation and with Si surface passivation. Our results show that: (1) F is effectively introduced into the gate stack by CF4 treatment and segregates near high-k/Ge interface; (2) Electrical characteristics like Dit, gate leakage, C-V hysteresis and breakdown voltage are improved after F incorporation; (3) Post-gate CF4 treatment is also compatible with pre-gate surface passivation, and it can further enhance the device performance. By combining Si surface passivation and post-gate CF4 treatment, interface quality has been greatly improved for high-k/Ge gate stack and a high peak hole mobility of 376 cm2/V⋅s has been achieved for Ge pMOSFETs

In this work, a simple model, with a higher interface trap density in the upper half of Ge bandgap than that in the lower half, is proposed to explain the abnormal behaviors in Capacitance-Voltage characteristics of both p- and n-MOS capacitors on Ge substrate using different surface passivation. Variable rise/fall-time charging pumping measurement is used to study the energy distribution of interface trap density in HfO2 gated Ge MOSFETs. Our results reveal that Dit is higher in the upper half of the Ge bandgap than that in the lower half of the bandgap. These results are also consistent with the observation that n-channel mobility is more severely degraded compared to p-channel for Ge MOSFET.

In this letter, we study the effects of sulfur (S) passivation, using aqueous ammonium sulfide ((NH4)2S), on germanium (Ge) MOS capacitors with sputtered HfON as gate dielectric and TaN as metal-gate electrode. Compared with control samples, the S passivation can effectively reduce both equivalent oxide thickness and interface-state density. X-ray-photoelectron-spectroscopy analysis shows that (NH4)2S treatment can reduce the Ge-O bonds on Ge surface. The thermal stability of the S passivation under different postmetal-annealing temperatures was also examined, and it was found that samples with (NH4)2S treatment exhibit stable Ge/high-fc interface upon 550-deg C postmetal-deposition annealing, whereas interface quality degrades for those samples without S passivation.

In advanced node semiconductor manufacturing, Chemical Mechanical Polish (CMP) is a critical integration step to many modules, from fin formation, replacement metal gate (RMG), to interconnects. In each application, CMP’s stop-on capability is increasingly seen as an essential element in gauging device integrity, and thus is critical to the successful implementation of a technology. Traditionally, CMP selectivity is merely a characteristic of slurry chemistry and its abrasive materials, and is measured by blanket rates of the corresponding films. However, in advanced node semiconductor manufacturing, as feature sizes are at Nano scale and polishing precision needs to be controlled at angstrom level, this slurry selectivity does not necessarily translate to a good stop-on capability. At this precision level, stop-on performance is sensitive to the selection of CMP pad as well as how the CMP process is developed. It is also highly sensitive to the integration process, including the deposition process and various integration steps leading to CMP. This presentation reviews the critical roles CMP plays in fin formation, replacement metal gate (RMG) and local interconnects. Taking middle of line (MOL) CMP steps as examples, detailed discussion will be presented on how selectivity is modulated and how the needs of stop-on capability is balanced with the need to make sure complete clearing.

The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore’s law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the sub-22nm non-planar finFET technologies that are either in advanced technology development or in manufacturing. It discusses the integration challenges in patterning for both the front-end-of-line and back-end-of-line elements in the CMOS transistor. In addition, this article also gives a brief review of integrating an alternate channel material into the finFET technology, as well as next generation device architectures such as nanowire and vertical FETs. Lastly, it also discusses challenges dictated by the need to interconnect the ever-increasing density of transistors.

In this paper, we present a 10nm CMOS platform technology for low power and high performance applications with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrates. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limits. Multi-workfunction (MWF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by Random Dopant Fluctuation (RDF) from channel dopants.

A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um 2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limit. Multi-workfunction (WF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by channel dopants.

The title reaction uses readily available 2-(2-bromophenyl)-indoles (I) and ketones (II) and (IV) as starting materials.

A simple and efficient copper-catalyzed method for the synthesis of 11H-benzo[a]carbazoles has been developed. The protocol uses readily available substituted 2-(2-bromophenyl)-1H-indoles and ketones as starting materials and an inexpensive catalyst system. The corresponding 11H-benzo[a]carbazoles were obtained in moderate to excellent yields.

An efficient copper-catalyzed method for N-arylation of amines has been developed with part-per-million catalyst loadings at room temperature under air. Reactions of substituted (E)-1-(2-halophenyl)alkanone oximes with aliphatic amines or aromatic amines provided the N-arylation products in good to excellent yields.

High-k/germanium (Ge) interfaces are significantly improved through a new interface engineering scheme of using both effective pregate surface GeO2 passivation and postgate dielectric (postgate) treatment incorporating fluorine (F) into a high-k/Ge gate stack. Capacitance-voltage (C-V) characteristics are significantly improved with minimum density of interface states (Dit) of 2 times 1011 cm-2 ldr eV-1 for Ge MOS capacitors. A hole mobility up to 396 cm2/V ldr s is achieved for Ge p-metal-oxide-semiconductor field-effect transistors (pMOSFETs) with equivalent oxide thickness that is ~10 Aring and gate leakage current density that is less than 10-3 A/cm2 at Vt plusmn 1 V. A high drain current of 37.8 muA/mum at Vg - Vt = Vd = -1.2 V is presented for a channel length of 10 mum. The Ge MOSFET interface properties are further investigated using the variable-rise-and-fall-time charge-pumping method. Over three times Dit reduction in both upper and lower halves of the Ge bandgap is observed with F incorporation, which is consistent with the observation that frequency-dependent flat voltage shift is much less for samples with F incorporation in the C-V characteristics of Ge MOS capacitors.

High-k/Ge interfaces are significantly improved through a new interface engineering scheme of using both effective pre-gate surface GeO2 passivation and post gate dielectric (post-gate) treatment incorporating fluorine (F) into high-k/Ge gate stack. Minimum density of interface states (Dit) of 2 times 1011 cm-2eV-1 is obtained for Ge MOS capacitors. Hole mobility up to 396 cm2/Vs is achieved for Ge pMOSFETs with EOT ~10 Aring and gate leakage current density less than 10-3 A/cm2 at Vt plusmn 1 V. Best drain current to date of 37.8 muA/mum at Vg-Vt = Vd= -1.2V is presented for an Lg of 10 mum. Variable rise and fall time charge pumping (CP) method is used to investigate Ge interface property and a significant Dit reduction in both upper and lower half of bandgap is observed with F incorporation.

A thin palladium layer (~20 A) was selectively formed on top of amorphous germanium film before annealing and the effects of palladium layer on the lateral crystallization behavior of the amorphous germanium film were investigated through optical microscope, Raman spectroscopy, transmission electron microscopy, energy dispersion X-ray spectroscopy and selective area electron diffraction. Lateral crystallization of Ge with high growth rate was observed after annealing at 400°C in N2 ambient. High quality poly-crystallized Ge film was formed with little metal impurity. This lateral crystallization phenomenon might be useful for fabrication of 3D ICs as the channel materials for thin film transistors, as well as for integration of Ge photodetectors on top of Si ICs.

In this paper, various interface engineering techniques for high-k/Ge gate stack for advanced CMOS device applications are reviewed. High-k gate stack formation on Ge substrate is first addressed with emphasis on pre-gate surface passivation. Post gate dielectric (post-gate) treatments are then discussed to further improve the high-k/Ge interface quality.

An efficient copper-catalyzed method for N-arylation of amines has been developed with part-per-million catalyst loadings at room temperature under air. Reactions of substituted (E)-1-(2-halophenyl)alkanone oximes with aliphatic amines or aromatic amines provided the N-arylation products in good to excellent yields.

Metal-induced lateral crystallization (MILC) of Si1-x Ge x (0≤x≤1) using Ni, Co, and Pd is carried out at 375 °C. It is found that the MILC rates increase with increasing Ge fraction when Ni and Co are used; however, the rate reaches a maximum at Ge mole fraction of 0.7 for Pd induced lateral crystallization of SiGe. The difference in these two trends is due to different contributions of the three processes involved during the metal-induced crystallization. Using Ni and Co, the MILC rates of Si1-x Ge x are limited by the silicon germanide formation and diffusion process for all Ge mole fractions. While the MILC rate of Si1-x Ge x using Pd is also controlled by these two processes when x is smaller than 0.7, the rate is dominantly limited by the lattice mismatch between silicon germanide and SiGe when the Ge mole fraction is larger than 0.7. Comparing the quality of MIC Ge films induced by the three metals, crystalline Ge film induced by Co has the largest grain size and the smoothest surface. Regarding the MILC rate, Pd has a similar rate as Ni in MILC of Ge, and a much higher rate than those of Ni and Co in MILC of Si0.3Ge0.7.

Low temperature (ranging from 350 to 420°C) metal induced lateral crystallization of Ge using germanide forming metals Ni, Co, and Pd is performed. The lateral growth lengths and crystallized Ge films' quality are optimized when annealed at 375°C, above which self-nucleation in Ge hinders the metal induced crystallization process. At 375°C, the sample with Pd as the seed metal has the largest lateral growth length, while the sample using Co as the seed layer exhibits the largest crystal grain size. The experiments suggest that the lateral growth length is associated with the diffusivity of the metal and germanide in Ge, while the crystal quality is related to the lattice mismatch between germanide and Ge.

In this article, metal (palladium, Pd)-induced lateral crystallization (MILC) of amorphous-germanium (α-Ge) films prepared by room-temperature sputtering on an insulating material (SiO 2 ) is observed and investigated using micro-Raman microscopy and transmission electron microscopy. The planar α-Ge thin films were annealed at 300, 350, and 400°C in a N 2 ambient. The MILC phenomenon is not observed for the samples annealed at 300°C for 2 h, while the MILC phenomenon is observed for α-Ge films annealed at 350 and 400°C for 2 h with a lateral growth rate of ∼ 1.1 and 1.3 μm/h, respectively. A poly-Ge film with a 400°C annealing temperature exhibits a smaller full width at half-maximum and a higher intensity of the sharp c-Ge peak than that annealed at 350°C, which can be the promising material candidate for Si-based three-dimensional integrated circuit applications.

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The energy distribution of interface trap density (Dit) in HfO2 gated germanium metal-oxide-semiconductor field effect transistors (MOSFETs) is investigated by using charge pumping method with variable rise/fall-time measurement. Our results reveal that a high density of interface traps is present in the upper half of the Ge bandgap. As a result, the inversion-layer electron mobility of Ge n-channel MOSFETs was significantly degraded by the Coulomb scatterings. These results are also consistent with the abnormal capacitance-voltage (C-V) characteristics of Ge MOS capacitors.

Effective pregate surface passivation and postgate treatments are very important to optimize the germanium metal-oxide-semiconductor (MOS) interface quality. In this work, pregate GeO2 surface passivation and postgate treatments including CF4-plasma treatment and forming gas annealing are employed to make high quality HfO2 gated germanium MOS capacitors. Excellent electrical characteristics with negligible capacitance-voltage stretch-out and frequency dispersion are achieved. The interface trap density of TaN∕HfO2∕GeOx∕Ge MOS structure is as low as 2.02×1011cm−2eV−1 at the minimum. Comparing to the forming gas annealing, it is found that CF4-plasma treatment is more effective to passivate interface states located in the upper half of Ge bandgap.

In this letter, a postgate CF4-plasma treatment is proposed and demonstrated on germanium (Ge) metal-oxide-semiconductor capacitors and the effects of fluorine (F) incorporation have been studied on both high-k∕Ge gate stacks without any surface passivation and with Si surface passivation. Our results show that F is effectively introduced into the gate stack by CF4 treatment and segregates near high-k∕Ge interface. Electrical characteristics such as frequency dispersion, interface state density (Dit), and gate leakage are improved after F incorporation. Interface quality of high-k∕Ge gate stack is further improved by combining Si surface passivation and postgate CF4 treatment, with its Dit as low as 4.85×1011cm−2eV−1.