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A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

Authors :
Jeffrey C. Shearer
Philip J. Oldiges
Soon-Cheon Seo
Terry A. Spooner
Matthew E. Colburn
Ravikumar Ramachandran
V. Sardesai
Kang-ill Seo
Dinesh Gupta
Richard G. Southwick
Xiao Sun
S. Stieg
H. Cai
S. Kanakasabaphthy
Vamsi Paruchuri
R. Sampson
Lars W. Liebmann
Walter Kleemeier
Kisik Choi
Deok-Hyung Lee
Christopher Prindle
R. Divakaruni
H. Shang
Abhijeet Paul
T. Gow
D. McHerron
Dechao Guo
Fee Li Lie
J. Nam
Neeraj Tripathi
Ruilong Xie
R. Kambhampati
Muthumanickam Sankarapandian
Balasubramanian S. Pranatharthi Haran
Carol Boye
James H. Stathis
B. Hamieh
John Iacoponi
Christopher J. Waskiewicz
Geum-Jong Bae
Derrick Liu
Sanjay Mehta
Reinaldo A. Vega
Terence B. Hook
Min Gyu Sung
Jay W. Strane
D.I. Bae
Robin Chao
Hoon Kim
F. Nelson
Theodorus E. Standaert
L. Jang
Erin Mclellan
M. Celik
S. Nam
Tae-Chan Kim
C.-C. Yeh
Sean D. Burns
P. Montanini
Charan V. V. S. Surisetty
Raghavasimhan Sreenivasan
Ju-Hwan Jung
B. Lherron
S.-B. Ko
E. Alptekin
Huiming Bu
Injo Ok
Jin Cho
Mukesh Khare
J. G. Hong
Gen Tsutsui
Andreas Scholze
Bomsoo Kim
D. Chanemougame
M. Mottura
M. Weybright
H. Mallela
K. Kim
Hemanth Jagannathan
Chanro Park
J. Jenq
Donald F. Canaperi
Young-Kwan Park
R. Jung
Kangguo Cheng
Source :
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.
Publication Year :
2014
Publisher :
IEEE, 2014.

Abstract

A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um 2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limit. Multi-workfunction (WF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by channel dopants.

Details

Database :
OpenAIRE
Journal :
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers
Accession number :
edsair.doi...........d4d82166b734af3db83f196d83853ba5