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We discuss advances in our research on 300mm GaN NMOS by demonstrating GaN-on-Si(111) NMOS transistors achieving low R ON =330Ω-μm; high ID,max=1.7mA/μm; BV DS (at I D =1μA/μm) of up to 90V with excellent R ON =660Ω-μm; record f T /f MAX of 200/350GHz for GaN-on-Si; industry’s best RF switch R on C off =55fs; and highest mmwave (28GHz) RF power amplifier peak PAE of 65% @ 19.5dBm saturated power. We discuss and compare the challenges in approaches to GaN and Si CMOS integration research including: (a) poly-silicon CMOS, (b) heterogeneous epitaxy of GaN and Si(111) CMOS, (c) wafer-to-wafer bonding [2], and (d) 3D monolithic Si(100) layer transfer using bonding techniques [1],[3].

In the past 25 years, process and device TCAD used in direct support of industrial process development has undergone radical change. In the era of Dennard scaling [1], TCAD efforts in manufacturers such as Intel could arguably be described as advanced applications work. However, with the advent of nanometer device dimensions, the need to calculate fundamental material properties on the fly, resolve quantum effects, and understand the role of atomic-scale defects has shifted TCAD from engineering towards research. Rigorous solutions to Schrodinger’s equations based on NEGF and DFT and semi-classical solutions of the BTE are now in routine use. Concurrently, aging continuum models such as drift-diffusion continue to be infused with more rigorous approaches to maintain accuracy while still affording the fast turn-around-time required by today’s development, which now involves a significant number of novel options under simultaneous consideration. This talk will contrast Intel’s TCAD environment of 25 years ago with today’s and give examples of studies which illustrate the evolution.

Perhaps the greatest challenge facing quantum computing hardware development is the lack of a high throughput electrical characterization infrastructure at the cryogenic temperatures required for qubit measurements. In this article, we discuss our efforts to develop such a line to guide 300mm spin qubit process development. This includes (i) working with our supply chain to create the required cryogenic high volume testing ecosystem, (ii) driving full wafer cryogenic testing for both transistor and quantum dot statistics, and (iii) utilizing this line to develop a quantum dot process resulting in key electrical data comparable to that from leading devices in literature, but with unprecedented yield and reproducibility.

This paper presents key specifications of RRAM-based nonvolatile memory embedded into Intel 22FFL FinFET Technology. 22FFL is a high performance, ultra low power technology developed for mobile and RF applications providing extensive high voltage and analog support and high design flexibility combined with low manufacturing costs [1]. Embedded RRAM technology presented in this paper achieves 104 cycle endurance combined with 85°C 10-year retention and high die yield. Technology data retention, endurance and yield are demonstrated on 7.2Mbit arrays. We describe device characteristics, bit cell integration into the logic flow, as well as key considerations for achieving high endurance and retention properties.

Quantum computing's value proposition of an exponential speedup in computing power for certain applications has propelled a vast array of research across the globe. While several different physical implementations of device level qubits are being investigated, semiconductor spin qubits have many similarities to scaled transistors. In this article, we discuss the device/integration of full 300mm based spin qubit devices. This includes the development of (i) a 28 Si epitaxial module ecosystem for growing isotopically pure substrates with among the best Hall mobility at these oxide thicknesses, (ii) a custom 300mm qubit testchip and integration/device line, and (iii) a novel dual nested gate integration process for creating quantum dots.

This paper presents a simulation study using a novel distributive quasi-ballistic drift diffusion (DD) TCAD model applied to low mobility unstressed and high mobility stressed scaled pMOS devices. The model is implemented in a DD simulator and used to study the gate length dependence of current drives. The new model captures the physically correct potential distribution and gives the correct drive current limit in ballistic devices for both linear current response and current saturation source–drain bias conditions. The diffusive and ballistic transport is connected using a ballistic probability, which relates to the fundamental time scale in the problem—the mean energy relaxation time. The model captures the ballistic velocity degradation from the diffusive limit at linear source–drain biases. It is shown that the DD simulation with the distributive quasi-ballistic model describes the stress ballistic drive gains at high driving field, which are missed by the existing ballistic models.

Despite extensive research, the technology of resistive random-access memory (RRAM) continues to be held back by insufficient understanding of the underlying physics. Using electrostatic and physical-kinetic approaches that are independent of microscopic structural details, the authors make two key observations that lead to a phenomenological theory of RRAM operation. This insight provides closed-form solutions for steady and transient states in terms of material parameters, which should have a significant impact on RRAM engineering.

We present quantum transport simulation results for InAs and In 0.7 Ga 0.3 As double-gate MOSFETs by using an atomistic full-band basis to evaluate the tunneling currents in the OFF state. While InAs has the advantage of lower mass and higher injection velocity, it also has lower bandgap. For low gate bias, the overlap in energy of the valence band in the channel with the source/drain conduction bands results in band-to-band tunneling (BTBT) between source and drain, which clamps the OFF current. Such current can be reduced by increasing the bandgap of the material either by increasing confinement or by lowering the In content, for example, using In 0.7 Ga 0.3 As. Grading the doping of the source/drain region to create a wider barrier also reduces BTBT, but to a lesser extent.

We present a compact model to calculate the capacitance of undoped high-mobility low-density-of-states materials in double-gate device architecture. Analytical equations for estimating the subband energies, while taking the effect of wavefunction penetration into the gate oxide and the effective mass discontinuity, are presented for the first time in a compact modeling framework. The surface potential equation for a two subband system is solved, assuming Fermi-Dirac statistics, and compared to numerical Schrodinger-Poisson simulations. The importance of accurately treating the charge profile distribution is illustrated, and an analytical expression for the effective oxide thickness to model the charge centroid is developed.

This paper discusses the historical role that SiGe has played in driving the CMOS scaling roadmap, including discussion of NMOS biaxial strain and PMOS uniaxial strain. The paper also discusses the potential future role that Ge or SiGe may play in CMOS scaling as a high mobility replacement for the Si channel. Challenges such as poor quality germanium oxide and the small Ge bandgap are reviewed in light of recent developments (high-k metal gate, and ultra-thin body devices) in MOSFET scaling.

We review our novel simulation approach to model the effects of applied stress and wafer orientation by mapping detailed dependencies of long channel physics onto short channel device conditions in Silicon NMOS and PMOS. We use kp and Monte Carlo methods to show the long channel dependencies of these effects on gate fields, doping levels, extrinsic charges, and homogeneous driving fields. Our model predicts the reduced effect of wafer orientation on short channel linear and saturation current drives due to weak gate confinement, high carrier density, high stress, and high driving field prevalent in scaled devices. This reduces NMOS (110) wafer orientation loss compared to (100), while keeping PMOS (110) gains over (100) surface orientation in current drives in 〈110〉 channels, consistent with data.

We have developed a novel simulation approach to model electron mobility in the inversion layer which encompasses all the important effects of arbitrary wafer and applied stress orientations, such as carrier re-population, band warping, and scattering, going beyond the separate treatments of band warping and inversion anisotropy that have been demonstrated. Our model predicts an important consequence of electron band warping in retaining the increase of stress gain at high stress levels in the presence of shear stress at strong inversion.

Tunneling Field Effect Transistor (TFET) has attracted interest due to its steep-SS prospects [1]. Although a number of sub-60mV/dec TFETs were demonstrated [2], many failed to realize this feat due to non-optimized geometry, material choice [3], and material defects [4, 5]. In this paper, we clearly distinguish the requirement for i) geometry, ii) semiconductor BTBT characteristics, iii) semiconductor defects and iv) oxide interface defects. Using Ge as a case study, multi-temperature characterization of experimental PIN diodes is used to separate bulk properties from the interface effects, calibrating the models for BTBT, trap-assisted-tunneling (TAT) and SRH. The measured BTBT characteristic of a material is as important as the effect of defects; even a zero-defect TFET using the calibrated Ge material requires thin body and thin oxide. Bulk SRH and TAT is found to be a less critical issue for thin body TFETs, whereas interface defect density ∼1012cm−2 is low enough to only degrade TFET SS

Due to the success of using strain for performance gain in advanced logic technologies, strain engineering has become an important part of advanced transistor design. This paper presents process and device models that are used to provide understanding of process-induced stress such as the stress due to epitaxial SiGe source drains and nitride capping films and how that stress affects device performance.

A comprehensive quantum anisotropic transport model for holes was used to study silicon PMOS inversion layer transport under arbitrary stress. The anisotropic band structures of bulk silicon and silicon under field confinement as a twodimensional quantum gas are computed using the pseudopotential method and a six-band stress-dependent k.p Hamiltonian. Anisotropic scattering is included in the momentum-dependent scattering rate calculation. Mobility is obtained from the Kubo-Greenwood formula at low lateral field and from the fullband Monte Carlo simulation at high lateral field. Using these methods, a comprehensive study has been performed for both uniaxial and biaxial stresses. The results are compared with device bending data and piezoresistance data for uniaxial stress, and device data from strained Si channel on relaxed SiGe substrate devices for biaxial tensile stress. All comparisons show a very good agreement with simulation. It is found that the hole band structure is dominated by 12 "wings," where mechanical stress, as well as the vertical field under certain stress conditions, can alter the energies of the few lowest hole subbands, changing the transport effective mass, density-of-states, and scattering rates, and thus affecting the mobility

Ballistic on-currents of thin-body n-channel metal-oxide-semiconductor field-effect transistors (n-MOSFETs) are compared across group IV (Si, Ge) and III-V (InAs, In0.5Ga0.5As, GaAs, GaSb) materials for different body thickness values, surface orientations, and transport directions under several idealization assumptions. Previous simulation studies have shown that, as oxide capacitance increases, typical III-V channels with (100) surface perform worse than Si in the ballistic limit due to the degraded density-of-states (DOS). In this letter, simulation results based on tight-binding band structure calculations verify a recent proposal that confined III-V n-MOSFETs with small Γ-L separations overcome the DOS bottleneck and deliver high injection velocities, boosting on-current performance. By using the quantized L-valleys, GaSb with (100) or (111) surface orientations shows the best ballistic performance, outperforming all other materials. Although GaAs (100) and InAs or In0.5Ga0.5As with any surface orientation suffer from the DOS bottleneck, GaAs (111) gives higher ballistic on -currents than Si does.

The transport properties of holes in Si, Ge, and Si1-xGe under high compressive stresses are studied with a Monte Carlo simulation method. Stress significantly improves the low-energy mass and mobility, while its effect is diminished in the high-energy bandstructure. The transient behavior of the carrier velocity exhibits a double-overshoot peak at high driving field. This double-overshoot behavior is manifested in carrier-velocity profiles in simulated short-channel PMOS devices. In steady state at lower field, the hole velocity exceeds the saturation velocity at high field. This leads to a negative differential resistance effect in simulated resistors. We propose to use this effect, generic to cubic semiconductors, for transferred-hole devices. An advantage of this approach is that it can be integrated into the conventional stress-engineered Si or Ge logic process.

Reducing supply voltage (Vdd) while keeping leakage current low is critical for minimizing energy consumption and improving mobile device battery life. The thermal limit of MOSFET subthreshold slope (SS) restricts lowering threshold voltage (Vt), causing significant performance degradation at low Vdd. A Tunneling Field Effect Transistor (TFET) is not limited by this thermal tail and may perform better at low Vdd [1,2]. In this paper, a leading N-TFET option - GaSb/InAs heterojunction - is atomistically modeled [3,4] and circuit simulation models are developed to predict 64% average energy savings against Si CMOS at Lg=13nm for a nanowire. Energy savings diminish to 21% without a good P-TFET option. Both MOSFET and TFET device variations are dominated by work-function variation, and TFET energy savings are slightly reduced when variations are considered.

As the economics of Moores law drives transistor feature scaling, multiple gate devices such as Tri-gate and FinFET transistors have been adopted to control short channel effects. As the device pitch is scaled, traditional strain engineering methods lose effectiveness and parasitics can increase, forcing technologists to evaluate disruptive solutions. Moreover, many local continuum models can no longer accurately describe device behaviour at these scaled dimensions and more advanced models must be adopted to guide process and device development. The challenges of present and future multi-gate device development and the role of technology computer aided design in addressing those challenges are discussed.

Recent attention has been given to metal–oxide–semiconductor field-effect transistor (MOSFET) device designs that utilize stress to achieve performance gain in both n-type MOSFETs (NMOS) and p-type MOSFETs (PMOS). The physics behind NMOS gain is better understood than that of PMOS gain, which has received less attention. In this letter, we describe the warping phenomena which is responsible for the gain seen in [110] uniaxially stressed PMOS devices on [100] orientated wafers. We also demonstrate that shear uniaxial stress in PMOS is better suited to MOSFET applications than biaxial stress as it is able to maintain gain at high vertical and lateral fields.

The technologically important question of whether the reduced density of electron states (DOS) for scattering in one-dimensional (1D) wire transport devices gives an advantage over the planar metal–oxide–semiconductor field-effect-transistor (MOSFET) for electron mobility is assessed by simulations. We self-consistently solve the Schrodinger–Poisson equations to calculate phonon-limited electron mobility in a multisubband cylindrical Si gated wire. We find that the benefit of reduced 1D DOS is offset by an increased phononscattering rate due to increased electron–phonon wave function overlap and results in a degraded mobility in narrow wires. The applied gate bias voltage and the wire size control the transition from wire geometry to surface field-dominated confinement. The size scale for this 1D to two-dimensional (2D) transition is also found to be surprisingly small: A wire with a 75 A radius has an essentially 2D DOS and has a 2D mobility that is degraded from the planar (100) MOSFET due to the anisotropy of the inversion mobility in different Si crystallographic planes.

For the past 40 years, relentless focus on Moore's Law transistor scaling has delivered ever-improving CMOS transistor density. This paper discusses architectural and materials options which will contribute to the ultimate CMOS device. In addition, the paper reviews device options beyond the ultimate CMOS device.

This paper summarizes the electrostatics and performance of III–V field effect transistors including thin body planar MOSFETs, 3-D tri-gate MOSFETs, and Tunneling FETs (TFETs). The electrostatics of the III–V devices is shown to improve from thick body planar to thin body planar and then to 3-D tri-gate. Beyond the MOSFET structures, sub-threshold slope (SS) steeper than 60 mV/decade has been demonstrated in III–V TFETs. These III–V devices, especially the 3-D tri-gate MOSFET and TFET, are viable options for future ultra low power applications.

This work demonstrates the steepest subthreshold swing (SS < 60mV/decade) ever reported in a III–V Tunneling Field Effect Transistor (TFET) by using thin gate oxide, heterojunction engineering and high source doping. Owing to a lower source-to-channel tunnel barrier height, heterojunction III–V TFETs demonstrate steeper subthreshold swing (SS) at a given drain current (I D ) and improved drive current compared to the homojunction III–V TFETs. Electrical oxide thickness (EOT) scaling and increased source doping in tandem with tunnel barrier height reduction are shown to greatly improve the SS of the III–V TFETs and increase I D by more than 20X.

In this work, non-planar, multi-gate InGaAs quantum well field effect transistors (QWFETs) with high-K gate dielectric and ultra-scaled gate-to-drain and gate-to-source separations (L SIDE ) of 5nm are reported for the first time. The high-K gate dielectric formed on this non-planar device structure has the expected thin TOXE of 20.5A with low J G , and high quality gate dielectric interface. The simplified S/D scheme is needed for the non-planar architecture while achieving significant reduction in parasitic resistance. Compared to the planar high-K InGaAs QWFET with similar T OXE , the non-planar, multi-gate InGaAs QWFET shows significantly improved electrostatics due to better gate control. The results of this work show that non-planar, multi-gate device architecture is an effective way to improve the scalability of III–V QWFETs for low power logic applications.

In this paper, we present extensive reliability characterization results for a novel dual gate 45nm HK+MG technology. BTI, HCI and TDDB degradation modes on the Logic and I/O transistors are studied and excellent reliability is demonstrated. Emphasis is placed on the importance of process optimizations to support robust I/O transistors while maintaining the high performance and reliability of Logic transistors. Monitoring of reliability for HVM and collateral reliability are also addressed.

In this paper for the first time, the logic performance of Schottky-gate In 0.7 Ga 0.3 As QWFETs is measured and evaluated against that of advanced Strained Si MOSFETs from Vcc = 0.5 to 1.0V. The QWFET is shown to have measured drive current gain over the Si MOSFET for the entire Vcc range. Effective velocity (V eff ) of the QWFET exhibits 4.6X–3.3X gain over the Si MOSFET. The high V eff enables 65% intrinsic drive current gain at V CC = 0.5V and 20% gain at V CC = 1.0V for the In 0.7 Ga 0.3 As QWFET over that of Strained Si, despite 2.5x lower charge density.

Simulation approaches used in Intel to evaluate the applicability of new devices and materials for future microprocessor technologies are reviewed. Examples discussed include the evaluation of highly stressed materials, III -V HEMT devices, and carbon nanoribbons. The techniques employed are similar to those used in the research community, but focused on efficient evaluation within a versatile infrastructure that works for both development and research.

For the first time, the performance impact of (110) silicon substrates on high-k + metal gate strained 45 nm node NMOS and PMOS devices is presented. Record PMOS drive currents of 1.2 mA/um at 1.0 V and 100 nA/um Ioff are reported. It will be demonstrated that 2D short channel effects strongly mitigate the negative impact of (110) substrates on NMOS performance. Narrow width (110) device performance is shown and compared to (100) for the first time. Device reliability is also reported showing no fundamental issue for (110) substrates.

In this paper, we present extensive breakdown results on our 45nm HK+MG technology. Polarity dependent breakdown and SILC degradation mechanisms have been identified and are attributed gate and substrate injection effects. Processing conditions were optimized to achieve comparable TDDB lifetimes on HK+MG structures at 30% higher E-fields than SiON with a reduction in SILC growth. Extensive long-term stress data collection results and a change in voltage acceleration are reported.

Device simulation needs are growing more diverse and it is difficult for traditional simulators to satisfy them while maintaining usability, maintainability, speed, and robustness. The Modular Device Simulator (MDS) is a completely new simulator framework that addresses this problem by providing simulation building blocks within a dynamic, runtime-configurable framework driven by a scriptable input parser. This flexible framework allows MDS to be applied to a wide range of problems that traditionally would have been handled by many independent codes. MDS has been applied to the 45 nm node and beyond, including advanced applications such as Schrodinger/drift-diffusion and non-equilibrium Green’s function (NEGF).

The onset of localized conduction in TaOx- and TiOx-based resistive switching devices during forming has been characterized. The novel temperature and voltage dependencies of forming times were extracted with pulsed forming experiments that spanned five orders of magnitude in time and showed three different regimes of electroforming. A universal field-induced-nucleation theory which included self-heating effects was used to explain a strong reduction in forming voltage with increasing forming time over all observed regimes of electroforming. It was shown that the effective activation energy for the incubation time changes inversely proportional with the electric field. A diameter of the volatile filament that precedes forming was estimated at ∼1 nm.

The electronic and vibrational properties of carbon nanoribbons (CNRs) are analyzed and compared to carbon nanotubes (CNTs). Transport properties are analyzed from the perspective of use in an FET device. The required sizing and consequent processing requirements are discussed. The overall properties of the CNRs and CNTs are found to be similar, with the primary difference being the more restrictive size vs. bandgap behavior of the CNRs.

For the first time, we show with simulation that the use of a metal gate/high-k stack offers improved mobility over polysilicon/high-k gates stacks while maintaining decreased gate leakage compared to conventional SiO/sub 2/ stacks, thus allowing high-performance transistor scaling to continue.

This paper presents an integrated approach to modeling front end stress which has been used to investigate the main sources of stress in advanced logic technologies and how they can be used to improve device performance. The approach is illustrated with the evaluation of several technologically important stress options.

We have developed a quantum anisotropic transport model for holes which, for the first time, allows mobility to be studied under both uniaxial and arbitrary stress in PMOS inversion layers. The anisotropic bandstructure of a 2D quantum gas is computed from a 6-band stress dependent k.p Hamiltonian. Our unique momentum-dependent scattering model also captures the anisotropy of scattering. A comprehensive study has been performed for uniaxial stress, biaxial stress, and their nonlinear interactions. The results are compared with device bending data and piezoresistance data, showing very good agreement.

We integrate a strained Si channel with HfO/sub 2/ dielectric and TiN metal gate electrode to demonstrate NMOS transistors with electron mobility better than the universal mobility curve for SiO/sub 2/, inversion equivalent oxide thickness of 1.4 nm (EOT=1 nm), and with three orders of magnitude reduction in gate leakage. To understand the physical mechanism that improves the inversion electron mobility at the HfO/sub 2//strained Si interface, we measure mobility at various temperatures and extract the various scattering components.

A hierarchical, model-based understanding of the key physical effects underlying stress-induced device performance gain is presented, focusing on the large gains seen for uniaxial PMOS stress conditions and the vertical stress impact on NMOS gain.

Direct bandgap transition engineering using stress, alloying, and quantum confinement is proposed to achieve high performing complementary n and p tunneling field effect transistors (TFETs) based on group IV materials. The critical tensile stress for this transition decreases in Ge1−xSnx for Sn content 0≤x≤0.068, calculated with the Nonlocal Empirical Pseudopotential method. Direct sub eV bandgap leads to high ON current in both n and p Ge and Ge1−xSnx TFETs, simulated using the sp3d5s*-SO model. Ge and Ge1−xSnx show an advantage over III-V p TFETs achieving steep subthreshold operation, which is limited in III-V devices by their low density of electron states.

The hole surface roughness and phonon limited mobility in the silicon 〈100〉, 〈110〉, and 〈111〉 square nanowires under the technologically important conditions of applied gate bias and stress are studied with the self-consistent Poisson-sp3d5s*-SO tight-binding bandstructure method. Under an applied gate field, the hole carriers in a wire undergo a volume to surface inversion transition diminishing the positive effects of the high 〈110〉 and 〈111〉 valence band nonparabolicities, which are known to lead to the large gains of the phonon limited mobility at a zero field in narrow wires. Nonetheless, the hole mobility in the unstressed wires down to the 5 nm size remains competitive or shows an enhancement at high gate field over the large wire limit. Down to the studied 3 nm sizes, the hole mobility is degraded by strong surface roughness scattering in 〈100〉 and 〈110〉 wires. The 〈111〉 channels are shown to experience less surface scattering degradation. The physics of the surface roughness scattering dependence...

Design for Manufacturability (DFM) is a phrase that often accompanies discussion of layout optimization for lithography process effects, particularly Optical Proximity Correction (OPC). In an environment where process technology and circuit design are developed together, many other process-layout co-optimization strategies can be investigated. In this paper we discuss physical modeling to enable co-optimization strategies from a device performance point of view by examining layout-induced variation in front-end manufacturing processes used to engineer transistor strain and dopant diffusion/activation.

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Electronic properties of graphene (carbon) nanoribbons are studied and compared to those of carbon nanotubes. The nanoribbons are found to have qualitatively similar electron band structure which depends on chirality but with a significantly narrower band gap. The low- and high-field mobilities of the nanoribbons are evaluated and found to be higher than those of carbon nanotubes for the same unit cell but lower at matched band gap or carrier concentration. Due to the inverse relationship between mobility and band gap, it is concluded that graphene nanoribbons operated as field-effect transistors must have band gaps