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It has been a mere 130 years since the first widely known wireless telegraphy apparatus was demonstrated by Guglielmo Marconi, transmitting radio signals to a distance of about 2.4 km. In today’s world, as illustrated by , we are using a plethora of radios for an ever-increasing number of different applications. In fact, observing the data rate of wireless standards published by bodies like the 3rd Generation Partnership Project (3GPP) and the Wi-Fi alliance , , shown in , it can be readily seen that they increase by an order of magnitude every five years. [ABSTRACT FROM AUTHOR]

The world’s first 5-carrier aggregation (CA) supporting digital-intermediate frequency (IF) receiver (RX) to support 5G sub-6 GHz new radio (NR) and CA/E-UTRA NR dual connectivity (CA/EN-DC) maintaining 2G and 3G in 14-nm FinFET CMOS technology is presented. Three digital-IF RXs with a shared local oscillator-phase-locked loop (LO-PLL) are integrated for supporting inter-/intra-band 5-CA to reduce power consumption and area of the massive number of RX paths. The RX features nine single-ended low-noise amplifiers (LNAs) with low/mid/high band (L/M/HB) characteristics. It achieves noise figure (NF) of 1.5 dB with 18 dB external LNA gain and +7.6-dBm out-of-band (OOB) input intercept point 3 (IIP3), and input intercept point 2 (IIP2) calibration is not required thanks to IF planning. The RX achieves an error vector magnitude (EVM) of 2.5% by intra-4CA for B1 LTE10MHz and LTE20MHz in one single RX path, as well as inter-3CA for B3, B5, and B7 long-term evolution (LTE) 20 MHz with a shared LO-PLL. The estimated power saving by sharing a single LO-PLL is 17% compared to 3-CA RXs with three separate LO-PLLs. [ABSTRACT FROM AUTHOR]

In this work, a novel asymmetric T/R switch is proposed. The operating principle and design equations of the proposed T/R switch topology are presented. Based on the proposed circuit topology, an X‐band asymmetric T/R switch is designed in 0.18‐µm CMOS. From 9 to 11 GHz, the measured isolation is higher than 32 dB and the measured insertion loss is less than 1.87 dB for the TX mode. At 10 GHz, the measured TX‐mode IP1dB$I\!P_\mathrm{1dB}$ is higher than 36 dBm. [ABSTRACT FROM AUTHOR]

We present a broadband parallel-combined compact Doherty power amplifier (PA) in a 28-nm bulk complementary metal–oxide–semiconductor (CMOS) device technology for fifth-generation (5G) millimeter-wave (mm-Wave) frequency band (n257, n258, and n261) applications. The proposed Doherty PA has a single transformer (TF)-based output matching network and an equivalent quarter-wavelength line placed between the carrier and peaking amplifiers, absorbing transistors’ output parasitic capacitances. Therefore, the Doherty PA occupies a very small die area and has a wide bandwidth characteristic compared with the conventional Doherty PA output matching network topologies (e.g., parallel- and series-combined Doherty PA output matching networks). The two-stage differential Doherty PA is implemented, which shows a saturation output power ($P_{\mathrm {OUT}}$) of >18.8 dBm and a peak power-added efficiency (PAE) of >30% at 27 GHz. It also exhibits a linear $P_{\mathrm {OUT}}$ of 12.4 dBm and an average PAE of 20.2% for 100 MHz 5G NR signal ($P_{\mathrm {OUT}}$ of 11.4 dBm and PAE of 18.1% for 8 $\times $ 100 MHz carriers) at the EVM of −25 dB. Over the frequency range of 24.5–29.5 GHz, the PA achieves a linear $P_{\mathrm {OUT}}$ of >11.2 dBm and a PAE of >14.5% (drain efficiency >20.8%). This PA occupies 640 $\mu \text{m}\,\,\times $ 250 $\mu \text{m}$ (core only) and is successfully integrated into a 32-channel RF phased-array transceiver IC for the first time. The IC die area is 10.2 mm $\times $ 6.4 mm and consumes about 120 mW per channel at $P_{\mathrm {OUT}}$ of 10.0 dBm. [ABSTRACT FROM AUTHOR]

A new millimeter-wave (mm-wave) fully-integrated 0.18- $\mu \text{m}$ BiCMOS frequency division duplex (FDD) transmit–receive (T/R) front-end module with internal power amplifier (PA) and low noise amplifier (LNA) is reported. It employs an active circuit to cancel the transmitter (TX) signal leaking into the receiver (RX). The T/R module provides 43.6 dB isolation between the PA output and LNA input at 29 GHz and 9.5 dB average noise figure (NF) over 27–29 GHz on the entire RX path. At 29 GHz, the T/R module has 13.8 and 10.6 dB gain on the RX and TX path, respectively. A design methodology is also presented for maximum isolation and optimum NF. It occupies a small area of 2 mm2. [ABSTRACT FROM AUTHOR]

This article describes the design and implementation of a hybrid in-building navigation system. The word hybrid has a twofold meaning in this case. On the one hand, it refers to the use of two tracking methods: demanding (beacons) and not requiring an electronic device (radio tomography imaging). On the other hand, it specifies several commercial wireless communication protocols that make up the presented system. Ultimately, the network created in this way will be designed to provide the user with location and navigation services with increased accuracy and reliability. The text describes both the topology of created networks, methods of communication between devices and their hardware layer, as well as the effects of work resulting from the actual test object.

Digitizing RF signals using few bit ADCs can provide system advantages in terms of reduced power dissipation, wider sampling bandwidth, and decreased demand for digital throughput. The diversity of established applications based on few bit ADCs, together with the recent surge of interest in the topic for 5G wireless communications and millimeter-wave radar, has created a need for practical design guidance governing their use in general RF systems. This paper, therefore, summarizes the state-of-the-art in few bit ADCs, comparing the dynamic range considerations involved with those of conventional RF receiver design. A simple analytic model for the monobit ADC is extended to multiple bits. Parametric analysis, independent of sampling considerations and system-specific signal processing, is used to illustrate the variation in the ADC output signal-to-noise-and-distortion ratio (SNDR) versus both the number of quantization bits and the input signal-to-noise ratio (SNR). At low and negative input SNR, increasing ADC resolution beyond 3-4 bits yields little advantage in output SNDR. Experiment confirms analytic predictions for the specific conditions under which the loss of signal fidelity due to quantization can be made negligible. In addition, parametric analysis of two-tone intermodulation distortion shows clear disadvantages to quantizing with

A modified cross-coupling low-triggering dual-polarity silicon controlled rectifier (m-CLTdSCR) for on-chip electrostatic discharge (ESD) protection is developed. Cross-coupling mechanism can effectively reduce the trigger voltage of the proposed structure. A lower leakage is achieved by replacing NMOS with PMOS and changed connection, and this also effectively reduces the parasitic capacitance of m-CLTdSCR between anode and cathode. The new structure shows low-triggering voltage ~3.46 V, low leakage ~0.46 nA under normal operation condition, and low parasitic capacitance ~190 fF at zero bias. As such, the proposed m-CLTdSCR is an attractive device for radio frequency integrated circuits (RFICs) ESD protection. [ABSTRACT FROM AUTHOR]

This work reports a monolithic RF front-end module integrating bulk acoustic wave (BAW) filters, Lamb acoustic wave filters, and electronic RF silicon-on-insulator (RFSOI) switches to deliver single-chip multiband RF front-end module (RF-FEM) manufactured on commercial 200mm RF silicon-on-insulator (RFSOI) foundry technology. BAW and Lamb filters built in the same chip and within the same process enable multiband operation. Vertical System-on-Chip (SoC) integration of MEMS and RFSOI components contributes to footprint reduction up to 50%, compared to system-in-package (SiP) modules, and reduces the integration and design complexity of the modules. At its current state of development, this technology is suitable for diversity receive modules (DRX) for 4G/LTE and 5G bands. Extensive characterization results and case studies demonstrate the robustness of the integrated platform. Further productization of this technology will enable the next generation of hundred-filter 5G sub-6GHz RF-FEMs. [2020-0304] [ABSTRACT FROM AUTHOR]

For wideband frequency-agile radio frequency (RF) integrated circuits, tunable components are essential. It has been a great challenge in RF electronics to utilize a magnetic tunable inductor for ultrawideband applications. This letter demonstrates an electrically tunable RF inductor encompassing a broad range of frequencies from 4 to 20 GHz. This is achieved by integrating domain-patterned Permalloy of various thicknesses, such as 20, 60, and 92 nm. There is a performance boost of the inductor, and a tunable inductor is achieved by applying dc current. Experimental results show that amongst all the Permalloy patterns, $11\,\mu\text{m}\times 13\,\mu\text{m}$ provides the highest inductance tunability of 15.8% at 20 GHz for 60 nm patterns, 10.8% at 15.1 GHz for 92 nm, and 4.3% at 15.7 GHz for 20 nm. This is the highest inductance tunability obtained so far for spiral inductors integrated with 60 nm Permalloy patterns using the dc bias method. The 15.8%, 10.8%, and 4.3% inductance tunability provides 8%, 5.7%, and 2.1% frequency tuning correspondingly. [ABSTRACT FROM AUTHOR]

In this letter, a frequency-tunable rectifier in the $C$ -band designed by a hybrid semiconductor integrated circuit (HySIC) concept is proposed. A GaAs monolithic microwave integrated circuit (MMIC) and a Si radio frequency integrated circuit (RFIC) were utilized as the HySIC configuration in the rectifier design. For the purpose of initial confirmation of this design validity, the GaAs and Si chips were fabricated and packaged onto the copper tungsten plate with gold plating. As measured results, frequency-tunable range from 3.82 to 4.55 GHz was measured. Maximum radio frequency (RF)–direct current (dc) conversion efficiency and output dc power in the measured power range from −10.0 to 17.8 dBm were 28.7% and 17.3 mW, respectively. [ABSTRACT FROM AUTHOR]

With the development of modern weapon techniques, radio frequency integrated technology has attracted widespread attention as a key technology to improve the informationalised level of missiles. Radar and communication are two typical electronic types of equipment, and their integration can support and promote the development of radio frequency integrated technology. In this study, experimental verification of an integrated radar–communication system is carried out. Firstly, the key technologies to achieve radar–communication integration are theoretically analysed. The solutions of the key issues, including signal separation, time synchronisation and frequency synchronisation, are proposed. Furthermore, a radar–communication demo is implemented and the experimental verification is carried out here to verify the feasibility of the proposed methods.

Antenna-in-package (AiP) technology, in which there is an antenna (or antennas) with a transceiver die (or dies) in a standard surface-mounted device, represents an important antenna and packaging technology achievement in recent years. AiP technology has been widely adopted by chipmakers for 60-GHz radios and gesture radars. It has also found applications in 77-GHz automotive radars, 94-GHz phased arrays, 122-GHz imaging sensors, and 300-GHz wireless links. It is believed that AiP technology will also provide elegant antenna and packaging solutions to the fifth generation and beyond operating in the lower millimeter-wave (mmWave) bands. Thus, one can conclude that AiP technology has emerged as the mainstream antenna and packaging technology for various mmWave applications. This article will provide an overview of the development of AiP technology. It will consider antennas, packages, and interconnects for AiP technology. It will show that the antenna choice is usually based on those popular antennas that can be easily designed for the application, that the package choice is governed for automatic assembly, and that the materials and processes choices involve tradeoffs among constraints, such as electrical performance, thermal–mechanical reliability, compactness, manufacturability, and cost. This article also shows a probe-based setup to measure mmWave AiP impedance and radiation characteristics. It goes on to give AiP examples implemented, respectively, in a low-temperature co-fired ceramic, an embedded wafer level ball grid array process, and a high-density interconnect processes. Finally, this article will summarize and present some recommendations on research topics to further the state of the art of AiP technology. [ABSTRACT FROM AUTHOR]

This letter presents an unprecedented stamped metal antenna-in-package (AiP) concept for millimeter-wave multiple-input–multiple-output (MIMO) and phased array applications. The stamped metal antenna containing an aperture dually functions as an efficient heat sink. Moreover, the presented antenna topology can be mass-produced using a stamping technology, which is widely used for conventional heat sinks. The ground wall of the proposed antenna encompassed by the dielectric substrate, which is thermodynamically equivalent to a cooling medium, is connected to the shield structures to guide the convection heat emitted by the radio frequency integrated circuits (RFICs) and discharges this heat into free space. Details of the proposed AiP topology are discussed, and the parametric effects of the key design factors are quantitatively analyzed. To verify the proposed AiP, the optimized design is fabricated using standard printed circuit board (PCB) and press technology. The fabricated 1 × 8 subarray features an impedance bandwidth of 700 MHz with a center frequency of 28.5 GHz and a measured gain of 13.78 dBi. Computational fluid dynamics results ascertain that the proposed stamped metal AiP effectively discharges the heat emission generated from the RFICs. [ABSTRACT FROM AUTHOR]

With the development of modern weapon techniques, radio frequency integrated technology has attracted widespread attention as a key technology to improve the informationalised level of missiles. Radar and communication are two typical electronic types of equipment, and their integration can support and promote the development of radio frequency integrated technology. In this study, experimental verification of an integrated radar–communication system is carried out. Firstly, the key technologies to achieve radar–communication integration are theoretically analysed. The solutions of the key issues, including signal separation, time synchronisation and frequency synchronisation, are proposed. Furthermore, a radar–communication demo is implemented and the experimental verification is carried out here to verify the feasibility of the proposed methods. [ABSTRACT FROM AUTHOR]

This study reports the design and analysis of novel step structure RF micro‐electromechanical system (MEMS) switch for low pull‐in voltage, low insertion loss and high isolation by using uniform single meander. The central beam of the membrane is designed with 0.5 µm lower than the side beams to form a step‐down structure which reduces the pull‐in voltage. Stress analysis, electromechancial, switching time, quality factor and RF analysis have done to understand the behavioural characteristics of the proposed step‐down switch. The analysis has been carried out for different beam and dielectric materials among them switch with gold material exhibits low pull‐in voltage of 4.7 V, low insertion loss <1 dB and high isolation of −38.3 dB at 28.2 GHz for silicon nitride. The switch also shows good quality factor of 0.95 for gold material along with high capacitance ratio of 132. The upstate capacitance of 56.8 pF contributes low return loss and made the switch to transmit the signal up to 26.2 GHz and provides 7.2 pF of downstate capacitance to produce high isolation at 26.2 GHz which is efficiently used for K‐band satellite applications. [ABSTRACT FROM AUTHOR]

A 120 GHz on-board chip-to-chip wireless link is presented. A printed circuit board-based, highly directive Y-shaped open-ended microstrip antenna that radiates electric fields perpendicular to the ground plane is used. To realize a real chip-to-chip environment, the antenna is connected to the radio frequency integrated circuit (RFIC) using a bond-wire. The distance was set to 20 and 50 mm. The measured peak S21 for the 20 and 50 mm wireless link was –28.7 and –35.6 dB. The measured 3 dB bandwidth was 22 GHz for the 20 mm case and 20 GHz for the 50 mm case. [ABSTRACT FROM AUTHOR]

This paper describes the design and implementation of a scalable $W$ -band phased-array system, with built-in self-alignment and self-test, based on an RFIC transceiver chipset manufactured in the TowerJazz 0.18- $\mu \text{m}$ SiGe BiCMOS technology with $f_{T}/f_{\text {MAX}}$ of 240/270 GHz. The RFIC integrates 24 phase-shifter elements (16TX/8RX or 8TX/16RX) as well as direct up- and down-converters, phase-locked loop with prime-ratio frequency multiplier, analog baseband, beam lookup memory, and diagnostic circuits for performance monitoring. Two organic printed circuit board (PCB) interposers with integrated antenna sub-arrays are designed and co-assembled with the RFIC chipsets to produce a scalable phased-array tile. Tiles are phase-aligned to one another through a daisy-chained local oscillator (LO) synchronization signal. Statistical analysis of the effects of LO misalignment between tiles on beam patterns is presented. Sixteen tiles are combined onto a carrier PCB to create a 384-element (256TX/128RX) phased-array system. A maximum saturated effective isotropic radiated power (EIRP) of 60 dBm (1 kW) is measured at boresight for the 256 transmit elements. Wireless links operating at 90.7 GHz using a 16-QAM constellation at a reduced EIRP of 52 dBm produced data rates beyond 10 Gb/s for an equivalent link distance in excess of 250 m. [ABSTRACT FROM AUTHOR]

In this paper, a class of balanced wideband phase shifters with good filtering property and common-mode (CM) suppression is proposed, synthetically designed, and implemented. Unlike the conventional coupled-line reference branch one, the proposed balanced phase shifter has its T-shaped structure in both of main and reference branches, so as to achieve superior passband selectivity and CM rejection simultaneously. The synthesis method is then presented to design the proposed balanced wideband phase shifters with the prescribed phase shift value, passband ripple, maximum phase deviation, and fabricated bandwidth. The 30°, 45°, 60°, 75°, and 90° balanced phase shifters are theoretically designed and demonstrated. To validate the design method, two prototypes with different fractional bandwidths (FBWs) and phase shift values (Case 1: FBW = 66.7%, typical phase shift value is 30°; Case 2: FBW = 55.6%, typical phase shift value is 90°) are designed, fabricated, and measured. The synthesized, simulated, and measured results are found in good agreement with each other. [ABSTRACT FROM AUTHOR]

Abstract Mixed signal on-chip solutions for space applications and high energy physics experiments require high voltage RF-LDMOS transistors with sufficient ruggedness against ionizing radiation and single event burnout. We report on a novel hardening by design approach for radiation tolerant integrated RF NLDMOS transistors confirmed by single event burn out (SEB) and total ionizing dose (TID) radiation tests. In order to substantially decrease TID induced leakage currents the shallow trench isolation (STI) of MOS transistors was replaced by narrow junction isolated regions. For a significant increase of the SEB onset voltage a cascode arrangement consisting of an isolated NMOS and NLDMOS was chosen. The floating NMOS-drain/NLDMOS-source node in the cascode arrangement is always reverse biased which efficiently avoids a turn-on of the parasitic npn bipolar transistor. The rad-hard isolated NMOS/NLDMOS cascode features a breakdown voltage BVDS > 50 V, a maximum cut off frequency f T = 5 GHz and a maximum oscillation frequency f MAX = 14 GHz. In comparison with standard NLDMOS transistors the isolated NMOS/NLDMOS cascode device shows an increase of the SEB onset voltage from 14V to 30V at a linear energy transfer LET of 67.7 MeVcm2/mg and a negligible increase of source drain leakage currents up to a TID of 1.5 Mrad after irradiation with a 60Co source. [ABSTRACT FROM AUTHOR]

This Letter presents for the first time radio frequency (RF) reliability studies of fully integrated CMOS RF integrated circuits (RFICs) for next generation wireless communication applications involving conformal bodies where wireless communication RFICs will be embedded on ultra‐thin flexible packages. As a test case, RF characteristics of a CMOS voltage‐controlled oscillator (VCO) chip with multiple die‐substrate thicknesses were measured and results are analysed. The CMOS VCO chip under study was designed and fabricated using 180 nm RF‐CMOS process. Reliability of performances of the VCO chips are characterised and results are compared before and after die thinning from 250 to 50, 35, and 25 μm, respectively. Critical RF performance parameters such as frequency of oscillation, output power, and phase noise are considered for analysis, respectively. All the dies are placed face‐up for probing on the top of a metal chuck with ground connection inside the micro‐chamber of a probe station. While the deviations of frequency and output power are within ±1% and ±1 dB, respectively, due to the die thinning affect, the phase noise deteriorations are observed significant. It confirms the well‐known fact of phase noise sensitiveness to the substrate thickness due to the leakage and SOI CMOS is discussed widely to minimise these parasitic effects. [ABSTRACT FROM AUTHOR]

This paper proposes a novel and iterative way to conduct model order reduction (MOR) of linear equivalent circuit models (ECMs) without the use of a state-space representation as a surrogate model. The result is an ECM with a reduced total number of circuit elements but same system behavior. The proposed method is as follows: first, the original ECM is decomposed into smaller subcircuits after which a variance-based global sensitivity analysis by means of polynomial chaos expansion is conducted in order to extract the Sobol indices which measure the relative impact of the circuit elements. The least influential ones are then removed by either shorting them or replacing them by an electric open. The frequency responses of the resulting reduced circuits are then fitted against the original frequency response through nonlinear least squares optimization and by subsequently updating the element values. As opposed to the traditional MOR techniques from systems theory, the proposed approach operates on the ECM themselves directly. Thus, it not only offers additional physical insight into the system at any iteration step but also inherently leads to reduced-order models that are at once stable, causal, and passive. This makes the approach especially useful for practical electromagnetic compatibility problems and analysis. In the following, this novel approach is first described in detail and then applied to different test cases. Finally, a discussion of its limitations will be given. [ABSTRACT FROM AUTHOR]

Increasingly, people around the world embrace the benefits provided by smart phones, smart cars, and smart homes. The key difference between smart phones and traditional mobile phones is the user-defined functionality that enables individuals to transform their phones into music players, movie theaters, or personal workstations. Smart cars with video sensors, lidar sensors, or even millimeter-wave (mm-wave) radar may be autonomously driven. When more and more user-defined functions/sensor capabilities are built into RF integrated circuits (RFICs), they are known as smart RFICs. [ABSTRACT FROM AUTHOR]

We describe the history of New Japan Radio Co. Ltd., (NJR) and our continuing presence in the business of manufacturing gallium arsenide radio frequency (GaAs RF) front-end devices. We also explain how our company survived and prospered despite the changing markets. We compare NJR strategies with those of competing RF integrated circuit (RFIC) manufacturers in Japan and briefly describe the hetero-junction field-effect transistor technology, which plays a key role in the success of NJR’s RFIC business. We present some of the manufacturing and performance data to show how we improved the wafer process. These unique underlying technologies have enabled the implementation of unique circuit types, which are rarely seen in conventional GaAs ICs. [ABSTRACT FROM AUTHOR]

We studied aerosol jet printing on flexible substrates for wearable and flexible electronic devices. First, we investigated the electrical conductivity of aerosol jet printed silver layers at different temperatures. An electrical conductivity up to 60% of bulk Ag was measured after sintering at 140 °C on a hot plate. Higher conductivities became possible with higher sinter temperatures. The printed ink showed a surprisingly high flexibility. Transmission lines were printed on flexible substrates [Kapton and Rogers liquid crystal polymer (LCP) foils], and the performance was measured up to 110 GHz. The coplanar waveguide transmission lines demonstrated insertion losses of 0.366 dB/mm for LCP and 0.546 dB/mm for Kapton foils at 110 GHz. [ABSTRACT FROM AUTHOR]

Balanced homodyne detector (BHD) that can measure the field quadratures of coherent states has been widely used in a range of quantum information technologies. Generally, the BHD tends to suffer from narrow bands and an expanding bandwidth behavior usually traps into a compromise with the gain, electronic noise, and quantum to classical noise ratio, etc. In this paper, we design and construct a wideband BHD based on radio frequency and integrated circuit technology. Our BHD shows bandwidth behavior up to 1.2 GHz and its quantum to classical noise ratio is around 18 dB. Simultaneously, the BHD has a linear performance with a gain of 4.86 k and its common mode rejection ratio has also been tested as 57.9 dB. With this BHD, the secret key rate of continuous-variable quantum key distribution system has a potential to achieve 66.55 Mb/s and 2.87 Mb/s, respectively, at the transmission distance of 10 and 45 km. Besides, with this BHD, the generation rate of quantum random number generator could reach up to 6.53 Gb/s. [ABSTRACT FROM AUTHOR]

The authors present two new metal oxide semiconductor field effect transistor (MOSFET)‐only second‐order voltage and transadmittance‐mode band‐pass filters (BPFs) employing only five transistors without using any passive elements such as a resistor, a capacitor, and an inductor. As a result, both proposed circuits possess low‐power consumption and occupy small chip area. The first proposed filter enjoys low output impedance and offset cancellation for voltage‐mode operation while the second proposed filter has low supply voltage. The centre frequency of both proposed filters can be electronically tuned by varying biasing voltage. To demonstrate the performance of the proposed filters, effects of output transconductance of transistors have been investigated and equations of input referred noise have been obtained. Furthermore, fourth‐order voltage and transadmittance‐mode BPF which is derived the first proposed filter is presented and its simulation results are given. All proposed filters are laid‐out in the Cadence environment using Taiwan semiconductor manufacturing company (TSMC) 0.18 µm complementary metal oxide semiconductor (CMOS) technology parameters. The required chip area of the fourth‐order voltage and transadmittance‐mode band‐pass filter is 1100 μm2 and the power consumption is about 436 µW. [ABSTRACT FROM AUTHOR]

This brief aims at finding the most appropriate frequency of operation of an integrated harmonic oscillator in order to maximize its spectral purity. To achieve this, a simple, yet accurate, scalable model is developed for the LC tank, that tracks the dependence of the parasitics on the inductance value. Using an ultra-scaled CMOS digital technology as a case study, the frequencies around 5 GHz are singled out as the sweet spot to minimize the phase noise. [ABSTRACT FROM PUBLISHER]

Series‐connected rectenna associations are proposed to improve the harvesting performance of conventional rectenna circuits by recovering power from different directions. With an available input power of −20 dBm, post‐layout simulations evaluated the total output power of four series‐connected rectennas designed in Complementary Metal Oxide Semiconductor Fully Depleted Silicon On Insulator (CMOS FD‐SOI) 28 nm technology, to 14 µW at maximum power point (MPP), while the post‐layout simulation of a single rectenna yields 5 µW at the same input power level. However, the rectenna association performance may be significantly degraded when dealing with different input power levels among rectennas. Therefore, a passive bypass circuit has been added at the output of the series association to short‐circuit the weakest rectenna. The proposed design is cost‐effective since there is a negligible silicon penalty and no additional power losses. In the designed four series‐connected rectenna association, the total output power is 7 µW at MPP with the bypass circuit when the strongest and the weakest rectennas receive −20 and −35 dBm, respectively. Also, thanks to the bypass circuit, the efficiency of the rectenna association and the ratio of maximum achieved power are improved by, respectively, 10 and 20%. [ABSTRACT FROM AUTHOR]

Magnetic resonance imaging (MRI) is among the most important medical imaging modalities. Coil arrays and receivers with high channel counts (16 and more) have to be deployed to obtain the image quality and acquisition speed required by modern clinical protocols. In this paper, we report the theoretical analysis, the system-level design, and the circuit implementation of the first receiver IC (RXIC) for clinical MRI fully integrated in a modern CMOS technology. The dual-channel RXIC sits directly on the sensor coil, thus eliminating any RF cable otherwise required to transport the information out of the magnetic field. The first stage LNA was implemented using a noise-canceling architecture providing a highly reflective input used to decouple the individual channels of the array. Digitization is performed directly on-chip at base-band by means of a delta-sigma modulator, allowing the subsequent optical transmission of data. The presented receiver, implemented in a $\mathbf {{130}\,{nm}}$ CMOS technology, is compatible with MRI scanners up to $\mathbf {{10.5}\,{T}}$. It reaches sub- $\mathbf {{1}\,{dB}}$ noise figure for $\mathbf {{3- 7}\,{T}}$ MRI units and features a dynamic range up to $\mathbf {{81.9}\,{dB}}$ at a power consumption below $\mathbf {{240}\,{mW}}$ per channel, with an area occupation of $\mathbf {{22}\,{mm^2}}$ . Mounted on a small-sized printed circuit board (PCB), the receiver IC has been employed in a commercial MRI scanner to acquire in-vivo images matching the quality of traditional systems, demonstrating the first step toward multichannel wearable MRI array coils. [ABSTRACT FROM PUBLISHER]

With advancing process technologies and booming Internet of Things markets, millimeter-wave CMOS RFICs have evolved rapidly and been widely applied in recent years. The performance of CMOS RFICs is very sensitive to the chip layout, and a tiny variation of the microstrip length can cause a large impact to the circuit performance. This results in a time-consuming tuning process including much simulation effort for chip design, which becomes the major bottleneck for time to market. This paper introduces a progressive integer-linear-programming-based method consisting of two phases: 1) global layout generation and 2) iterative validation. In the global layout generation phase, we focus on the most critical constraints such as layout planarity and device connection relations to determine the topology of the final design. This provides a basis for constructing the accurate model in the iterative validation phase. The layouts generated by applying our method can satisfy very stringent routing requirements of microstrip lines, including spacing/noncrossing rules, precise length, and bend number minimization, within a given layout area. The resulting RFIC layouts excel in both performance and area with much fewer bends compared with the simulation-tuning based manual layout, while the layout generation time is significantly reduced from weeks to a few minutes. [ABSTRACT FROM AUTHOR]

Radio‐frequency integrated circuits (RFICs) design and fabrication require sets of skills that are professionally earned through years of hands‐on experiences in a developed industrial environment such as fabless design houses. Difficult design specifications, dynamic working environment, and tight deadlines in ruthless time cycles of design to mass production are all, but few examples that academia often fails to train young engineers to face. In general, no skill‐based education can be easily found for fresh graduates interested in a career in IC design. As part of an industry‐oriented graduate course in RFIC, students were introduced into industry design flow through lectures and major project assignments. The latter were selected to form an integrated design flow that ultimately leads to the design of a full RFIC. Students were offered to select design blocks as projects and were given specifications to meet, extracted from a transceiver architecture study. The outcome of the work showed an interesting trend of students starting their design in individual efforts, but later clustering together in team effort to match their designs together and to finish their tasks at the fictitious tape‐out deadline. [ABSTRACT FROM AUTHOR]

A semi‐passive charge‐sharing complex bandpass filter employing positive feedback technique is proposed to control bandwidth at different centre frequencies. In contrast to the previous arts, bandwidth can be changed independent of centre frequency without any rise in the number of clock phases and switches. Also, insightful continuous‐time model and block diagram of the proposed filter have been presented. The results of simulation carried out with 0.18 µm CMOS technology at 200 MHz reference frequency for centre frequencies of 10 and 20 MHz and bandwidth of 1, 3 and 7 MHz indicate the filter's ability to control the quality factor excellently. [ABSTRACT FROM AUTHOR]

The large signal operation of the bulk acoustic wave (BAW) resonators is characterized by the amplitude-frequency effect and the intermodulation effect. The measurement of these effects, together with that of the small signal frequency characteristic, are used in this paper for the parameter identification of the nonlinear circuit models developed previously by authors. As the resonator has been connected to the measurement bench by wire bonding, the parasitic elements of this connection have been taken into account, being estimated solving some electrical and magnetic field problems.

Digital RF transmitter architectures offer several advantages over conventional analog transmitters, including reduced area, reconfigurability, compatibility with scaling, and the ability to use highly efficient switching-class power amplifiers (PAs). However, the nonlinear transfer functions from the switch conductance to the output RF amplitude and phase of these switching-class PAs and the inherent interaction between I and Q paths in digital Cartesian architectures necessitate the use of 2-D digital predistortion (2D-DPD) for linearization. In this brief, we discuss the 2D-DPD of a class E/F\mathrm{odd} PA-based Cartesian RF-power-digital to analog converter (DAC) transmitter. The effects of parameters associated with the 2D-DPD such as the rotation of the static nonlinearity constellation, size of predistortion look-up tables (LUTs), and interpolation technique on system performance metrics such as error vector magnitude (EVM) and output power are discussed. We also investigate design tradeoffs related to output power, efficiency, and the effective number of bits in such transmitters. This brief is supported by measurement results from a watt-level 2.4-GHz 9-b Cartesian RF-power-DAC transmitter implemented in 65-nm CMOS. [ABSTRACT FROM AUTHOR]

Radio‐frequency (RF) circuits employing periodically gated switches can be difficult to characterise in the frequency domain because they are time variant. The time variance causes frequency mixing and makes impedances difficult to define. A new method of frequency‐domain analysis for periodic switching circuits is proposed in which a switch is represented by a matrix of admittance values. The columns of the admittance matrix correspond to voltage frequencies and the rows correspond to current frequencies, facilitating frequency translation effects in the circuit. The frequency domain is considered using a discretised set of harmonically related frequencies. The method is applied to the design and analysis of an RF switching mixer to demonstrate its advantages in calculating impedances and tuning the frequency response. [ABSTRACT FROM AUTHOR]

A generally applicable calibration technique for digitally reconfigurable self-healing radio frequency integrated circuits based on a hybrid of the Nelder-Mead and Hooke-Jeeves direct search algorithms is presented. The proposed algorithm is applied to the multiobjective problem of gain error and phase error minimization for a self-healing phase rotator test case. For the 8-D phase rotator calibration problem, we show that the proposed hybrid Nelder-Mead and Hooke-Jeeves calibration algorithm is capable of reducing the gain error and phase error of the phase rotator output to less than a maximum of 0.5 dB and 2°, respectively, relative to the chosen gain and phase targets. A 3-GHz self-healing phase rotator test chip was fabricated in a 45-nm silicon-on-insulator CMOS process, and the measured data were obtained to validate the performance of the proposed calibration algorithm. [ABSTRACT FROM PUBLISHER]

An ultra‐low‐power oscillator with 0.24 pJ/cycle energy efficiency is presented, suitable for nanowatt‐level energy harvesters. The sub‐pJ/cycle energy efficiency is comparable with the lowest energy per cycle costs of prior arts and is achieved by minimising short‐circuit current with a leakage‐based delay cell and minimising dynamic power consumption with a capacitively coupled stacked structure. The proposed oscillator is fabricated in 180 nm CMOS process. Under 2.2 V supply voltage, the energy per cycle is 0.24 pJ/cycle over a frequency range of 18.2–226 kHz. [ABSTRACT FROM AUTHOR]

Fully integrated high‐voltage pulse driver with low voltage supplies and low voltage switching signals is described. Using charge redistribution for the output drive significantly reduces switching losses in the load capacitors even with the high‐voltage output swing. The proposed circuit implemented with 0.18 µm HV LDMOS technology achieves 24–55% efficiency improvement for 20 k–1 MHz 29 V pulse generation with 1.2 and 3.3 V supply voltage. [ABSTRACT FROM AUTHOR]

This book covers almost every topic imaginable on radiofrequency integrated circuits (RFIC), provides examples as well as problems for students, and has a consistency of presentation that teachers, students, and researchers alike will appreciate. Almost all the examples and derivations originate from the author and based on fundamentals. The work of other researchers is cited to give the book a broad foundation, but this is not a collection of examples from the literature, which makes this book all the more useful for teachers. In 16 chapters and one appendix, Dr. Nguyen covers everything from the fundamentals of electromagnetics to systems. This book methodically goes through almost all aspects of RFICs in a way that is well thought out and easy to read. The lengthiest chapters are on transmission lines and amplifiers, while the shortest are on electromagnetics and stability. It is easier to point out what the book does not include than to itemize what it does. The book is primarily about complementary metal-oxide semiconductors (CMOSs) although GaAs circuits are mentioned. The chapter on stability discusses load pull and K factors but does not mention newer stability criteria such as the normalized determinant function, which is more relevant to multitransistor circuits. Any quibbles aside, this book covers a huge amount of ground in a well-developed manner and so is a very useful reference and textbook. [ABSTRACT FROM PUBLISHER]

Detectors play an important role in many communication systems such as delay locked loops, alias-locked loops [1], digital-microwave radio [2], clock-data recovery [3], [4], and phase-locked loops (PLLs) [5]. A phase frequency detector (PFD) is one of the mature detector circuit designs used to detect phase and frequency differences of input signals. Time-to-digital converter (TDC) blocks are a modern and emerging technique used to quantify these phase and frequency differences precisely. [ABSTRACT FROM PUBLISHER]

The three articles in this special section are dedicated to the research activities in the IEEE Microwave Theory and Techniques Society (MTT-S) Technical Committee Biological Effect and Medical Applications of Radio Frequency (RF) and Microwave (MTT-10). Specifically, this issue focuses on using microwave technologies in medical applications with practical scenarios. The research articles review developments in magnetic resonance imaging (MRI), microwave remote monitoring, and body phantom models for electromagnetic wave characterization. [ABSTRACT FROM PUBLISHER]

The two implementation choices for the baseband part of wireless radios are the application‐specific platforms (e.g. application‐specific integrated circuits (ASICs)) and the programmable processors (e.g. digital signal processors (DSPs)). An application‐specific instruction‐set processor (ASIP) is a customised processor that bridges the gap between the two platforms. In this work, a novel implementation of the signal processing part of an orthogonal frequency division multiplexing (OFDM) baseband processor using three ASIPs is presented. The ASIPs provide novel architectures for the symbol chain, including fast Fourier transform, channel estimation subsystem and synchronisation subsystem. This design provides a close to DSPs level of flexibility, making it suitable for supporting all the modes of a large number of OFDM standards. In the meantime, the system maintains a performance level comparable to ASICs. This is demonstrated by providing post‐layout results for 0.13 μm Taiwan semiconductor manufacturing company complementary metal‐oxide semiconductor technology. [ABSTRACT FROM AUTHOR]

This article discusses the benefits and challenges associated with the design of multi-function scalable phased arrays at millimeter wave frequencies. First, applications for phased arrays with tens to hundreds of elements are discussed. Existing solutions for scaling silicon-based phased arrays from microwave to terahertz frequencies are reviewed. The challenges and tradeoffs associated with multiple integration options for W-band phased arrays are analyzed, with special consideration given to packaging and antenna performance. Finally, a solution based on SiGe ICs and organic packages for a 64-element dual-polarized 94 GHz phased array is described, along with associated measurement results. [ABSTRACT FROM PUBLISHER]

A CMOS variable gain amplifier (VGA) based on a novel linear and tunable triode transconductor is presented. The proposed transconductor employs local negative feedback for linearisation controlling the drain voltage of the input transistors biased in the triode region. The new design is able to operate at low supply voltage and the stability is guaranteed. The transconductor features a 47.75 dB dc gain and a 4.23 MHz unity gain frequency with a power consumption of only 91 µA. To show the feasibility of the proposed transconductor, a VGA has been fabricated. Measurement results for a 0.13 µm CMOS design show a −3 dB bandwidth above 2.8 MHz and a third‐order harmonic distortion at 500 kHz below −46 dB over the whole gain range. The VGA exhibits a maximum power consumption of only 395 µW from a single 1.2 V supply. [ABSTRACT FROM AUTHOR]