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A Single Path Digital-IF Receiver Supporting Inter/Intra 5-CA With a Single Integer LO-PLL in 14-nm CMOS FinFET.

Authors :
Sung, Barosaim
Seok, Hyun-Gi
Kim, Jaekwon
Lee, Jaehoon
Jang, Taejin
Jang, Ilhoon
Kim, Youngmin
Yu, Anna
Jang, Jong-Hyun
Lee, Jiyoung
Bae, Jeongyeol
Park, Euiyoung
Lee, Sungjun
Lee, Seokwon
Kim, Joohan
Kim, Beomkon
Lim, Yong
Oh, Seunghyun
Lee, Jongwoo
Source :
IEEE Journal of Solid-State Circuits; Dec2022, Vol. 57 Issue 12, p3646-3655, 10p
Publication Year :
2022

Abstract

The world’s first 5-carrier aggregation (CA) supporting digital-intermediate frequency (IF) receiver (RX) to support 5G sub-6 GHz new radio (NR) and CA/E-UTRA NR dual connectivity (CA/EN-DC) maintaining 2G and 3G in 14-nm FinFET CMOS technology is presented. Three digital-IF RXs with a shared local oscillator-phase-locked loop (LO-PLL) are integrated for supporting inter-/intra-band 5-CA to reduce power consumption and area of the massive number of RX paths. The RX features nine single-ended low-noise amplifiers (LNAs) with low/mid/high band (L/M/HB) characteristics. It achieves noise figure (NF) of 1.5 dB with 18 dB external LNA gain and +7.6-dBm out-of-band (OOB) input intercept point 3 (IIP3), and input intercept point 2 (IIP2) calibration is not required thanks to IF planning. The RX achieves an error vector magnitude (EVM) of 2.5% by intra-4CA for B1 LTE10MHz and LTE20MHz in one single RX path, as well as inter-3CA for B3, B5, and B7 long-term evolution (LTE) 20 MHz with a shared LO-PLL. The estimated power saving by sharing a single LO-PLL is 17% compared to 3-CA RXs with three separate LO-PLLs. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
00189200
Volume :
57
Issue :
12
Database :
Complementary Index
Journal :
IEEE Journal of Solid-State Circuits
Publication Type :
Academic Journal
Accession number :
160620834
Full Text :
https://doi.org/10.1109/JSSC.2022.3212375