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A modular massively parallel computing (Modular-MPC) philosophy to image-related processing is discussed in this paper The approach is based on application-specific configurations of generic fine-grain Single Instruction stream operating on Multiple Data (SIMD) streams massively parallel computing modules to achieve high performance and maximal flexibility and programmability while remaining cost-effective. The need for a software architecture to allow programming such systems is highlighted and the implementations on current Modular-MPC systems are described. The experience with ASTRA, a Modular-MPC testbed system, in image related application development and system performance has led to a technology road-map using VLSI, MCM, and monolithic WSI technologies aiming at 'future proofing' of the Modular-MPC concept and systems achieving T (10/sup 12/) operations per second performance. This experience and progress are discussed together with the implementation of three image-related processing applications.

While WSI-based devices continue to be of particular interest for applications with severe performance, size, weight, power, cost, and reliability requirements, various implementation constraints in the past, including interconnect defect occurrences, have prevented their successful realization. This paper presents an investigation into defect and fault tolerant interconnect strategies for a representative WSI device, WASP (WSI Associative String Processor). >

It is argued that although it is not yet clear which of the two wafer scale integration (WSI) forms, monolithic or hybrid, will gain the lead to an enabling technology for second-generation massively parallel computers (MPCs), there are noticeably more backers for hybrid-WSI. The application requirements, implementation problems, and engineering issues of MPCs are discussed. In particular, the associative string processor (ASP) modules, which comprise building blocks for second-generation MPC configurations, are described. The progress reported in developing ASP modules is quantitatively extrapolated to other MPC implementations. >

Associative processing architectures as candidates for second-generation massive parallel computers (MPCs) are discussed. The authors outline the principle of operation of associative processors, and briefly review their development. They explore the associative string processor (ASP) architecture as a representative case study in the development of a second-generation MPC. >

A research project, in which various high-density interconnect (HDI) and wafer-scale integration (WSI) implementation variants of a common computer architecture, the associative string processor (ASP), are compared, is discussed. The ASP is a fault-tolerant and highly versatile massively parallel processor capable of sustaining high performance over a wide range of computationally intensive tasks and, unlike most other computer architectures, the ASP has been designed to exploit state-of-the-art microelectronic technology. The study indicates that, until the feasibility of WSI ASP technology has been proven, a 3-D HDI ASP seems to offer a cost-effective alternative technology for the development of highly compact massively parallel processors for aerospace and automotive applications. >

The WSI associative string processor (WASP), a massively parallel processor, implemented as a system-on-silicon, is discussed. The WASP is organized as a string of simple content-addressable associative processing elements (APEs), which achieves particularly high APE packing density and incorporates a highly flexible and compact inter-APE communications network on silicon. At the VLSI level the associative string processor architecture is already finding wide acceptance in a variety of applications areas. The integration of this architecture with the potential of wafer-scale integration (WSI) promises further significant decreases in size and weight production cost, and power dissipation, combined with improvements in performance and reliability. The WASP architecture and microelectronic implementation are described. The evolution of the WASP research program, the current WASP demonstrators, and the potential characteristics of a realistic WASP system are summarized. >

The associative string processor (ASP) is a homogeneous, reconfigurable, programmable massively parallel processor which offers step-function advantages in cost performance and application flexibility due to its unique architecture and its use of state-of-the-art microelectronics. The authors briefly describe the ASP architecture and its implementation and report the results of an evaluation of its applicability to image-processing tasks. In order to provide a realistic demonstration of the above-mentioned advantages, a set of independently defined tasks (viz. the Defense Advanced Research Projects Agency (DARPA) image-understanding benchmark) was chosen for the evaluation, and the results are used to compare the performance of the ASP architecture with the performances of other parallel computer architectures when applied to the same computer vision tasks. >

The authors address yield modeling considerations and their impact upon the floorplanning and defect tolerance strategies of the WSI Associative String Processor (WASP) architecture. A fully parameterized, detailed yield model for the WASP architecture has been presented previously. This yield model has been developed further and applied to the various design options for future WASP devices. Using the improved model, the impact of these design options on the yield of WASP devices is assessed, leading to a set of recommendations as the optimum WASP floorplan. >

The WASP (WSI Associative String Processor) project is aimed at the production of embedded wafer-scale MPC (massively parallel computer) components, with performance, size, weight, power dissipation, and reliability parameters that are far superior to those obtained using conventional technology. WASP 3 heralds the progression to the WASP experimental program into its application demonstrator phase. As the first in a family of three devices, WASP 3 will demonstrate fundamental signal and data processing operations using a WASP device. Of at least equal significance will be the demonstration of the use of an industry-standard microelectronic packaging route for WASP devices. This establishes that WASP packaging has progressed far beyond the laboratory bench, and is maturing towards end-user standards. >

The authors introduce and evaluate a multichip module produced in hybrid-WSI (wafer scale integration) technology embedded for real-time signal and data processing. The benefits and potential of the technologies of the HASP-1002 hybrid-WSI device are shown. The combination of improvements of the size-performance and the cost-performance trade-offs underlines the vitality of hybrid-WSI technologies, as traditionally the cost-performance trade-off worsens for size and weight sensitive applications. >

Progress to data has concentrated on the integration of 8192 processors on a single silicon wafer (viz., a 2-D WASP (Wafer Scale Integration Associative String Processor) device). The author considers the migration of the design concept to 3-D WASP wafer stacks. A 3-D WASP architecture is described and compared with its 2-D WASP predecessor. Benefits in size, weight, power, reliability, and cost are discussed, and cost-effectiveness figures-of-merit on the order of 100 tera-OPS/ft/sup 3/, 100 tera-OPS/lb, 1 giga-OPS/W, and 10 mega-OPS/$ are forecast. >

Wafer scale integration (WSI) is a technology of particular interest for applications with severe size, weight, power, cost and reliability requirements. Because of technological difficulties in implementing clock and signal distribution, monolithic WSI has not been widely employed. A novel approach to clock and signal distribution for WSI is introduced. It combines the advantages of monolithic-WSI with the superior interconnection capabilities of hybrid-WSI. >

The HASP4001 hybrid wafer scale integration (HWSI) device, optimized for massively parallel processing, is described. It is a large-area silicon-on-silicon multichip module (MCM-D). The design is based on the experience gained in the implementation of a previous-generation massively parallel computer. It is shown that the resulting module is a significantly more cost-effective system component, minimizing board area and enhancing performance. It is shown that the HWSI incorporates many of the same techniques adopted for the monolithic WSI version, ensuring reliable implementation suitable for medium scale production. >

Hybrid wafer scale integration (HWSI) is a promising technology for the cost-effective development of the next generation of massively parallel computers (MPCs). It is argued that it is not easy to understand the relative merits and technological tradeoffs associated with vendor-specific factors in order to determine the best technological route for a particular application. Cost models aimed at the resolution of these problems are introduced, and progress towards a design methodology for HWSI devices is reported. >

Details of defect and fault tolerance strategies used in the wafer interface blocks of wafer scale integration (WSI) associative string processor (WASP) devices are given. A structured approach to the design and optimization of redundant-path defect- and fault-tolerant signal distribution networks is presented. Monte Carlo simulations are used to analyze the success rate of various WASP signal distribution network topologies in the presence of randomly distributed defects. It is shown that the proposed signal distribution strategy lends itself well to high-speed recovery from in-operation failures. >

While hybrid and monolithic Wafer-Scale Integration (WSI) technologies have brought about dramatic improvements in the density of integration of embedded massively parallel computers (MPCs), systems and applications engineers continue to demand ever more processing power in less space. The emerging technology of 3D-WSI offers a way of meeting this challenge, giving the potential for step-function increases in parallelism using existing WSI package options. It also permits independent scaling of I/O, parallel processing power and control, leading to a degree of cost-effectiveness that conventional 2D-WSI cannot match. The paper explores the potential of 3D-WASP (WSI Associative String Processor) and reports the results of a study into the engineering feasibility of such a device. This study suggests that a single 3D-WASP device, packages in a standard 2.5"/spl times/2.5"/spl times/0.25" can could deliver 100 Giga-OPS performance form 65536 processing elements, provide up to 64 input-output data channels of 16 bits each and dissipate only 25 W. >

Parallel computing shows considerable potential to deliver cost-effective solutions to applications with high requirements in performance. However, current experience shows that performance often falls well below user expectations and below what would be considered cost-effective. Therefore, MPC hardware and software designers need to focus on the factors which affect parallel computing efficiency, if they are to narrow the gap between potential and delivered performance. Many analyses of parallel computing efficiency which have been reported are mainly too restrictive to provide helpful results. Thus, a different approach is required which would help parallel architecture and algorithm designers to climb the learning curve associated with parallel computing efficiency. In this paper, a performance analysis is introduced which makes a distinction between natural parallelism (which is inherent to an application) and applied parallelism (which can be observed when an application is implemented on an MPC). By highlighting parallel computing bottlenecks the analysis supports MPC hardware and software designers to identify causes for inefficiency. Furthermore helpful efficiency measures can be defined. The paper demonstrates the usefulness of the analysis and concludes that it could form the basis of a methodology which formalises the improvement of parallel computing efficiency. >

Hybrid-WSI technologies offer an attractive implementation route for Massively Parallel Computing (MPC) Modules. However, cost and, especially, delivery problems, still associated with these technologies make MPC manufacturers wary. Uncertainties are mainly caused by limited individual die yields, and loss of good die during the mounting and bonding processes. Although significant research effort is aimed at supplying "known-good-die" and die yields can be expected to improve in the near future, these are likely to be superseded by increased levels of integration. This paper demonstrates how redundancy and reconfiguration can offer a solution to the problem and ensure on-time delivery while reducing the production cost of hybrid-WSI MPC modules significantly. >

The problems of external interfacing and internal interconnection for WSI (wafer scale integration) devices are considered. In particular, the WASP (WSI associative string processor) 2A device is examined in detail, and practical results are presented. Analysis of the experimental on-wafer interconnection included on WASP 2A has shown that, given simple layout precautions, a high yield can be obtained for non-defect-tolerant buses. However, it is also apparent that practical experience concerning the defect modes of these buses is important in the design of any defect tolerance strategy for yield improvement. Results from using WASP 2A have shown that defect and fault tolerance may be cost-effectively implemented at the level of the wafer interface, allowing for the recovery from defects and in-service failures, and substantially increasing the projected yield of this crucial wafer component. >

Addresses yield modeling considerations in the development of the WASP (WSI associative string processor) architecture, floor plan, and defect-tolerance strategy. A fully parameterized, detailed yield model for WASP devices is presented, and the implications of various design options for device yield are analyzed. The WASP architecture has been shown to be capable of yields well in excess of the target of 50% for 8192-APE WASP devices. >

A WASP device is a WSI implementation of an ASP (Associative String Processor) substring and, as such, it constitutes a fundamental building block for the assembly of SIMD Massively Parallel Computer (MPC) components. This paper describes current progress in the WASP 3/4/5 programme. >

It is demonstrated that wafer-scale-integration associative string processor (WSI ASP) module components offer a 150-800 times improvement in TOPS (tera operations per second)/ft/sup 3/, a 13 times improvement in GOPS (giga operations per second)/W and a 14-44 times improvement in MOPS (mega operations per second)/$ over VLSI components. For all three figures-of-merit monolithic-WSI ASP modules have an advantage over hybrid WSI ASP modules. In addition, the inherent defect-tolerance in the manufacture of monolithic-WSI ASP modules offers fault-tolerance in service, which the hybrid-WSI ASP could only match with an increase in chip size and cost. Lastly, and significantly for the future, the precisely regular layout of monolithic-WSI ASP wafers renders them excellent candidates for highly-compact 3-D packaging techniques, offering significant improvements in TOPS/ft/sup 3/ which could not be achieved with hybrid-WSI. >

The new decade (1990-2000) heralds the age of very powerful compute-, graphics- and information-servers, based on Massively Parallel Processors (mppS), capable of TOPS (Tera Operations-Per-Second) performance in networked scientific, engineering, knowledge-base and artificial intelligence applications. This paper describes a WSI associative string processor (WASP) in CMOS fault-tolerant WSI MPP architecture which satisfies both the architectural and engineering requirements outlined and, thereby, offers a step-function improvement in cost-effectiveness compared with first-generation MPPs. >

ASP (associative string processor) modules comprise highly-versatile parallel processing building-blocks for the simple construction of application-specific second-generation massively parallel processors (MPPs). The author discusses ASP module philosophy, demonstrates how ASP modules can satisfy the market, algorithmic, architectural, and engineering requirements of application-specific MPPs, and reports on current progress in the development of ASP technology. A case example indicates that 1 TOPS/ft/sup 3/, 1 GOPS/W, and 1 MOPS/$ can be reasonably forecast figures-of-merit for the cost effectiveness of second-generation MPPs built with WSI ASP modules. Comparison with first-generation MPP implementations reveals a 2-3 orders-of-magnitude advantage in favor of the ASP modules. >

The Massively Parallel Computing (MPC) arena continues to demand ever more powerful and compact building-blocks, especially for the construction of embedded-MPC systems. Multi-Chip Modules (MCMs) offer a means of implementing such building-blocks, but have been shown to suffer from cost and delivery problems at the complexity levels required. As these problems stem from infant die mortality, assembly yield losses and the 'known-good-die' problem it has been proposed to incorporate fault-tolerance into an MCM to permit these faults to be overcome by programmable MCM configuration, rather than costly and time-consuming module re-work. Theoretical studies have confirmed the potential of this approach, but it remains to evaluate practical means of its implementation. The present paper reports the results of an initial practical experiment into the design of such an MPC MCM that uses a fault-tolerant active substrate based on an existing gate-array wafer.

In this paper the author sets out to explore the cost-effectiveness of wafer-scale embedded-MPC (massively parallel computers) modules for cost-effective image processing systems. Design considerations for modular-MPC accelerators for image processing workstations have provided the basis for a case-study. It has been demonstrated that, with the WSI ASP modules being developed by Aspex Microsystems, modular-MPC accelerators could offer the application flexibility and cost-effectiveness to overcome current problems and achieve end-user acceptability.

The paper presents an investigation into two defect and fault tolerant signal routing strategies for WASP devices. The success rate of each strategy in establishing good signal routing connections, for a complete 32-bit WASP bus structure in the presence of randomly distributed defects is investigated using Monte Carlo simulations. The most efficient, as well as defect and fault tolerant, of the two strategies is then identified.

A performance-scalable ISDP (Interactive Sensor Data Processing) workstation, accelerated with commercial PCI multiprocessor cards, is described and a WSI massively data-parallel processor (MdPP) device is proposed for the replacement of its VLSI processors. Delivering 60 GOPS for 16-bit integer multiply-accumulate operations, a WSI-FPGA implementation of the reconfigurable device is shown to be better suited to ISDP applications and at least two orders-of-magnitude more cost-effective.

Real-time near Earth objects (NEO) detection is a problem requiring large processing capabilities due to the large CCD arrays and computation intensive algorithms to ensure system efficiency. The paper summarises the results and recommendations from the study for the use of a modular-MPC (massively parallel computer) as a cost-effective solution for real-time NEO detection.

Research into new computer structures, which would be better suited to non-numerical information processing tasks, has been in progress for some years.1,2,3The problem has been to design a computing system with high hardware efficiency and low software complexity over a wide range of these applications. Recent research4,5,6has indicated that these apparently conflicting requirements could possibly be achieved by a parallel processing system containing content-addressable storage. Hence there is a revival of interest in associative memories and associative processors.

The authors discuss the design, development and implementation of the 9-kb (256-word*37-bit) associative memory used in the single-chip array processing element (SCAPE) chip, a CMOS VLSI associative parallel processor (APP) that integrates 256 associative processing elements (APEs) on a single 68-pad chip to achieve high-speed, cost-effective image and signal processing. It is shown that a static CMOS content-addressable memory (CAM) design is unsuited to the constraints of the SCAPE chip architecture and that a purely nMOS CAM cell provides the best compromise between the conflicting area, speed, power, and control requirements. Comprehensive details of this design are given together with an evaluation of its performance. Finally, a description of the design methodology used in the construction of the SCAPE chip is presented with a breakdown of circuit areas and operational data. >

The author presents ASP architecture, which offers cost-effective support of a wide range of numerical and nonnumerical computing applications, using state-of-the-art microelectronic technology to achieve processor packing densities that are more usually associated with memory components, ASP is designed to benefit from the inevitable VLSI-to-ULSI-to-WSI (very large, ultra large, and wafer-scale integration) technological trend, with a fully integrated, simply scalable, and defect/fault-tolerant processor interconnection strategy. The author discusses the architectural philosophy, structural organization, operational principles, and VLSI/ULSI/WSI implementation of ASP and indicates its cost-performance potential. ASP microcomputers have the potential to achieve cost-performance targets in the range of 100 to 1000 MOPS (million operations per second) per $1000. This gives ASPs an advantage of two to three orders of magnitude over current parallel computer architectures. >

A design for a 256 bit dynamic MOS associative memory, integrated on a 60/spl times/80 mil chip, is described. Computer simulation studies predict match, read, and write access times of less than 10 ns. Line capacities are sufficiently small to allow quite large associative memory arrays to be controlled by cheap peripheral circuitry.

The SCAPE chip is a practical implementation of a VLSI associative string processor; integrating a string of 256 identical processing elements, each comprising 37 bits of content-addressable memory, a 1-bit adder and logic for communication with other processing elements. Packing 143K transistors on a 73 mm2 silicon die, with 2.5 ?m p-well (two-layer metal) CMOS design rules, the SCAPE chip is packaged in a 68-pin chip carrier and, operating at 10 MHz, dissipates less than 900 mW. The paper describes the SCAPE chip architecture and floor plan in structural detail. Testability considerations, design verification and SCAPE software are discussed, and the results from recent performance simulation studies are also reported. The SCAPE chip is scheduled for fabrication, by Plessey (Caswell), in the second quarter of 1986.

The production cost-per-bit of high-speed associative memory, implemented with m.o.s. l.s.i. content addressable memory (c.a.m.) devices (selected from a survey of 20 designs), is compared with that of conventional memory, implemented with currently available m.o.s. l.s.i. random access memory (r.a.m.) devices.For a development cost of about £20k, the cost-perbit of the m.o.s. c.a.m.s is about 5× that of a 1024-bit p-channel m.o.s. dynamic r.a.m. and about 9× that of a 4096-bit n-channel m.o.s. dynamic r.a.m., if plastic dual-in-line packaging is employed. However, for open-chip (beam-lead or flip-chip) assembly the cost-per-bit of the m.o.s. c.a.m.s is less than 2× that of the 1024-bit r.a.m. and less than 3× that of the 4096-bit r.a.m.It is shown that for most associative processing applications the associative memory can provide a cheaper alternative to conventional r.a.m.-based computer systems.

A novel fine-grain parallel-processing microelectronic architecture is proposed as a cost-effective building-block for fifth-generation computer systems. Based on a fully programmable associative string processing computational structure, the architecture provides particularly flexible support and manipulation of abstract data structures over a wide range of information processing tasks. Moreover, the architecture is well suited to the technological constraints of VLSI chip and, especially, WSI device fabrication. The paper describes the ASP (associative string processor) architecture and its instruction set. The style of associative string processing is introduced with three algorithms, illustrating both relational and arithmetic operations. Current projects leading to VLSI ASP chips and WSI ASP devices are discussed and ‘ball-park’ performance figures are given.

Since the early 1960s, semiconductor chips have matured from single transistor devices to 1 million transistors per chip. This increase in integration has been achieved by reducing transistor dimensions, and by increasing chip sizes. However, physical limits are being reached as submicrometre dimensions are approached. Therefore, there is need for larger chip, and wafer, sizes. Manufacturers use defect tolerance to maintain the increase in chip complexity; acceptable yields are achieved with larger chip sizes. In the paper, various aspects of defect-tolerant design are investigated. It is suggested that yield improvement is only one of the many possible gains offered by defect tolerence. The advantages and disadvantages of the many approaches to defect tolerance are discussed. Wafer-scale integration appears to be the target size for defect tolerant IC chips, but as wafer size continues to increase, the constraints due to wafer-scale implementation of an architecture must be weighed up against the advantages that such devices offer. The paper also examines a particular subsystem implemented in VLSI, ULSI and WSI, and considers the relative merits of each implementation.

A design technique, which allows the data-storage and the word-control functions of a byte-organized variable record-length Associative Parallel Processor (APP), to be integrated on a single l.s.i. chip is discussed, and a new l.s.i. device, called the Micro-APP, is proposed. Two implementations of the Micro-APP (16 words × 16 bits and 32 words × 12 bits) are described and their characteristics compared with a similar APP in which all functions are implemented separately. Improvements of 16% and 112% in bit-per-pin ratio and reductions of 96% and 94% in cost-per-word-row are reported. Minimum times for a search/write cycle (with tag resolution) of 190ns and 220ns are also recorded.

A design for a 128-bit m.o.s. associative memory is described. The memory array can be integrated on a 1.6 × 2.9 mm (63 × 114 mil) chip using standard silicon-gate m.o.s. fabrication technology. The basic memory cell is dynamic in operation, but external refresh circuitry is not required. Computer simulation studies predict match and read access times of 10 ns, and a write ‘toggle’ time of 25 ns. A design for a cheap interface buffer circuit is also described. With these two designs it is possible to build a low-cost associative memory array, organized as 256 words of 256 bits each, which is TTL compatible and will operate with a 100 ns cycle time.

An experimental 64-bit m.o.s. associative memory has been developed from a limit-case design study. Speeds in excess of 50 MHz are reported at a cost per bit that could approach eight times that for a conventional m.o.s. dynamic r.a.m. The design of the basic associative memory cell is described.