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In this paper, high temperature Phosphorus ion implantation is applied to p-type Si (1 0 0) substrates and n-type bulk Si fin field-effect-transistors. Phosphorus profiles and sheet resistance on p-type Si (1 0 0) substrates are analyzed. High temperature ion implantation shows less Phosphorus diffusion after rapid thermal annealing compared to room temperature ion implantation. In n-type bulk Si fin field-effect-transistors with wide spacers and ion implanted source and drain, the high temperature extension ion implantation shows better electrical characteristics in terms of drain-induced-barrier-lowering, on-state resistance, on-state current, and off-state current. In n-type bulk Si fin field-effect-transistors with narrow spacers and Phosphorus in-situ doped Si epi source and drain, drain-induced-barrier-lowering and off-state current characteristics are improved by high temperature extension ion implantation, compared to room temperature extension ion implantation. Phosphorus distribution in fin field-effect-transistors is analyzed by scanning spreading resistance microscopy. Suppression of Phosphorus diffusion into the channel area is confirmed.

The aggressive downscaling of FET devices (FinFET, NanowireFET, NanosheetFET, to name a few) in past years has put a great emphasis on the need to come up with properly calibrated process and device simulation tools to predict performances, suggest processing options and even understand failure mechanisms. As their modeling is complex with multiple calibration parameters, adequate two- and three-dimensional characterization techniques have been identified as a necessity to achieve an accurate modeling and calibration of the complex physical mechanisms for scaled devices. In such scaled devices even the smallest variations of the structure dimensions (i.e., width or length, local interconnect or spacer, source/drain epi volumes, etc.), carrier distribution and/or activation rate can cause significant variations in the electrical properties.

New process options in CMOS technology scaling often result in degradation of ESD device performance. TCAD simulations bring an in-depth look at the impact of S/D epitaxy process options with channel strain engineering on CDM-time domain turn-on transient overshoot of ESD diodes in next generation bulk FinFET and GAA technologies.

Solution processed polymer (donor) and fullerene (acceptor) bulk heterojunctions are widely used as the photo active layer in organic solar cells. Intimate mixing of these two materials is essential for efficient charge separation and transport. Identifying relative positions of acceptor and donor rich regions in the bulk heterojunction with nanometer scale precision is crucial in understanding intricate details of operation. In this work, a combination of Ar(+)2000 gas cluster ion beam and scanning probe microscopy is used to examine the lateral and vertical phase separation within regio-regular poly(3-hexylthiophene)(P3HT):phenyl-C60-butyric acid methyl ester (PCBM) bulk heterojunction. While the Ar(+)2000 gas cluster ion beam is used as a sputter tool to expose the underneath layers, scanning probe microscopy techniques are used to obtain two-dimensional (2D) electrical maps (with sub-2 nm lateral resolution). The electrical mapping is decoded to chemical composition, essentially producing lateral and vertical maps of phase separation. Thermal stress causes large PCBM-rich hillocks to form, and consequently affecting the balance of P3HT:PCBM heterojunctions, hence a negative impact on the efficiency of the solar cell. We further developed a method to analyze the efficiency of exciton dissociation based on the current maps and a loss of 20% in efficiency is observed for thermally degraded samples compared to fresh un-annealed samples.

Display Omitted We present the concept and fabrication for overcoated diamond tips (ODTs).We show that thin diamond layers can be deposited into recessed areas in an upside-down manner.The diamond tips (ODTs) overcome the breaking issue of conventional coated silicon probes (CDTs).We show that ODT probes allow the high-conductivity nanoscopic analysis of device structures. Micromachined diamond tips have become the ultimate choice for the electrical probing of semiconductor devices at the nanometer scale because of the required high pressures in the GPa range. Although state-of-the-art full diamond tips (FDTs) show an ultra-high spatial resolution of 1nm, they are suffering from the limited electrical conductivity of the interfacial diamond layer resulting in an overall lower dynamic range. Conventional coated diamond tips (CDTs) on the other hand show a higher electrical conductivity but their core Si tips are prone to breaking off close to the apex due to the high lateral forces during scanning. Therefore, we developed in this work so-called overcoated diamond tips (ODTs) which are combining the advantages of the high mechanical stability of molded FDTs with the higher conductivity of CDTs. The key is the local underetching of a first molded diamond tip and the subsequent growth of a 50-150nm thin boron-doped diamond layer onto the interfacial diamond layer. The resulting ODT structure is attached to a metal cantilever and is used for electrical atomic force microscopy (AFM) measurements. The fabricated ODTs are mechanically stable and show a higher conductivity than FDTs. This work presents the probe and fabrication scheme, shows manufactured probe devices and demonstrates their performance in electrical AFM measurements.

Electrical nanoprobing inside scanning electron microscopy (SEM) systems has become a routinely used characterization technique for electrically measuring prototypes of the most advanced nanoelectronics device structures. Tungsten wire needles with a sharpness of about 50-100nm are commonly used as probe tips in these measurements. They suffer unfortunately from tip oxidation effects and need to be initialized. Moreover, they are too soft to directly probe on semiconductor materials such as Si and Ge. Therefore, harder probe tips are required which can withstand high pressures (in GPa range) and oxidation. In order to meet these requirements, we have developed doped diamond tips and integrated them into metal cantilevers. They have an in-plane geometry which allows direct visibility in the SEM system of both the area to be contacted and the tip apex. Furthermore, the probes are mounted at the end of a metal wire which ensures compatibility with existing nanoprobing systems and allows for convenient probe handling. This paper describes the probe concept and discusses the probe fabrication process in detail. Manufactured probes are presented and their suitability for measurements on a Ge calibration structure is demonstrated. Our work shows that the developed diamond nanoprobes overcome the disadvantages of existing tungsten wire probes and enable the probing of semiconductor materials.

With the transition from planar to three-dimensional device architectures such as FinFets, TFETs and nanowires, new metrology approaches are required to characterize the 3D-dopant and carrier distributions precisely, as their positioning relative to gate edges, 3D-distribution, conformality, and absolute concentration determine the device performance in great detail. Concepts like atomprobe tomography with its inherent 3D-resolution are obviously a potential solution although its routine application is still hampered by localization problems, reconstruction artifacts due to inhomogeneous evaporation, sensitivity due to the limited statistics, poor tip yield, etc. Although on the other hand concepts like scanning spreading resistance microscopy are inherently 2D, extensions towards 3D appear possible either by the design of dedicated tests structures or by novel approaches such as mechanical scalping. Ultimately even 1D-methods like secondary ion mass spectrometry can be used to study dopant incorporation in 3D-structures. When assessing their performance as metrology tool for 3D-devices and structures one needs to address not only their ability to achieve 3D-spatial resolution but also the physical property which is probed, i.e. dopants versus carriers, as well as the complexity of the method used. An evaluation in terms of time to data is equally important as the technical capabilities. The application of these methods to 3D-structures and confined volumes, has demonstrated that the changing surface/volume ratios in confined devices versus blanket films lead to phenomena (dopant deactivation, enhanced diffusion,..) which cannot be observed in blanket experiments. Hence more emphasis should be placed on the analysis of device and structures with the relevant dimensions relative to the exploration of blanket experiments. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Self assembled monolayers derived from amino silane precursors (C 11 NH 2 ) are studied using conductive AFM (C-AFM) technique in high vacuum (HV) conditions (∼5 × 10 −5 torr). Working in HV condition was preferred to working in air in order to reduce the impact of water meniscus on the surface which increases the adhesion forces causing smearing of the SAMs. C-AFM current maps of these samples indicate a decrease in the number of leakage spots with an increase in the deposition time. The latter is indicative of a trend towards a complete coverage of SAMs for the higher deposition times. To further assess the electrical properties of the SAMs, point I – V spectroscopy measurements were performed up to the point of electrical breakdown. The breakdown voltage increases with the increase in the number of multilayers for the 3 h, 6 h, and 18 h deposition time and then drops for the 24 h deposition time. In this final case we speculate that the numbers of impurity sites are higher and the charge carriers need less electric field to tunnel to the nearest site.

Electron beam induced current (EBIC) measurements can be used to visualize depletion region in semiconductor junction structures. In this work we use a nanoprober setup to create local contacts to nanowire (NW) based tunnel-field-effect-transistors (TFET), which are gated p-i-n diodes, and perform EBIC measurements to investigate dopant diffusion effects in the junction region of TFET structures fabricated with high and low thermal budget. For contacting we use commercial tungsten probes and in-house fabricated conductive diamond tips. The results show that nanoprober based EBIC measurements are a straight forward way to study the functionality of a large number of NWs simultaneously while also allowing to make an in-depth investigation of the junction position as a result of different processing conditions of the nanowire transistors.

The performance of nanoelectronic devices critically depends on the distribution of charge carriers inside such structures. High-vacuum scanning spreading resistance microscopy (HV-SSRM) has established as the method of choice for quantitative 2D-carrier mapping in nanoscale devices during the last decade. However, due to the 3D-nature of these nanoscale device architectures, dopant incorporation and dopant diffusion mechanisms can vary for any of the three dimensions, depending on the particular processes used. Therefore, mapping of carriers in three dimensions with high spatial resolution is inevitable to study and understand the distribution of active dopants in confined 3D-volumes and ultimately to support the process development of next generation devices. In this work, we present for the first time an approach to extend the capabilities of SSRM from an inherent 2D-carrier profiling technique towards a quantitative 3D-characterization technique based on the example of a nanowire (NW)-based heterojunction (SiGe–Si) tunneling transistor. In order to implement a 3D-methodology with a 2D-imaging technique, we acquired 2D-carrier concentration maps on successive cross-section planes through the device of interest. This was facilitated by arranging several devices in a staggered array, allowing to produce a series of cross-sections with incremental offset by a single cleave. A dedicated interpolation algorithm especially suited for structures with rotational symmetry like NWs was developed in order to reconstruct a 3D-carrier distribution map. The validity of the method was assessed by proving the absence of variations in carrier distribution in the third dimension, as expected for NWs etched into a blanket stack.

In order to confirm the existence of a height-selective emitter, we compared local doping profiles of such emitters with profiles of a standard homogeneous emitter. The concept of a height-selective emitter is based on the classical selective emitter but in a smaller scale. The pyramid tips are highly doped. The sides and valleys are lowly doped. The comparison of the doping profiles was addressed by using a high-spatial-resolution analysis method: scanning spreading resistance microscopy. The measurement was performed on fully produced cells with a height-selective emitter and a standard homogeneous emitter, both with random pyramid textured surfaces. We prepared samples from these cells and investigated the cross sections. A representative pyramid of each type of emitter was selected. We found that for height-selective emitters the surface concentration can strongly vary depending on the measured position of the selected pyramid. The tip of the pyramid is heavily doped, while the bottom is lowly doped. For standard cells with a homogeneous emitter, the doping profiles do not differ dramatically as for the sample with a height-selective emitter. We calculated the local sheet resistance by using the measured local emitter profiles and a doping-dependent mobility model for phosphorus-doped silicon.

This work investigates the interface resistivity of several heterostructures. Theoretical simulations suggest that, apart from the doping impact, the band offset and the difference in density of states (DOS) increase significantly the heterostructure interface resistivity. This conclusion corresponds well to our experiments that 1) high interface resistances are observed between (high-Ge content) p-SiGe/p-Si, n-InAs/n-Si, and n-InAs/n-Ge; and that 2) a TiSi x /12nm Si:P/n-Ge contact with favorable band alignment between Si:P/n-Ge approaches low effective contact resistivity of 1.4×10−8 Ω cm2, close to a record-low value for n-Ge contacts.

In this paper, we illustrate how high resolution two-dimensional (2D) carrier maps obtained from scalpel scanning spreading resistance microscopy (s-SSRM) can be applied to calibrate a technology computer aided design (TCAD) simulator in order to predict and understand the performance of sub-10nm WFIN FinFETs. In the proposed approach, process simulations are calibrated such that the resulting simulated carrier profiles match the quantified s-SSRM profiles. Upon reaching satisfactory agreement, they can be used as input for device simulators in order to predict more accurately key device parameters such as the linear on-state resistance (RON, LIN), and the threshold voltage (VT, SAT) roll-off to name few. This also allows us to accelerate the development of devices towards new technology nodes (as N7 and N5) by identifying parameters to be improved and technological options to be selected.

We demonstrate the effectiveness and limitations of critical performance elements in silicon channel bulk finFET CMOS devices featuring embedded Source/Drain (e_SD) dual epi. Further scaling of the fin width below 10nm is shown to impact both the access resistance and S/D overlap capacitances while the mobility behavior for both nMOS and pMOS devices further degrades. Epitaxial S/D regrowth options are optimized to demonstrate ring-oscillator functionality for fin width down to ∼4nm.

Electrical atomic force microscopy (AFM) methods require highly conductive tips with nanometer-scale spatial resolution. Si tips with metal (e.g. PtIr) and doped-diamond coatings are most commonly used. Metal coatings are however prone to rapid wear and diamond coatings are limited in conductivity and spatial resolution. Therefore, we have developed solid TiN tips with a pyramidal shape made by molding using anisotropic Si etching for defining an inverted pyramid and TiN sputtering for mold filling. The TiN tips are attached to Ni electroplated cantilevers. The probes are removed from the substrate using a dedicated peel-off step. The fabrication process is based on state-of-the-art 200-mm Si wafer technology. Probe evaluation in AFM shows a typical spatial resolution of about 8-15nm for these TiN tips. Using the hard TiN tips in scanning spreading resistance microscopy (SSRM) we demonstrate two-dimensional measurements of Ge doping staircase structures which could so far only be measured by doped diamond tips. Further measurements of carbon nanotube (CNT) interconnects and high-k metal gate stacks by conductive AFM (c-AFM) illustrate the potential of the TiN tips. This paper describes the probe concept, fabrication and evaluation in AFM.

In this paper we present a procedure and software allowing to predict and understand device performance by incorporating two dimensional (2D)-carrier profiles obtained from high vacuum scanning spreading resistance microscopy (HV-SSRM) into a device simulator. We demonstrate the incorporation of quantified SSRM 2D-carrier profiles obtained on p-MOSFETs into a device simulator. The simulated electrical characteristics (based on the measured 2D-carrier profiles) of the device show nice agreement with the experimentally obtained device results, whereas calculations based on process simulations with available advanced calibration showed significant discrepancies. With this approach the difficult and time consuming calibration step of the process simulation can be circumvented and device results can be interpreted directly based on the details of the real 2D-carrier profiles.

The semiconductor ICT industry continues its neverending pursuit of new approaches for fabricating integrated circuits to reduce device cost and improve device performance. For future device generations, many different approaches are considered, for which the efficient engineering of new materials and architectures are the main challenge to improve device performance. InP is one of these new materials, which is considered to be used as virtual substrate for III-V based nMOS devices.

We discuss the selective epitaxial growth of InP on patterned Si (001) substrates with Shallow Trench Isolation using a thin Ge buffer to facilitate InP nucleation. The main focus is the defect formation mechanism during epitaxial growth and to develop solutions to reduce defect density so that device-quality III-V virtual substrates can be realized on large-scale Si substrates. We compare the InP growth on on-axis and off-axis Si substrates. In the case of off-axis wafers, the formation of stacking faults / twins cannot be avoided, at least not at one of the four STI side-walls. The formation of antiphase domain boundaries is reduced (but not yet completely eliminated) by engineering the local Ge surface profile. Further, the high density of Ge surface steps promotes step-flow growth mode instead of 3D growth during the growth of the InP seed layer. Finally, high aspect ratios (>2) allow to confine threading dislocations in the bottom of the trench.

Pyramidal tips made from boron doped diamond have become the ultimate choice for electrically measuring semiconductor device structures in electrical atomic force microscopy (AFM). An advanced measurement setup with diamond probing units directly integrated inside a scanning electron microscopy (SEM) system is highly wanted as this allows for accurate tip positioning compared to the optical microscope of a standard AFM and enables also multiple tip measurements. Therefore, we have developed highly conductive in-plane diamond tips with a triangular shape and attached them to Ni cantilevers. We have established a LabVIEW-based setup enabling automated electrical measurements inside a SEM system using stick-and-slip motion nanomanipulators and a parameter analyzer system. To our best knowledge, this paper presents first 1- and 2-tip electrical measurements of microfabricated diamond probes inside a SEM system. Measurements of Si staircase and Ge structures are shown and compared to scanning spreading resistance (SSRM) results. Our work demonstrates that doped diamond tips clearly outperform common tungsten probe needles enabling nanoprobing experiments which were impossible so far. Based on our results, we predict that doped diamond is going to be the standard tip material not only for electrical AFM but also for nanoprobing of semiconductor materials.

Within this work, we have explored the use of scanning spreading resistance microscopy (SSRM) on advanced solar cell structures. Three main topics, corresponding to three important needs, were targeted. First, we have analyzed the highly doped regions at the frontside of solar cells. The influence of the surface roughness, hindering the use of other techniques (e.g., secondary ion mass spectrometry, SIMS), and the phosphorus diffusion along grains for multicrystalline silicon (mc-Si) have been studied quantitatively as they may affect substantially the electrical properties of solar cells. Secondly, we have explored local backside contacts manufactured using new techniques like laser ablation followed by dopant diffusion. Having a better knowledge of the two-dimensional (2D)-dopant distribution is a subject of growing interest. Finally, we have studied electrical properties of grain-boundary and intragrain defects in polycrystalline silicon (pc-Si) layers as they may play a major role in the electrical performances of the solar cells.

Systematic experimental studies on phosphorus diffusion from phosphosilicate glass into the p-type bulk Si (100) substrate with different capping barrier layer thicknesses have been conducted. In both 2- and 5-nm phosphosilicate glass conditions, a thicker SiO2 cap showed a lower sheet resistance and a higher retained phosphorus dose in the Si substrate after 1050 °C 4 s rapid thermal annealing as drive-in annealing. However, the sheet resistance of 2-nm phosphosilicate glass with a 10-nm SiO2 cap was lower than that of 5-nm phosphosilicate glass with a 3-nm SiO2 cap due to a higher retained phosphorus dose in the Si substrate. For a higher retained phosphorus dose in the Si substrate using fixed total thickness, 2-nm phosphosilicate glass with 6-nm SiO2 cap is better than 5-nm phosphosilicate glass with 3-nm SiO2 cap since prevention of phosphorus out-diffusion during the drive-in annealing is more important than the total phosphorus dose in phosphosilicate glass. Next, SiO2 cap thickness on 2-nm phosphosilicate glass was split to understand the role of the SiO2 capping layer in detail for scaled devices. 3-nm SiO2 cap could not prevent out-diffusion during the drive-in annealing, and it showed much higher sheet resistance and lower retained phosphorus dose in the Si substrate. The highest retained phosphorus dose in the Si substrate was observed for 6-nm SiO2 cap and resulted in 1.8 × 1014 atoms/cm2 retained phosphorus dose with 96% activation level after 1050 °C 4 s rapid thermal annealing. Thicker SiO2 caps than 6 nm were not beneficial since 10-nm SiO2 cap showed a higher sheet resistance value as well as lower phosphorus activation level (82%) compared to 6-nm SiO2 cap even though both the process conditions showed same phosphorus profiles after the drive-in annealing. That sheet resistance increase with 10-nm SiO2 cap could be caused by heterogeneous surface formation on the Si substrate with a prolonged SiO2 atomic layer deposition process.

Within this paper, the authors propose a refined high vacuum scanning spreading resistance microscopy (HV-SSRM) electromechanical nanocontact model based on experimental results as well as molecular dynamics (MD) simulation results. The formation under the tip of a nanometer-sized pocket of β-tin, a metastable metalliclike phase of silicon (also named Si-II), acting as a virtual probe is demonstrated. This gives a reasonable explanation for the superior SSRM spatial resolution as well as for the electrical properties at the Schottky-like SSRM contact. Moreover, the impact of the doping concentration on the plastic deformation of silicon for different species using micro-Raman combined with indentation experiments is studied. In order to elucidate the superior results of SSRM measurements when performed under high vacuum conditions, the impact of humidity on the mechanical deformation and Si-II formation is also analyzed using MD and SSRM experimental results.

Over the past decade, boron-doped diamond tips have become the ultimate choice for electrically characterizing microelectronics devices using scanning probe methods such as scanning spreading resistance microscopy (SSRM). Although nanometer-scale electrical resolution has been demonstrated, the development of a reliable probe process remained a challenge. Therefore, we did develop in this work solid diamond tips with sub-nanometer electrical resolution and integrated them into metal cantilevers using a peel-off approach. It is shown that the ultra-high tip resolution is achieved by diamond nanocrystals protruding from the apex of the diamond pyramid. The yield for sub-nanometer probes is 20-30% in air and 40-60% in vacuum. This paper describes the fabrication scheme, discusses probe characterization, and shows SSRM measurements obtained with these probes. Our probes are routinely used for SSRM measurements and current efforts are focusing on increasing the yield for sub-nanometer tips further.

In routine scanning probe microscopy (SPM) measurements either the tip is hidden underneath the cantilever and thus the position of the tip is only known with a very low accuracy (>5@mm) or a high aspect-ratio tip is used which is visible but is very fragile. Furthermore, for electrical applications, visible tips are simply coated with a thin layer of active material that wears fast in case of high pressure applications such as scanning spreading resistance microscopy (SSRM). In this work we present a novel approach for fabricating SPM probes with tips that can be located with sub-micrometer accuracy. A fully-integrated batch fabrication process was developed and used to make low aspect-ratio tips entirely made of hard metal (TiN) with an uncertainty on the tip position below 200nm. We evaluated our fabricated tips in tapping mode topography atomic force microscopy (AFM) and SSRM analysis. A reference sample of SrTiO"3 was used for tip evaluation in tapping mode AFM and SSRM measurements were performed on an n-type GaAs staircase test structure with different doping levels. From the topography measurements we calculated a tip radius below 40nm for our fabricated tips and we were able to resolve all of the different layers in the GaAs reference sample.

As CMOS is approaching the 22 nm node, the importance of high-mobility materials such as Ge and GaAs is rapidly increasing. For the timely development of these new technologies accurate dopant and carrier-profiling solutions for source-drain extensions with these materials are required. Identical n-type-doped (Si, Se) layers on same and opposite type medium-doped layers on S.I. GaAs substrates will be investigated, with layer thicknesses ranging from 200 down to 50 nm and doping concentration levels up to 1e20 at/cm3. In this work, secondary ion mass spectrometry will be used for dopant profiling. For GaAs carrier profiling, conventional spreading resistance probe, as commonly used in Si-CMOS, fails. Hence, reliable alternatives need to be found for characterizing these high–low structures. Techniques to be discussed range from the more conventional approaches such as Hall or electrochemical capacitance–voltage (performed by different laboratories), over micro-Raman spectroscopy and photo-luminescence along a beveled surface, up to more advanced approaches using scanning spreading resistance microscopy.

We report the simultaneous improvement of both on- and off-properties for n- and p-channel MOSFETs by means of carbon co-implantation at extension level, using conventional spike annealing. For the first time, spike-annealed NFETs with phosphorus-implanted source/drain extensions (SDE) are shown to outperform conventional As-implanted devices in the deca-nanometric range. Parameters such as on-current, drain-induced barrier lowering (DIBL), external resistance (REXT) vs. effective channel length (Leff) trade-off are examined. To obtain the full benefit of carbon co-implantation, we recommend adjusting pocket, highly doped drain (HDD) and spacer parameters.

When comparing the extracted carrier mobility of long- and short-channel transistors, special consideration must be given to the metallurgical gate length (Lmet), neglecting the impact of source and drain junction profiles. Lmet can be identified with nanometer precision by using RF split-C-V measurements, and physical and electrical analysis can demonstrate the accuracy of the method. Another important parameter, the external transistor resistance (Rsd), can be identified with linear current measurements of short-channel devices. However, it is important to quantify the mobility dependence from the gate length in order to obtain an accurate result. A method to estimate the electrical field (Eeff) of short-channel devices is proposed. The extracted short-channel mobility shows a universal behavior identical to the classical long-channel one.

Planar devices have been used for manufacturing integrated circuits for many decades already. Further device shrinkage and performance improvement by conventional size scaling are reaching their limits because of increasing difficulty to control short channel effects (SCE). In this paper, various approaches for source and drain doping in planar transistors are presented and discussed. The conventional approach based on implant and dopant activation anneal is analyzed versus other technologies. Especially many new developments in thermal treatment of the wafer in order to activate dopants and control their diffusion are presented.

Within this work, we have studied ultrathin n- and p-type extension implants in order to evaluate the junction delineation accuracy and reproducibility of the SSRM technique on ultra-shallow implants. This is a challenging task since it needs a technique that has simultaneously good sensitivity (

Site-specific real three-dimensional (3D) carrier profiling in sub-10nm WFIN devices is demonstrated for the first time. Extension-gate overlap, active dopant concentration and distribution inside extensions and epi source/drain are observed with 1 nm-spatial resolution along X, Y and Z-directions. Using this new technique providing full 3D-carrier mapping we analyzed different processing flows for sub-10nm fin width FinFETs, identified possible failure mechanisms, and demonstrated the direct link between improved performance and 3D-carrier distribution at the nm-scale.

The performance of nanoelectronics devices critically depends on the distribution of active dopants inside these structures. For this reason, dopant profiling has been defined as one of the major metrology challenges by the international technology roadmap of semiconductors. Scanning spreading resistance microscopy (SSRM) has evolved as one of the most viable approaches over the last decade due to its excellent spatial resolution, sensitivity and quantification accuracy. However, in case of advanced device architectures like fins and nanowires a proper measurement of the spreading resistance is often hampered by the increasing impact of parasitic series resistances (e.g. bulk series resistance) arising from the confined nature of the aforementioned structures. In order to overcome this limitation we report in this paper the development and implementation of a novel SSRM mode (fast Fourier transform-SSRM: FFT-SSRM) which essentially decouples the spreading resistance from parasitic series resistance components. We show that this can be achieved by a force modulation (leading to a modulated spreading resistance signal) in combination with a lock-in deconvolution concept. In this paper we first introduce the principle of operation of the technique. We discuss in detail the underlying physical mechanisms as well as the technical implementation on a state-of-the-art atomic force microscope (AFM). We demonstrate the performance of FFT-SSRM and its ability to remove substantial series resistance components in practice. Eventually, the possibility of decoupling the spreading resistance from the intrinsic probe resistance will be demonstrated and discussed.

This paper presents the benefits of both co-implantation of diffusion-retarding species and ultra-fast annealing techniques as studied on blanket and device wafers. F and C co-implantation with B+ for PMOS and P+ for NMOS combined with conventional spike annealing produce reduced junction depths and improved dopant activation and profile abruptness, as measured on blanket wafers and compared to similar implants without the co-implanted species. Device wafers show that the overlap capacitance is reduced, consistent with the shallower junction depths and reduced lateral diffusion. The improved dopant activation manifests itself in reduced series resistance and improved Ion values. Depending on the implant conditions, either the gate/extension overlap capacitance or the series resistance can be improved when sub-melt laser annealing is used instead of conventional spike anneal. For both approaches, scanning spreading resistance microscopy (SSRM) measurements confirm the shallow junction depths and reduced lateral diffusion.

In this paper, we demonstrate the consequences of extension junction formation by low-temperature solid-phase-epitaxial-regrowth in nMOS transistors. Atomistic simulations, experimental device results, sheet resistance, and scanning spreading resistance microscopy data indicate that the high concentration of silicon interstitials associated with the end-of-range defect band promote the local formation of boron-interstitial clusters, and thus deactivate boron in the pocket and channel. These inactive clusters will dissolve after the high concentration silicon interstitial region of the end-of-range defect band has been annihilated. This nMOS requirement is in direct opposition to the pMOS case where avoidance of defect band dissolution is desired, to prevent deactivation of the high concentration boron extension profile.

Atomic force microscopy (AFM) probes with highly doped molded diamond tips have proven to increase the resolution of scanning spreading resistance microscopy (SSRM) measurements. There is consequently a need for probes with consistent characteristics. AFM probes with molded tips require the attachment of a holder piece for their manipulation. Because of the size of this holder piece, the probes are typically released from the backside of the substrate. We propose a novel approach that combines the advantages of topside release with a release after attachment of the holder piece. In this approach, the contact area between the holder piece and the substrate is reduced to a few bonding pads. The release chemical can then flow under the holder piece in between the pads. Since only the pads need to be underetched, the release time is greatly reduced.

As emphasized in the ITRS roadmap, two-dimensional (2D) carrier profiling is one of the key elements in support of technology development. For CMOS silicon devices, scanning spreading resistance microscopy (SSRM) has demonstrated an attractive spatial resolution and concentration sensitivity. The automated construction of calibration curves allows for the fast semi-quantitative transformation of one-dimensional (1D) and 2D resistance profiles/images into resistivity/carrier profiles/images. However in order to arrive, at a reliable, fully quantitative analysis a new physical contact model involving a Schottky-like contact with tunneling and surface states has been proposed. The latter has been based on establishing a qualitative agreement with experimental data. The first aim of this work is to refine this contact model in order to achieve a quantitative agreement between device simulations (with ISE/DESSIS) and experimental 1D profiles on well-calibrated, junction isolated (carrier spilling affected), sub-micron CMOS structures. Among others, scanning spreading resistance spectroscopy (SSRS), i.e. collecting a full I–V curve at each data point, will be used. Furthermore, the impact of this new contact model on the deconvolution procedure from the measured resistance profiles/images towards resistivity/carrier profiles/images through an improved correction factor database will be discussed.

Scanning spreading resistance microscopy (SSRM) proves to be a promising two-dimensional (2-D) carrier profiling tool, particularly for complicated structures. However, its application to InP-based devices has limited quantitative possibility due to the lack of reliable measuring results. This study reveals that this limitation is related to a tip-induced (field-enhanced) oxidation procedure, which is explained by a P-diffusion-limited model. A practical solution for realizing reliable measurement is developed for the first time with excellent results. Furthermore, a fast quantification procedure based on careful constructed calibration is completed.

An STI-last integration scheme was successfully developed to fabricate low-defectivity and dopant-controlled SiGe SRB / sGe Fins. For the first time, 15 nm fin-width SiGe SRB/highly-strained Ge pFinFETs are demonstrated down to 35 nm gate length. With a CET INV -normalized G M,SAT,INT of 6.7 nm.mS/μm, the Si 0.3 Ge 0.7 / sGe pFinFETs presented in this work improve the performance by ~90% as compared to the state-of-the-art relaxed-Ge FinFETs.

Si cantilevers with conductive diamond pyramids have recently shown the highest dynamic range in scanning spreading resistance microscopy (SSRM). The use of metal cantilevers would significantly reduce fabrication costs because fewer process steps are required. Furthermore, smaller diamond pyramids, which are commonly sharper, could be used. Therefore, we have developed a procedure for metal cantilevers with diamond pyramids based on a peel-off concept which gives a yield of ∼70%. This paper discusses the fabrication of sharp diamond pyramids and their integration into metal cantilevers. SSRM measurements on Si device structures are presented. A peel-off procedure with higher yield is currently under development.

The manufacturing of state-of-the-art electronic devices involves an increasing demand for the accurate determination of ultra-shallow electrical carrier profiles related to the need to monitor the activation of the dopants with reduced thermal budgets. For sub-micron structures (down to 100 nm) a qualified conventional spreading resistance probe system is an attractive tool for the reliable measurement of the resistivity (and carrier) depth variations in silicon due to its high geometrical resolution (nm) and high dynamic range (nine orders of magnitude). The spreading resistance (SR) roadmap for future process development (sub-50 nm profiles), however, shows that there is a need for a significant reduction of the involved contact size and tip separation, a higher depth resolution (sub-nm) and an improved quantification. The recently introduced scanning spreading resistance microscopy technique resolves some of the involved issues such as the smaller contact size (20–50 nm) and the higher geometrical depth resolution (sub-nm) when applied on a bevelled surface. Further developments are, however, needed in the fields of tip configuration, surface preparation and contact modelling to achieve timely all the needs of the SR roadmap. This is expected to lead to a new instrument, the NanoProfiler™, using two small (20–50 nm contact size), closely spaced (250 nm), conductive tips mounted on an atomic force microscope-based system. The NanoProfiler TM setup can easily achieve Angstrom depth resolution and therefore makes the profiling of sub-10 nm structures feasible.

Thin-film polysilicon solar cells are a promising low-cost alternative for bulk silicon solar cells due to their reduced material thickness. Recently, we showed that the use of an amorphous silicon/polycrystalline silicon heterojunction emitter instead of a diffused homojunction emitter led to a boost in the open-circuit voltage by 90 mV. Now, we present a full evidence that shows that this improvement is related to the absence of dopant smearing along the grain boundaries. By using scanning spreading resistance microscopy, we found an enlargement of the junction area by a factor of five in case of a homojunction. The tips of the dopant spikes represent lowly doped areas with an enhanced recombination.

Atomistic Kinetic Monte Carlo (KMC) diffusion modeling is used for dopant diffusion and defect analysis in ultra shallow junction formation in Si and SiGe. An analysis of dopant diffusion and defects in SiGe-channel Quantum Well (QW) using an atomistic KMC approach are shown. Thin SiGe layer with high Ge content for SiGe-channel QW has an impact on implantation damage and Boron-Transient Enhanced Diffusion (TED) suppression, and defect evolution. KMC shows that As-pocket in SiGe-channel pFET shows enhanced diffusion toward SiGe-channel and higher As concentration in SiGe-channel. The difference of pocket diffusion is one of possible reason for the higher Vth mismatch for SiGe-channel with As pocket than for Si-channel. To avoid implant damage influence, Implant-Free SiGe channel-QW with B-doped SiGe epi for extension-S/D formation is used. KMC simulation and SSRM shows that B migration from B-doped SiGe raised-S/D to SiGe-channel can form S/D-extension overlap.

Scanning spreading resistance microscopy is a two-dimensional carrier profiling technique now widely used for the characterization of silicon (Si) devices as well as other semiconductor materials. Whereas the state-of-the-art spatial resolution for this technique using commercial-diamond-coated silicon probes is limited to 10–20 nm, enhanced resolution is demonstrated through the use of full-diamond tips integrated in Si cantilevers. Sub-5-nm-spatial resolution is obtained on fully depleted silicon on isolator devices, putting the technique closer to the characterization requirements of the forthcoming semiconductor dimensions. Resistance and scanning electron microscope measurements clearly show that this enhanced resolution results from a smaller effective radius for full diamond tips as compared to the diamond-coated Si probes.

An analysis of dopant diffusion and defects in SiGe-channel (SiGe-ch) Implant-Free Quantum Well (IFQW) using an atomistic KMC approach are shown. B-doped SiGe layer is used for S/D-extension formation. KMC and SSRM show that B migration from B-doped SiGe raised-S/D can form S/D-extension gate overlap. Arsenic Vt-adjustment implant before SiGe-ch formation instead of Arsenic pocket implant after SiGe-ch formation can reduce Arsenic concentration in channel region and shows better Vt-mismatch.

Beside the V TH -tunability, a raised SiGe S/D module offers higher L G -scalability than an embedded SiGe S/D in SiGe-IFQW pFETs. In-depth transport study of record performing 1.5mA/µm-I ON strained-SiGe IFQW pFETs reveals that mobility improvement is still the key performance booster whereas LG-scaling has limited impact.

With the continued scaling of CMOS devices down to 32nm node and beyond, device performance is very sensitive to the lateral diffusion mechanisms influencing the effective channel length. Tools are thus, required to measure with sufficient resolution and accuracy the carrier distribution. Scanning spreading resistance microscopy (SSRM) has evolved as a successful carrier-profiling technique with sub-nm resolution, less than 2 nm/decade gradient resolution and high dynamic range 1015 to 1021 cm−3. In this work, we present the approaches (methodology and special test structures) to obtain a 3D-carrier concentration map for FinFET-based devices. We also correlate the results obtained with SSRM for various process conditions and its implications on device performance.

In this work, we demonstrate for the first time 3D-carrier profiling in FinFETs with nm-spatial resolution using SSRM. The results provide information on gate underlap, dopant conformality, source/drain doping profiles. The 3D-carrier profiles as extracted for two different device approaches (extensions vs. extension-less) are conclusive in demonstrating the differences in device performance and are consistent with first order 3D-simulations.