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Superior N- and P-MOSFET scalability using carbon co-implantation and spike annealing

Superior N- and P-MOSFET scalability using carbon co-implantation and spike annealing

Authors :
Malgorzata Jurczak
J. Ramos
Philippe Absil
Stefan Kubicek
A. De Keersgieter
Serge Biesemans
Simone Severi
Thomas Chiarella
A. Falepin
Christoph Kerner
Pierre Eyben
W. Vandervorst
Bartek Pawlak
D. Vanhaeren
Emmanuel Augendre
T. Y. Hoffmann
Source :
Solid-State Electronics. 51:1432-1436
Publication Year :
2007
Publisher :
Elsevier BV, 2007.

Abstract

We report the simultaneous improvement of both on- and off-properties for n- and p-channel MOSFETs by means of carbon co-implantation at extension level, using conventional spike annealing. For the first time, spike-annealed NFETs with phosphorus-implanted source/drain extensions (SDE) are shown to outperform conventional As-implanted devices in the deca-nanometric range. Parameters such as on-current, drain-induced barrier lowering (DIBL), external resistance (REXT) vs. effective channel length (Leff) trade-off are examined. To obtain the full benefit of carbon co-implantation, we recommend adjusting pocket, highly doped drain (HDD) and spacer parameters.

Details

ISSN :
00381101
Volume :
51
Database :
OpenAIRE
Journal :
Solid-State Electronics
Accession number :
edsair.doi...........317e8a66c6e570f01ca9f7ffd7503faa
Full Text :
https://doi.org/10.1016/j.sse.2007.09.038