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This paper investigates the n-type vertical slit FET (VeSFET) performance at 7-nm node and beyond by TCAD simulation. VeSFET is a twin-gate device with 3-D monolithic integration-friendly vertical terminals and horizontal channel manufactured based on SOI wafer with conventional CMOS fabrication hardware. The second gate provides the capability of transistor behavior adjustment and the potential for advanced circuit designs. The results show that VeSFET can provide high $ {I} _{ {\mathrm {eff}}}$ to $ {I} _{ {\mathrm {off}}}$ ratio, low gate capacitance, high $\Delta {V} _{{t}}/ {V} _{{ {\textit{g2s}}}}$ , and competitive drive capability with respect to a reference FinFET of comparable dimensions.

A hybrid approach to model the effect of random dopant fluctuations in low doped FinFETs is proposed. Existing Monte Carlo and atomistic approaches are found to be inadequate to capture device variability correctly when applied independently. Instead a hybrid methodology which uses an atomistic approach in low doped regions and Monte Carlo everywhere else is developed. The hybrid approach is shown to capture the threshold voltage variability adequately. Comparison with analytical results for planar MOSFETs shows an excellent agreement and establishes the validity of the approach. The results suggest that accurate modeling of low doped regions is essential to be able to estimate variability correctly.

In this paper, a detailed 3-D numerical analysis is carried out to study and evaluate CMOS logic device and circuit performance of gate-all-around (GAA) Si nanowire (NW) field-effect transistors (FETs) operating in sub-22-nm CMOS technologies. Employing a coupled drift-diffusion room temperature carrier transport formulation, with 2-D quantum confinement effects, we numerically simulate Si GAA NWFET electrical characteristics. The simulation predictions, on the device performance, short channel effects, and their dependence on NW geometry scaling, are in good agreement with the Si NWFET experimental data reported in literature. Superior electrostatic integrity, OFF-state device performance, lower circuit delays, and faster switching in the Si GAA NWFET-based CMOS circuits are numerically demonstrated in comparison with an Si-on-insulator FinFET. The mixed-mode numerical simulations also predict low supply voltage operations for the Si NWFET-based logic circuits.

We introduce SiGe FinFET device physics, process integration, and modeling considerations. Germanium is know to have a higher hole mobility than silicon. Enhancement of hole velocity due to lattice mismatch strain in SiGe epitaxy layers is significant. In addition, uniaxial stress is beneficial for device performance. Transformation of biaxial to uniaxial stress naturally occurs when SiGe film is etched into stripes. Furthermore, control of MOSFET threshold voltage by adjusting the SiGe-channel germanium content is possible. On the other hand, SiGe processing challenges include the elimination of interface trap states at the gate dielectric interface, fast diffusion of n-type dopants, and defects in stress relaxed buffer and critical thickness limitations. Band-to-band tunneling sets a lower bound to device static leakage current.

Low Ge content SiGe-based CMOS FinFET is one of the promising technologies [1-2] offering solutions for both high performance and low power applications. In this paper, we established a competitive SiGe-based CMOS FinFET baseline and examined various elements for high performance offering. The performance elements in gate stack, channel doping, contact resistance, and junction have been explored to provide a cumulative 20% / 25% (n/pFET) performance enhancement. These elements provide a viable path towards performance enhancement for future technology nodes.

The effect of positive fixed oxide charge (Qf) on the electrical characteristics of bulk FinFET devices is investigated and newly addressed as a Fin scaling detractor. The aggressively scaled Fin width leads to abnormal subthreshold slope (SS) degradation in nMOS devices even with a long channel length, while pMOS is free of such degradation. This observation is reproduced and analyzed by a well-calibrated TCAD simulation deck with Qf introduced. A new Fin profile suppressing the Qf effect is proposed, and the benefits of the new profile are predicted in terms of variability reduction and mobility improvement, as well as Qf immunity.

This paper presents modeling and measurements of single event transients in a commercial 45 nm SOI device technology. SETs in clock circuits and pass gates can cause upsets in circuit structures hardened against single event upsets.

As semiconductor devices decrease in size, soft errors are becoming a major issue that must be addressed at all stages of product definition. Even before prototype silicon chips are available for measuring, modeling must be able to predict soft-error rates with reasonable accuracy. As the technology matures, circuit test sites are produced and experimentally tested to determine representative fail rates of critical SRAM and flip-flop circuits. Circuit models are then fit to these experimental results and further test-site and product circuits are designed and modeled as needed.

In this paper, we review the current status of single-event upsets caused by alpha-particles in IBM circuits and technology. While both alpha-particles and cosmic radiation can induce upsets, the alpha-particle-induced upset rate has become an increasingly important issue because alpha-particle-induced upsets are no longer limited to memory circuits. Latch circuits have become highly sensitive to alpha-particles. The alpha-particle-induced upset rate of latch circuits is one of the most critical issues for microprocessors requiring both high performance and high reliability.

This paper describes techniques for mitigating single event upsets in master-slave flip-flop latches in 65 nm SOI device technology. Techniques are explained, modeled, and measured with hardware experiments.

14 nm technology node bulk silicon FinFETs and SOI FinFETs and 14 nm SOI Ultra-Thin-Body and BOX nFETs were irradiated under bias using a 10 keV X-ray source. Irradiation resulted in significant changes in the threshold voltages of the SOI devices and large changes in the off-state current of the bulk FinFETs.

This paper describes a technique for modeling single-event upsets due to ionizing radiation in a partially depleted silicon-on-insulator (SOI) MOSFET device. Two current pulses are used, one connected between the drain and body of the device, and the other connected between the body and source of the device. The physical representation of these two current sources is described in detail. Circuit modeling is verified against drift-diffusion field solver modeling and hardware experiments. The effects of manufacturing variation and operating condition variation on the qCrit of circuit storage elements are explored

In this paper, we present a 10nm CMOS platform technology for low power and high performance applications with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrates. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limits. Multi-workfunction (MWF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by Random Dopant Fluctuation (RDF) from channel dopants.

A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um 2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limit. Multi-workfunction (WF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by channel dopants.

TDDB lifetime projections at operating voltages for backend of line (BEOL) dielectrics have been based on accelerated testing at high fields and extrapolation to operating conditions based on electric field dependent dielectric wearout models. As operating voltages are reduced to 1V range, such intrinsic field acceleration based wearout mechanisms become negligible making such extrapolations questionable. At the same time, as we scale the BEOL geometries, extrinsic wearout mechanisms involving copper and moisture can impact TDDB reliability. In this paper, we, for the first time, investigate extrinsic reliability in low voltage regime where electrochemical redox reactions are possible. We formulate a physical electrochemical model for TDDB. We present analytic solution for limiting cases that show TDDB lifetime dependence on voltage or electric field depending on relative rates of electrode reactions and field assisted ion transport. Generalization to higher voltages are also discussed.

The metal-gate granularity-induced threshold voltage ( \(V_{T}\) ) variability and \(V_{T}\) mismatch in Si gate-all-around (GAA) nanowire n-MOSFETs (n-NWFETs) are studied using coupled 3-D statistical device simulations considering quantum corrected room temperature drift-diffusion transport. The impact of metal-gate crystal grain size on linear and saturation mode \(V_{T}\) variability are analyzed. The \(V_{T}\) mismatch study predicts lower mismatch figure of merit ( \(A_{\rm VT}\) ) in TiN-gated Si GAA n-NWFETs compared with the reported experimental mismatch data for TiN-gated Si FinFETs.

Two FinFET fabrication processes are compared with simulation: the conventional fin-first process and the novel fin-last process. With the fin-last process, more longitudinal strain can be incorporated into the channel from source and drain SiGe stressor than fin-first. pFET mobility advantage is 15% at fully-strained condition and with silicon recess. Maintaining vertical junction uniformity is the main challenge for fin-last. However, its impact on parasitic resistance and capacitances are small. Vertical junction non-uniformity is improved with source and drain recess and doping optimization.

The natural choice to achieve multiple threshold voltages (V th ) in fully-depleted devices is by choosing the appropriate gate workfunction for each device. However, this comes at the cost of significantly higher process complexity. The absence of a body contact in FinFETs and insensitivity to back-gate bias leaves the conventional channel doping approach as the most practical technique to achieve multiple V th . This choice, however, introduces a variable that is usually not considered in the context of fully depleted devices. For the first time, we demonstrate a multiple V th solution at relevant device geometries and gate pitch for the 22nm node. We investigated the impact of FinFET channel doping on relevant device parameters such as T inv , mobility, electrostatic control and V th mismatch. We also show that V th extraction by the “constant current” method could mislead the DIBL analysis of devices with greatly different channel mobility.

This paper describes the importance of bipolar current gain and diode ideality factor to predictions of single-event circuit responses. It then reports on measurements of parasitic bipolar transistors in 45 nm Silicon-on-Insulator (SOI) technology, and adjustments to the simulation model to match the measurements.

Hot-carrier degradation (HCI) in aggressively scaled undoped-body devices is carefully studied and compared for high-k/metal gate FINFETs and extremely thin silicon-on-insulator (ETSOI) transistors. We show that HCI involves different degradation mechanisms for silicon-on-insulator (SOI)-FINFETs and ETSOI devices though both are fabricated on undoped body. For FINFETs, the HC degradation correlated with interface trap generation in the channel region, whereas for ETSOI, trap generation and electron trapping in the spacer-nitride region were observed.

We present a new ETSOI CMOS integration scheme. The new process flow incorporates all benefits from our previous unipolar work. Only a single mask level is required to form raised source/drain (RSD) and extensions for both NFET and PFET. Another new feature of this work is the incorporation of two strain techniques to boost performance, (1) Si:C RSD for NFET and SiGe RSD for PFET, and (2) enhanced stress liner effect coupling with faceted RSD. Using the new flow and the stress boosters we demonstrate NFET and PFET drive currents of 640 and 490 µA/µm, respectively, at I off = 300 pA/µm, V DD = 0.9V, and L G = 25nm. Respectable device performance along with low GIDL makes these devices attractive for low power applications. Record low V T variability is achieved with A Vt of 1.25 mV·µm in our high-k/metal-gate ETSOI. The new process flow is also capable of supporting devices with multiple gate dielectric thicknesses as well as analog devices which are demonstrated with excellent transconductance and matching characteristics.

For the first time, we discuss the compatibility of stress proximity technique (SPT) with dual stress liner (DSL) in high-κ/metal gate (HK/MG) technology. The short-channel mobility enhancement and the drive current improvement brought by SPT have been demonstrated at 32nm technology node. With maintained short channel control and threshold voltage roll-off characteristics, SPT has achieved 7% drive current improvement for both nFET and pFET from the optimization of SPT with DSL.

We study multi-bit upsets (MBU) in 65 nm SOI SRAMs. Proton beam and thorium foil experiments demonstrate that SOI SRAMs have lower soft error rate than bulk SRAMs. Monte Carlo SER simulations show that SOI SRAMs have a lower fraction of MBU than bulk SRAMs. The probability of MBU correlates with the spacing of sensitive devices in neighboring cells.

Device technology scaling continues to deliver faster and smaller transistors, contributing to IBMs continued leadership in server systems. However, there is also a dark side to device technology scaling. As transistors shrink, the amount of charge required to change the logic state of a memory or a logic circuit (i.e. flip a 1 to a 0 and vice versa) also shrinks. This complication spurs continued effort at IBM to test, characterize, and mitigate these transient bit flips, so called soft errors. In this paper we survey our ongoing work in this realm and introduce our views on trends for soft errors in future device technologies.

Starting with the 45 nm node, a tradeoff between performance and density exists that will become more severe at the 32 nm node. An in-depth analysis of the impact of pitch and increased parasitics on device performance in the 32 nm node is presented. To counteract these effects, reduction of parasitics, gate length scaling, and aggressive stress engineering are necessary. Optimized layout using a "relaxed-pitch" approach is demonstrated to show up to a 15% improvement over conventional layout in ring oscillators. The lower parasitics of SOI provide an additional degree of freedom allowing relaxed pitch designs to enhance performance in critical paths. Simpler device isolation in SOI is also shown to be very beneficial in this generation leading to an improved cost/performance tradeoff compared to previous generations.

We demonstrate poly-Si/high-k gate stacks suitable for successful implementation in low power technologies. An optimized gate dielectric process was employed to suppress the large pFET threshold voltage shift commonly found with Hf-based gate dielectrics, reducing it to -0.2 V, while preserving pFET and nFET device performance.

Design and integration issues have been investigated for the hybrid orientation technology (HOT), i.e. device isolation, epitaxy and dopant implantation. Ring oscillators using HOT CMOS have been demonstrated for the first time, with L/sub poly/ about 85nm and t/sub ox/=2.2nm, resulting in 21% improvement compared with control CMOS on (100) orientations.

A novel vertical bipolar transistor on SOI is proposed and demonstrated. The transistor operates on the principle that the collector region is fully depleted so that the charge carriers travel laterally towards the collector reachthrough and contact after traversing the intrinsic base layer. The SOI silicon layer thickness is comparable to that used in SOI CMOS, and no subcollector layer or deep trench isolation are required. Simulated device characteristics are shown. The transistor is demonstrated in a polysilicon-emitter SiGe-base npn implementation on SOI with a 140-nm silicon layer. The fabricated npn bipolar transistors exhibit a BVceo of 4.2 V and a peak f/sub T/ of over 60 GHz.

Line edge roughness (LER) has been widely perceived to be one of the roadblocks to the continuing scaling of semiconductor devices. However, little evidence has been published on the impact of LER on device performance, particularly on the performance and the reliability of advanced interconnects. In this paper, we present such evidence from both the Front-End-Of-Line (FEOL) and Back-End-Of-Line (BEOL) standpoints. In the FEOL, we employed computer simulations to estimate the effects of LER on a number of performance parameters of sub-100nm transistors based on 2-dimensional and 3-dimensional device models. LER has been shown to affect both the average value and the variance of key device performance parameters for sub-100nm transistors. In the BEOL, we investigated the impact of LER on the performance of barrier layers in dual damascene copper interconnects. To this end, we emulated LER by roughening Si surfaces with controlled patterning by self-assembled diblock copolymers and reactive ion etching. In-situ time-resolved X-ray diffraction was used to study Cu diffusion through about 5nm Ta and TaN barrier layers deposited by plasma enhanced-atomic layer deposition (PE-ALD) on both smooth and rough surfaces. The X-ray diffraction results indicated that the surface roughness does not degrade barrier performance of the ALD Cu barriers. Mechanism of the roughness effects is also discussed. Line edge roughness is, however, expected to degrade copper interconnect performance by increasing copper electrical resistivity through enhanced electron surface scattering.

In order to improve the performance of carbon nanotube field effect transistors (CNFETs), a nanotube array should be used. For a densely packed array of nanotubes, screening by nearby tubes affects the capacitance per tube. The gate-to-channel capacitance for a nanotube array of three different gate electrode configurations was examined in this study. Simulation results show that a wrap-around gate gives the largest gate-to-channel capacitance among the three gate configurations. A bottom gate structure, in which carbon nanotubes are unpassivated, presents a distinct electrostatic disadvantage of the weakest gate control. For a top gate structure, we found that an optimum design point exists for the pitch, which is defined as the distance between the centers of adjacent nanotubes, to get the largest gate capacitance per unit area.

The ultra-thin gate oxide required for the 0.13 /spl mu/m generation and beyond introduces a significant amount of gate-to-body tunneling current. The gate current modulates the body voltage and therefore the history effect. This paper discusses several methods to minimize the impact of gate current, which can cause excessive history effect in 0.10 /spl mu/m SOI CMOS. Our result demonstrates that the combination of high gate leakage and small junction capacitance can enhance circuit performance due to beneficial gate coupling. Ultra-low junction capacitance can be achieved by aggressive SOI thickness scaling, though, the proximity of source/drain extension and channel depletion to the buried oxide complicates device design and modeling.

In this paper, we present a fully-coupled and self-consistent continuum based three-dimensional numerical analysis to understand hot carrier and device self-heating effects for device-circuit co-optimization in Si gate-all-around nanowire FETs. We employ three-moment based energy transport formulations and two-dimensional quantum confinement effects to demonstrate negative differential conductivity in Si nanowire FETs and assess its impact on a CMOS inverter and three-stage ring oscillator. We show that strong two-dimensional quantum confinement yields volume inversion conditions in Si nanowire FETs and surround gate geometry enables better short-channel effect control. We find that hot carrier and self-heating effects can degrade ON-state current in Si nanowire FETs and severely limit the logic circuit performance due to the introduction of higher signal propagation delays. (C) 2014 The Japan Society of Applied Physics

We propose a mobility extraction methodology for metal-oxide-semiconductor field effect transistors with extremely scaled equivalent oxide thickness (EOT) below 1 nm. In conventional split C-V method, extracted mobility shows strong dependence on drain bias. As EOT scales to the requirements of 22 nm node and beyond, the phenomenon becomes more pronounced and causes bigger errors in mobility determination. We studied the physical origin of the extracted mobility dependence on drain bias by technology computer aided design electrostatics modeling and electrical characterization. A methodology is proposed and verified for intrinsic effective mobility determination for devices with EOT down to 0.6 nm.