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Ultra-thin epitaxially grown Si layers have been used for Ge surface passivation in CMOS devices utilizing standard silicon SiO2/HfO2 gate stack. In this work, we propose a high-k TmSiO interfacial layer, which has shown excellent performance on Si, instead of the chemical SiO2. We successfully transfer a TmSiO/Tm2O3/HfO2 gate stack from silicon to Si-passivated Ge devices, yielding interface state density of 3·1011 eV-1cm-2, which is comparable to GeOx passivation. Moreover, Si-capped Ge gates with TmSiO interfacial layer achieve significant improvement in oxide trap density compared to GeOx passivation, exhibiting a potential for superior reliability. We further investigate the robustness of Si layer growth process and show that small (±3˚C) variations of growth temperature can be detrimental to the interface state density of the gate stacks.

Fully depleted silicon-on-insulator (FDSOI) CMOS with thick buried oxide (BOX) can operate at higher temperatures compared to bulk CMOS. This work demonstrates, both experimentally and through simulations, that the subthreshold characteristics (off-state leakage current, I leak and subthreshold swing, SS) are greatly improved at high temperatures by reducing the Si thickness (t Si ) in FDSOI CMOS. Fabricated N and PFET devices exhibit low I leak leak . With proper gate electrodes FDSOI CMOS can achieve an I off < 1nA/μm at 300 °C for both P and NFETs. This result shows that FDSOI CMOS can find use as low power control logic at high temperatures.

This paper presents our in-house fabricated 4H-SiC n-p-n phototransistors. The wafer mapping of the phototransistor on two wafers shows a mean maximum forward current gain (βFmax) of 100 at 25 °C. The phototransistor with the highest βFmax of 113 has been characterized from room temperature to 500 °C. βFmax drops to 51 at 400 °C and remains the same at 500 °C. The photocurrent gain of the phototransistor is 3.9 at 25 °C and increases to 14 at 500 °C under the 365 nm UV light with the optical power of 0.31 mW. The processing of the phototransistor is same to our 4H-SiC-based bipolar integrated circuits, so it is a promising candidate for 4H-SiC opto-electronics on-chip integration.

Silicon nanowire (SiNW) biosensors have received a special attention from the research community due to its ability to detect a range of species. The nano feature size of the SiNW has been exploited to fabricate small, low-cost, robust, portable, real-time read-out biosensors. These sensors are manufactured by two methods – top-down or bottom-up. Instead of the bottom-up method, the top-down approach is widely used due to its compatibility with complementary metal-oxide semiconductor (CMOS) process and scope of mass production. However, in the top-down method, the post fabrication microfluidic channel integration to access the SiNW test site remains complex and challenging. Since the nanosensor is expected to operate in a bio environment, it is essential to passivate the metal electrodes while pathways have to be made to access the test site. In this paper, we present a relatively easier method to access the SiNW test site without employing complex microfluidic channels while achieving leakage free passivation of metal electrodes and preserving the integrity of the nanosensor. This is accomplished in the last step of the manufacturing process by employing a lithography mask and reactive ion etching (RIE). HfO2 integrated crystalline silicon nanosensors are manufactured using novel top-down front end of line (FEOL) sidewall transfer lithography (STL) process. HfO2 acts as an etch stop layer while performing RIE in the last step to access the sensor test site. The 100 mm wafer scale results of 20 nm × 60 nm × 6 μm (H x W x L) p-type nanosensors shows an average Ion/Ioff ≥ 105 with maximum turn-on voltage of −4 V and uniform subthreshold slope of 70 mV/dec. In comparison with sensors encapsulated with SiO2, the HfO2 integrated nanosensors were found to improve the threshold voltage variation by 50%. Based on this work, the HfO2 integrated SiNW demonstrates good stability for biosensing application.

This letter presents the design, fabrication, and characterization of a 4H-SiC n-p-n bipolar junction transistor as a switch controlling an on-chip integrated p-i-n photodiode. The transistor and photodiode share the same epitaxial layers and topside contacts for each terminal. By connecting the collector of the transistor and the anode of the photodiode, the photo current from the photodiode is switched off at low base voltage (cutoff region of the transistor) and switched on at high base voltage (saturation region of the transistor). The transfer voltage of the circuit decreases as the ambient temperature increases (2 mV/°C). Both the on-state and off-state current of the circuit have a positive temperature coefficient and the on/off ratio is >80 at temperature ranged from 25 °C to 400 °C. It is proposed that the on/off ratio can be increased by ~1000 times by adding a light blocking layer on the transistor to reduce light induced off-state current in the circuit.

Field effect transistors (FETs) based on networks of randomly oriented Si nanowires (Si nanonets or Si NNs) were biomodified using Thrombin Binding Aptamer (TBA&ndash, 15) probe with the final objective to sense thrombin by electrical detection. In this work, the impact of the biomodification on the electrical properties of the Si NN&ndash, FETs was studied. First, the results that were obtained for the optimization of the (3-Glycidyloxypropyl)trimethoxysilane (GOPS)-based biofunctionalization process by using UV radiation are reported. The biofunctionalized devices were analyzed by atomic force microscopy (AFM) and scanning transmission electron microscopy (STEM), proving that TBA&ndash, 15 probes were properly grafted on the surface of the devices, and by means of epifluorescence microscopy it was possible to demonstrate that the UV-assisted GOPS-based functionalization notably improves the homogeneity of the surface DNA distribution. Later, the electrical characteristics of 80 devices were analyzed before and after the biofunctionalization process, indicating that the results are highly dependent on the experimental protocol. We found that the TBA&ndash, 15 hybridization capacity with its complementary strand is time dependent and that the transfer characteristics of the Si NN&ndash, FETs obtained after the TBA&ndash, 15 probe grafting are also time dependent. These results help to elucidate and define the experimental precautions that must be taken into account to fabricate reproducible devices.

In this work we study the epitaxial Si growth with Si2H6 for Ge surface passivation in CMOS devices. The Si-caps are grown on Ge in the hydrogen desorption limited regime at a nominal temperature of 400 °C. We evaluate the process window for the interface state density and show that there is an optimal Si-cap thickness between 8 and 9 monolayers for Dit < 5·1011 cm−2 eV−1. Moreover, we discuss the strong impact of the Si-cap growth time and temperature on the interface state density, which arises from the Si thickness dependence on these growth parameters. Furthermore, we successfully transfer a TmSiO/Tm2O3/HfO2 gate stack process from Si to Ge devices with optimized Si-cap, yielding interface state density of 3·1011 eV−1 cm−2 and a significant improvement in oxide trap density compared to GeOx passivation.

Processing techniques for 4H-SiC devices and circuits are optimized. The SiC mesa etching process has a variation of $< 5$% over the wafer. The average n-type contact resistivity is $1.15 \times 10 ^{-6}$ Ohm. cm2. The fabricated devices and circuits with one-layer metal interconnect have high yield with no need of chemical-mechanical planarization process. More complex circuits with two-layer metal interconnect achieve high yield by applying chemical-mechanical planarization process.

Novel materials are being aggressively researched for integration in high-k/metal gate CMOS technology, as innovations in the gate stacks are necessary to sustain scaling toward the end of the roadmap. In this paper, we discuss thulium silicate as a candidate dielectric for integration as interfacial layer, focusing on compatibility with the requirements in terms of both process integration and effects on electrical device characteristics. In particular, we demonstrate that thulium silicate provides advantages over conventional chemical oxide interfacial layers in terms of scalability and channel mobility.

Low-frequency noise measurements were performed on n-channel MOSFETs with a novel ultra-low 0.3-nm equivalent-oxide-thickness (EOT) interfacial layer (TmSiO) and two different bulk high- $k$ dielectrics (Tm2O3 and HfO2). The MOSFETs were fabricated in a gate-last process and the total gate-stack EOT was 1.2 and 0.65 nm for the Tm2O3 and HfO2 samples, respectively. In general, both gate-stacks resulted in 1/ $f$ type of noise spectra and noise levels comparable with the conventional SiO2/HfO2 devices with similar EOTs. The extracted average effective oxide trap density was $2.5\times 10^{17}$ and $1.5\times 10^{17}$ cm $^{\mathrm {-3}}$ eV $^{\mathrm {-1}}$ for TmSiO/HfO2 and TmSiO/Tm2O3, respectively. Therefore, the best noise performance was observed for the gate-stack with Tm2O3 bulk high- $k$ layer and we suggest that the interface free single-layer atomic layer deposition (ALD) fabrication scheme could explain this.

Germanium is considered as a high mobility channel material for its potential to be introduced in future CMOS technology nodes. Ge surface passivation with a thin silicon layer (Si-cap) has been shown to be efficient for pFETs because of a sufficient valence band offset between Ge and Si-cap, which confines the holes in the Ge layer. Strained Ge pFinFETs outperforming Si pFinFETs due to four times higher mobility have been demonstrated using Si-cap process [1]. Interfacial defects can be further passivated with a high-pressure anneal in H2 resulting in reduced sub-threshold swing and increased mobility in Ge nanowires [2]. Moreover, by using a Si-cap, Negative-bias temperature instability reliability is improved compared to GeOx passivation because of the energy decoupling between holes and defects in SiO2/HfO2 gate stack [3]. However, a Si-cap process poses gate stack scalability issues because in order to achieve sufficient surface passivation, the Si-cap thickness cannot be scaled. An introduction of a high-k interfacial layer instead of a chemical oxide SiO2 could potentially help to scale down equivalent oxide thickness. Integrating thulium silicate (TmSiO) as a replacement of the SiO2 interfacial layer has been demonstrated on silicon, and a hole and electron mobility enhancement compared to SiO2/HfO2 gate stacks has been achieved for an equivalent oxide thickness (EOT) < 1 nm [4]. Moreover, we have previously displayed the compatibility of Tm2O3 with Ge by demonstrating GeOx/Tm2O3 gate stacks with interface state density Dit < 5·1011 eV-1cm-2 [5]. In this work, we integrate TmSiO with a Si-cap process to achieve Dit comparable to GeO2 passivation. In order to evaluate Ge/Si/TmSiO interfaces, MOS capacitors (MOSCAPs) were fabricated on n-type Ge strain relaxed buffers epitaxially grown on n-type Si wafers in a two-step process using GeH4 precursor [6]. Si-caps of different thicknesses were grown at 400 °C using Si2H6. Si growth was confirmed by ellipsometry spectroscopy and testing that the surface is hydrophobic. While trying to keep the Si-cap exposure to air to a minimum, 400 nm PECVD SiO2 was deposited and active areas were defined. After removing the remaining SiO2 from the active areas with 1 % HF, Tm2O3 was deposited by atomic layer deposition (ALD) at 225 °C. Rapid thermal anneal at 550 °C for 60 s in N2 was then employed to form TmSiO layer. High-k HfO2 was deposited by ALD at 350 °C followed by a post deposition anneal in O3 for 10 min. TiN gate metal was deposited at 425 °C by ALD and 500 nm Al was deposited by sputtering for probing purposes. After patterning, the samples were subjected to a forming gas anneal of 10% H2 in N2 at 400 °C for 30 min. Reference MOSCAPs with Ge/GeOx/Tm2O3/HfO2 gate stacks were also fabricated as described in [5] with addition of ALD HfO2. Interface state density in the midgap of Ge/Si/TmSiO/Tm2O3/HfO2 gate stacks was evaluated by CV measurements where measured CV characteristics where compared to calculated ones assuming a parabolic Dit distribution. Dit highly depends on Si-cap thickness, as displayed in Fig. 1. An optimal Si-cap thickness corresponding to 40-50 min deposition time provides Dit at midgap ~5·1011 cm-2eV-1 at CET of 4 nm. Reference MOSCAPs with Ge/GeOx/Tm2O3/HfO2 gates exhibit similar Dit of 4-5·1011 cm-2eV-1. Interface state density distribution within the band gap of Ge/Si/TmSiO interface with 40 min Si-cap deposition time was evaluated using the conductance method at different temperatures and is displayed in Fig. 2. Dit in the midgap is in agreement with the results obtained from CV measurements, and increases towards the valence and conduction band edges. The oxide trapped charge Qox of 2.5·1010 cm-2 (40 times lower than in the Ge reference devices without Si-cap) was determined from CV measurements and corresponds to only 5 mV hysteresis showing the potential of superior reliability. A Si-cap process with high-k TmSiO interface has been demonstrated on Ge MOS devices. A low Dit comparable to GeOx passivation has been shown. In addition, devices with TmSiO potentially have a superior reliability vs GeOx devices due to low oxide trapped charge density. References: [1] J. Mitard et al., Dig. Tech. Pap. - Symp. VLSI Technol., vol. 2016–Septe, 1–2, 2016. [2] H. Arimura et al., 2017 Symposium on VLSI Technology, 2017, T196–T197. [3] J. Franco et al., 2013 Int. Electron Devices Meet., 397–400, 2013. [4] E. Dentoni Litta et al., Eur. Solid-State Device Res. Conf., vol. 2, 155–158, 2013. [5] L. Žurauskaitė et al., ECS Trans., vol. 86, no. 7, 67–73, Jul. 2018. [6] A. Abedin et al., ECS Trans., vol. 75, no. 8, 615–621, 2016. Figure 1

Herein, results from noise and dark current density studies on InAs/GaSb type-II superlattice IR detectors are presented. The activation energy of the dark current density is used to identify the d ...

The p-i-n ultraviolet (UV) photodiodes based on 4H-SiC have been fabricated and characterized from room temperature (RT) to 550 °C. Due to bandgap narrowing at higher temperatures, the photocurrent of the photodiode increases by 9 times at 365 nm and reduces by 2.6 times at 275 nm from RT to 550 °C. Moreover, a 4H-SiC p-i-n photodiode array has been fabricated. Each column and row of the array is separately connected by two-layer metallization.

Germanium (Ge) has been intensively investigated as a high-mobility channel material alternative to silicon (Si). A high quality Ge/dielectric interface with interface state density Dit compared to Si is required for competitive device performance. GeO2 has been identified as potential candidate for an interfacial layer (IL) due to effective Ge surface passivation with Dit in the range of 1011 cm-2eV-1 [1]. However, in order to achieve scaled effective oxide thickness (EOT) a combination of GeO2 IL and a high-k dielectric is needed. Low interface state density in the range of 1011 cm-2eV-1 has been achieved while employing Al2O3 barrier [2] as well as rare earth oxides such as Y2O3 [3]. Rare-earth thulium oxide (Tm2O3) provides high dielectric constant k~16 [4] and sufficient valence (3.05 eV) and conduction (2.05 eV) band offsets [5] for a high-k dielectric layer on Ge. In this work Ge/GeOx/Tm2O3 interface quality and the impact of post deposition anneal ambient are investigated. Metal oxide semiconductor (MOS) capacitors were fabricated to evaluate Ge/GeOx/Tm2O3 gate stacks. After n-Ge substrate clean (acetone, propanol and O2 plasma) and native germanium oxide removal with aqueous HF and HCl solutions the samples were immediately loaded into the rapid thermal anneal (RTA) chamber where oxidation was carried out at 550 °C for 5 s to 5 min. The temperature in the chamber is controlled by a pyrometer which is calibrated to a Si wafer, and oxidation is performed by placing a Ge substrate piece on a Si carrier wafer. The temperature of the Ge sample is thus lower than that of the Si wafer. After oxidation the samples were loaded to atomic layer deposition (ALD) chamber where 40 cycles (~7 nm) of Tm2O3 were deposited using TmCp3 and H2O as precursors. Then Ge/GeO2/Tm2O3 gate stacks were annealed in different ambient (O2, O3, N2 and H2/N2) and temperatures (400 - 550 °C). Reference samples without Tm2O3 deposition or without post deposition anneal (PDA) were also fabricated. Al gate metal was deposited by physical vapor deposition and patterned. MOS capacitors were electrically characterized with capacitance-voltage (CV) measurements. Interface state density in the midgap was evaluated from CV curves using a method described in [6]. X-ray photoelectron spectroscopy (XPS) was performed on some samples using Al Kα X-ray (1486.6 eV) source and PSP Vacuum Technology electron energy analyser. Electrical properties of thermally grown Ge/GeO2 interfaces were evaluated and low interface state density Dit < 5·1011 cm-2eV-1 in the midgap was extracted from CV measurements. The influence of Tm2O3 deposition on high-quality Ge/GeO2 interfaces was then determined. A degradation of the interface quality after the deposition was observed as displayed in Fig. 1. Dit is higher for thinner underlying GeOx layer and seems to saturate to ~9·1011 cm-2eV-1 for thick layers. A series of post deposition anneals in different ambient and temperatures were performed on Ge/GeOx/Tm2O3 gate stacks in order to investigate the influence on the interface state density and capacitance equivalent thickness (CET). The results are shown in Fig. 2. It can be seen that a temperature of 500 °C or higher and O2 ambient is needed to sufficiently reduce Dit, when values as low as 2·1011 cm-2eV-1 can be reached. XPS measurement was performed on Ge/GeOx/Tm2O3 gate stack with O2 PDA at 500 °C and the obtained spectrum is shown in Fig. 3. The difference between the GeOx 3d5/2 peak and Ge0 3d5/2 peak is 2.7 eV which corresponds to Ge3+ oxidation state. This result is consistent with previously reported XPS results on Ge/GeOx/Al2O3 stacks [7] and suggests that Ge3+ oxidation state provides the low Dit values of Ge/GeOx/Tm2O3 gate stacks. Tm2O3 integrated with GeO2 and O2 PDA is a viable candidate for Ge MOS devices due to low interface state density of ~2·1011 cm-2eV-1 which is correlated to Ge3+ oxidation state. A further investigation of O2 PDA time in terms of the trade-off between Dit and CET will be reported. References [1] H. Matsubara et al., Appl. Phys. Lett., vol. 93, no. 3, p. 32104, 2008. [2] R. Zhang et al., IEEE Trans. Electron Devices, vol. 61, no. 2, pp. 416–422, 2014. [3] C. H. Lee et al., Tech. Dig. - Int. Electron Devices Meet. IEDM, pp. 40–43, 2013. [4] E. Dentoni Litta et al., J. Electrochem. Soc., vol. 160, no. 11, pp. D538–D542, 2013. [5] I. Z. Mitrovic et al., J. Appl. Phys., 2015. [6] L. Zurauskaite et al., EDTM, pp. 164–166, 2017. [7] X. Wang et al., Appl. Surf. Sci., vol. 357, pp. 1857–1862, 2015. Figure 1

The placement of bottom tier blocks under top-tierinductors could significantly improve the area-efficiency of M3DRF/AMS circuits, paving the way for new applications of thisintegration technology. This work investigates the potential ofplacing digital blocks in the bottom tier, underneath top tierinductors. A design-technology co-optimization flow is appliedand a number of design guidelines are suggested. These guidelinesensure high electromagnetic isolation between the two tiers, withminimum penalties on the loading of bottom tier wires, as wellas on the inductor’s performance. QC 20181008

High-k interfacial layers have been proposed as a way to extend the scalability of Hf-based high-k/metal gate CMOS technology, which is currently limited by strong degradations in threshold voltage ...

Integration of a high- $k$ interfacial layer (IL) is a promising technological solution to improve the scalability of high- $k$ /metal gate CMOS technology. We have previously demonstrated a CMOS-compatible integration scheme for thulium silicate (TmSiO) IL and shown excellent characteristics in terms of equivalent oxide thickness (EOT), interface state density, channel mobility, and threshold voltage control. Here, we report on optimized annealing conditions leading to gate leakage current density comparable with state-of-the-art SiO x /HfO2 nFETs (0.7 A/cm $^{2}$ at 1 V gate bias) at sub-nm EOT (as low as 0.6 nm), with near-symmetric threshold voltages (0.5 V for nFETs and −0.4 V for pFETs). We demonstrate an excellent performance benefit of the TmSiO/HfO2 stack, i.e., improved channel mobility over SiO x /HfO2 dielectric stacks, demonstrating high-field electron and hole mobility of 230 and 70 cm $^{2}$ /Vs, respectively, after forming gas anneal at EOT = 0.8 nm. Finally, the reliability of the TmSiO/HfO2/TiN gate stack is investigated, demonstrating 10-year expected lifetimes for both oxide integrity and threshold voltage stability at an operating voltage of 0.9 V.

A low temperature (T max =350 °C) process for Ge on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this work. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding, and an etch-back process using Si 0 . 5 Ge 0 . 5 as an etch-stop layer. Using this technique, GOI substrates with surface roughness below 0.5 nm, thickness nonuniformity of less than 3 nm, and residual p-type doping of less than 1016 cm−3 are achieved. Ge pFETs are fabricated (T max =600 °C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of −0.18 V and 60% higher mobility than the SOI pFET reference devices.

Ultraviolet (UV) detection is important in astronomy, combustion detections and medical analysis. Solid-state UV detectors based on wide band gap semiconductors, such as 4H-SiC, are widely studied because of their excellent electrical properties [1]. 4H-SiC based UV detectors are solar blind and can be applied in extremely high temperature environments [2]. However, the state-of-art 4H-SiC photodetectors still have large sizes (>10000 μm2), which are not suitable to be integrated into high resolution UV photography sensors. To build a full-frame UV imaging sensor containing megapixels, photodiodes smaller than 20 μm by side are necessary. Here, we report the fabrication and characterization of 4H-SiC p-i-n photodiodes with mesa areas scaled from 40000 μm2 to 400 μm2. The relationships between the parameters and the areas of the photodiodes are discussed. The photodiodes are fully functional from room temperature (RT) to 500 °C.

This work demonstrates high quality Ge/GeO 2 interfaces fabricated by O 2 RTA that are degraded by a good quality SiO 2 layer deposited by ALD. However, neither O 3 and H 2 O precursors commonly used during subsequent high-k ALDs nor Si precursor AP-LTO-330 do not degrade the interface. Thus Dit increase after SiO 2 deposition is likely due to intermixing. Therefore, the effect of subsequent ALDs on the interface quality has to be considered while designing Ge-based gate stacks.

An alternative route to continue the trend of scaling of CMOS technology is to implement novel channel materials with superior transport properties. Germanium has high intrinsic mobilities for both electrons (3900 cm2/Vs) and holes (1900 cm2/Vs), and is compatible with Si process technology, making it a suitable channel material for low power, high performance devices. The smaller band gap of Ge (0.67 eV) potentially allows for lower contact resistances compared to Si due to a reduced barrier height, and hence is more suitable for voltage scaling. A challenging task is the formation of a high-quality gate stack with low interface trap density and sub-nm equivalent oxide thickness (EOT) to maintain the intrinsically high performance of Ge. The peak electron mobility has been dramatically improved for Ge MOSFETs in recent years [1,2], largely achieved by improving the quality of GeO2/Ge interface. Although thermally grown GeO2 is the most natural choice, its inherent shortcomings still remain, such as: high water solubility, low desorption temperature (~400°C), low dielectric constant (~6); unconventional growth methods. Since the dielectric constant of GeO2 is low it cannot be used as the gate dielectric for aggressively scaled devices. The focus is on high-k dielectric (k>20) for sub-nm EOT scaling. The Liverpool group has been interested in two possible routes for Ge interface engineering: (i) using high-k materials that are intimate with Ge, such as La2O3 and Y2O3, and (ii) introducing a robust ultra-thin high-k interfacial layer (IL) barrier, such as Al2O3 and Tm2O3. Concerning the first route, high reactivity of Ge with high-k allows for germanate IL formation, which role is two-fold: to reduce the interface states, and to suppress the GeO desorption at the interface. The second route involves the use of ultra-thin barrier layers, Al2O3 and Tm2O3, as oxides highly resistant to oxygen diffusion and to reaction with Ge. The rare-earth metals (La, Y, Tm) tend to possess multiple valency, such as +2 and +3 oxidation states, that can provide effective passivation of electrically active defects. Both routes lead to achieving a GeOx-free gate stack with effective Ge surface passivation. We will present an overview study of physical and electrical properties of La2O3/Ge, Y2O3/Ge, Tm2O3/Ge, Al2O3/Ge and HfO2/Al2O3/GeO2/Ge gate stacks. The interfacial composition, valence band offset, uniformity, thickness, band gap, crystallinity, dielectric function and absorption features will be shown, as ascertained using X-ray photoelectron spectroscopy, X-ray diffraction, high resolution transmission electron microscopy, medium energy ion scattering and ultra violet variable angle spectroscopic ellipsometry. The correlation of these results with electrical characterization data, will make a case for Ge interface engineering with rare-earth inclusion as a viable route to achieve high performance Ge CMOS. Acknowledgement: the authors thank the EPSRC (UK) and the EU (OSIRIS and ESTEEM2 projects) for funding. [1] S. Takagi et al., Microelectron. Eng. 109, 389 (2013); [2] A. Toriumi et al. IEEE IEDM Tech. Dig., 646 (2011).

Thulium oxide layers on germanium were investigated.The valence band offset was found to be 2.95eV.The band gap of thulium oxide was found to be 5.3eV from the Tauc method.A sub-band gap absorption at 3.2eV points to a bulk thulium oxide defect.A permittivity of 14 was derived from electrical measurements. This paper investigates the band line-up and optical properties (dielectric function) of Tm2O3/Ge gate stacks deposited by atomic layer deposition. X-ray photoelectron spectroscopy has been performed to ascertain the shallow core levels (Ge3d and Tm4d) in ultra-thin and bulk Tm2O3/Ge stacks as well as valence band maxima in Ge and bulk Tm2O3. The valence band offset of Tm2O3/Ge has been found to be 2.95?0.08eV. Vacuum ultra violet variable angle spectroscopic ellipsometry studies reveal the indirect band gap nature of Tm2O3, with the value extracted from the Tauc method of 5.3?0.1eV. A distinct absorption feature is observed at ~3.2eV below the band gap of Tm2O3, and clearly distinguished from the Si and Ge critical points. A dielectric constant of 14 to 15 has been derived from the electrical measurements on 5nm Tm2O3/epi Ge/Si gate stacks. The band line-up study of Tm2O3/Ge implies an acceptable barrier for holes (2.95eV) and electrons (greater than 1.7eV) for Ge MOSFET engineering.

A novel process for atomic layer deposition of thulium oxide (Tm2O3) has been developed, employing TmCp3 as metal precursor and H2O as oxidizing agent. The use of a highly reactive oorganometallic ...

This chapter focuses primarily on sequential 3D, since only the high interconnection density achieved in this case is capable of supporting a scaling path in the vertical dimension. The successful ...

International audience; 1D silicon nanowires (SiNW) are attractive for charge based DNA sensing applications due to their small size and large surface to volume ratio. An ideal portable biosensor is expected to have repeatable and reliable sensitivity, selectivity, low production cost and small feature size. Instead of using tools such as e-beam that are capital and time intensive, we propose a low cost CMOS self-aligned-double-patterning I-line lithography process to fabricate 60 nm wide SiNW. DNA probes are grafted on a thin dielectric layer that is deposited on top of the SiNW surface. Here we used HfO2 instead of the usual SiO2. Indeed, compared to SiO2, HfO2 has been reported to have higher amount of OH groups on its surface leading to enhanced signal quality. We also report preliminary biosensor characterizations. After HfO2 functionalization and single-stranded DNA probe grafting onto the SiNWs, the sensors were first put in contact with fluorophore labelled complementary DNA targets in order to test the efficiency of DNA hybridization optically. Then, a sequence of hybridization, de-hybridization and re-hybridization steps was followed by Id-Vg measurements in order to measure the electrical response of the sensors to target DNA as well as recycling capability. After each step, SiNW devices exhibited a threshold voltage shift larger than device-to-device dispersion, showing that both complementary DNA hybridization and de-hybridization can be electrically detected. These results are very encouraging as they open new frontiers for heterogeneous integration of liquid interacting array of nano sensors with CMOS circuits to fabricate a complete lab on chip.

Germanium, with its superior electron and hole mobility compared to Si, is considered as a channel material in future CMOS technology [1]. The band gap of Ge makes it attractive in optoelectronic devices. However, integration of crystalline Ge on Si wafers is challenging due to the high lattice mismatch, leading to misfit and threading dislocations in Ge strain relaxed buffers (SRBs) grown on Si. Threading dislocations reaching the device layer can degrade the carrier mobility and increase the junction leakage current of MOSFETs and photodetectors. Several groups have reported that threading dislocation density (TDD) can be reduced by implementing a two-step growth (Step 1: T~400°C, Step 2: T~600-800°C) and using post growth anneal and/or cyclic thermal annealing TDDs~107cm- 2 has been demonstrated for SRB thicknesses ~1µm [1]. Even lower TDDs~106cm-2 has been achieved by increasing the SRB thickness >3µm [2]. In this work, we show that further reduction of the Ge growth temperature during the initial step to less than 300°C together with Ge2H6 as precursor enables a 0.5µm thin Ge SRB with TDDs as low as 4·104cm- 2.The Ge SRB was grown on (100) oriented Si wafers by reduced pressure (20 torr) chemical vapor deposition (CVD) using Ge2H6 as precursor and H2 as carrier gas. Dopant sources were PH3 and B2H6 for n- and p-type Ge SRB, respectively. HF last Si wafers were loaded into the CVD reactor followed by a 2 min H2 bake at T=1050°C. The temperature was ramped down to 280°C and Ge2H6 was introduced in the chamber followed by a temperature ramp up to 300°C for 20 min growing a 40nm strained relaxed Ge layer. The temperature was ramped up to 600°C in H2 followed by the growth of a 460nm thick Ge layer. For comparison, a 3µm thick Ge SRB was deposited with the conventional method; i.e. first layer grown at T=400°Cfollowed by the second layer at T=600°C and post growth annealing at T=800°C.The grown Ge SRB was subjected to wet chemical etching using SECCO solution (K2Cr2O7:H2O:HF) in order to delineate the threading dislocations. TDD was determined by counting delineated defects on images obtained from dark field optical microscope, AFM and SEM. High Resolution Reciprocal Mapping (HRRLM) was used to compare crystalline quality and XTEM was implemented to image the defects at the interfaces. Surface morphology and roughness were investigated using AFM.Fig. 1 shows AFM images of the surface morphology for temperature ramped (T=280-300°C) Ge SRB (left image) and conventional (T=400°C) Ge SRB (right image). The images indicate that the strain relaxation occurred through pit formation in the temperature ramped Ge SRB while in the conventional Ge SRB, the strain relaxed through island and valley formation. Similar relaxation through pit formation has been found in Ge grown on Si at T=290°C [3]. The pits are formed in the first grown Ge layer at T=280-300ᵒC where the low temperature allows Ge growth in 2D mode instead of 3D. The 2D growth mode enables low TDD in the Ge layer grown at T=600°C. Fig. 2 shows dark field optical microscope images of the Ge SRB after delineation of the threading dislocations by SECCO etching. For the conventional 3µm thick Ge SRB (right image) a TDD~107cm-2 was measured. The Ge SRB with the temperature ramped (T=280-300°C) exhibits a comparably low TDD~4·104cm-2. Fig. 3 displays reported TDDs in grown Ge SRBs together with the TDDs achieved in this work. The conventionally 3µm thick Ge SRB (T=400°C) exhibits a TDD well in accordance with what has been reported in the literature. The Ge SRB grown with an initial temperature ramp (T=280-300°C) exhibits about 3 decades lower TDD at the same thickness compared to literature data.In conclusion, we have shown that by using Ge2H6 and optimizing the temperature profile of the initial Ge growth it is possible to grow a 0.5µm thin Ge SRB on Si with a threading dislocation density ~4·104cm-2without any post growth annealing. [1] H.-C. Luan, D. R. Lim, K. K. Lee, K. M. Chen, J. G. Sandland, K. Wada, and L. C. Kimerling, Appl. Phys. Lett., vol. 75, no. 1999, p. 2909, 1999. [2] Y. Yamamoto, P. Zaumseil, T. Arguirov, M. Kittler, and B. Tillack, Solid. State. Electron., vol. 60, no. 1, pp. 2–6, 2011. [3] B. W. Cheng, H. Y. Xue, D. Hu, G. Q. Han, Y. G. Zeng, A. Q. Bai, C. L. Xue, L. P. Luo, Y. H. Zuo, and Q. M. Wang, 5th Int. Conf. Gr. IV Photonics, GFP, pp. 140–142, 2008. Figure 1

Highlights ► Ge surface passivation by scalable multilayer of La2O3/ZrO2. ► LaxGeyOz interfacial layers thickness controllable by oxidation time. ► Forming gas annealing improves Dit down to 3 × 1011 eV−1 cm−2 in presence of LaxGeyOz interlayer. ► Trade-off between interface trap density and equivalent oxide thickness., The paper addresses the passivation of Germanium surfaces by using layered La2O3/ZrO2 high-k dielectrics deposited by Atomic Layer Deposition to be applied in Ge-based MOSFET devices. Improved electrical properties of these multilayered gate stacks exposed to oxidizing and reducing ambient during thermal post treatment in presence of thin Pt cap layers are demonstrated. The results suggest the formation of thin intermixed LaxGeyOz interfacial layers with thicknesses controllable by oxidation time. This formation is further investigated by XPS, EDX/EELS and TEM analysis. An additional reduction annealing treatment further improves the electrical properties of the gate dielectrics in contact with the Ge substrate. As a result low interface trap densities on (1 0 0) Ge down to 3 × 1011 eV−1 cm−2 are demonstrated. The formation of the high-k LaxGeyOz layer is in agreement with the oxide densification theory and may explain the improved interface trap densities. The scaling potential of the respective layered gate dielectrics used in Ge-based MOS-based device structures to EOT of 1.2 nm or below is discussed. A trade-off between improved interface trap density and a lowered equivalent oxide thickness is found.

The cross-bridge Kelvin resistor is a commonly used method for measuring contact resistivity (ρc). For low ρc, the measurement has to be corrected for systematic error using measurements of contact resistance, semiconductor sheet resistance, and device dimensions. However, it is not straightforward to estimate the propagation of random measurement error in the measured quantities on the extracted ρc. In this paper, a method is presented to quantify the effect of random measurement error on the accuracy of ρc extraction. This is accomplished by generalized error propagation curves that show the error in ρc caused by random measurement errors. Analysis shows that when the intrinsic resistance of the contact is smaller than the semiconductor sheet resistance, it becomes important to consider random error propagation. Comparison of literature data, where ρc

The paper presents the results of electrical characterization of MOS capacitors and SOI MOSFETs with novel high-κ LaLuO3 dielectric as a gate oxide. The energy distribution of interface state density at LaLuO3/Si interface is presented and typical maxima of 1.2×1011 eV–1cm–2 was found at about 0.25 eV from the silicon valence band. The output and transfer characteristics of the n- and p-MOSFET (channel length and width were 1 µm and 50 µm, respectively) are presented. The front channel mobility appeared to be 126 cm2V–1s–1 and 70 cm2V–1s–1 for n- and p-MOSFET, respectively. The front channel threshold voltages as well as the density of states at the back interface are presented.

The energy bandgap (Eg) of Ge effectively shifts toward lower energies by alloying with Sn atoms. Strain-relaxed (SR) GeSn layers with more than 8% Sn content assumes a direct bandgap and can be potentially used for highly-sensitive photodetectors for the short-wavelength infrared (SWIR) region (Eg0.9Sn0.1 layer through microstructuring and Ge under-etching. The GeSn layers were grown on a Ge-buffered Si wafer [3] in a reduced pressure chemical vapor deposition tool using digermane and tin tetrachloride as Ge and Sn precursors. Two batches of detectors were fabricated; one based on GeSn on Ge and the other one based on suspended GeSn layers. Photolithography and ICP dry etching were used for patterning the detectors and the Ge underneath were removed by anisotropic selective etching using CF4 gas. XRD and RBS measurements indicate Sn contents of more than 10% without any Sn out diffusion. Raman spectroscopy shows the strain relaxation through Ge under-etching and layer release. The temperature dependence dependent photoluminescence spectra shown in Fig. 1 is in accordance with a direct band gap transitions of the GeSn layers around 0.5 eV. The effects of layer suspension on the absorption spectra and the photo response of the detectors will be discussed in the presentation. Fig. 1) Temperature dependence photoluminescence spectra of GeSn layer with 12% Sn content Acknowledgements: This work was supported by the Swedish Foundation for Strategic Research (SSF) and Vetenskapsrådet (VR). References: [1] S. Wirths, R. Geiger, N. von den Driesch, G. Mussler, T. Stoica, S. Mantl, Z. Ikonic, M. Luysberg, S. Chiussi, J.M.Hartmann, H. Sigg, J. Faist, D. Buca & D. Grützmacher, Nature Photonics volume 9, pages 88–92 (2015). [2] S. Gupta, R. Chen, Y. Huang, Y. Kim, E. Sanchez, J. S. Harris, and K. C. Saraswat, Nano Letters 13 (8), 3783-3790 (2013). [3] A. Abedin, A. Asadollahi, K. Garidis, P.-E. Hellström and M. Östling, ECS Trans. volume 75, issue 8, 615-621 (2016). Figure 1

Experimental and modeling results are reported for high-performance strained-silicon heterojunction bipolar transistors (HBTs), comprising a tensile strained-Si emitter and a compressively strained Si0.7Ge0.3 base on top of a relaxed Si0.85Ge0.15 collector. By using a Si0.85Ge0.15 virtual substrate strain platform, it is possible to utilize a greater difference in energy band gaps between the base and the emitter without strain relaxation of the base layer. This leads to much higher gain, which can be traded off against lower base resistance. There is an improvement in the current gain β of 27 × over a conventional silicon bipolar transistor and 11× over a conventional SiGe HBT, which were processed as reference devices. The gain improvement is largely attributed to the difference in energy band gap between the emitter and the base, but the conduction band offset between the base and the collector is also important for the collector current level.

Strained Si is recognised as a necessary technology booster for the nanoelectronics regime. This work shows that high levels of stress attainable from globally strained Si/SiGe platforms can benefit gate leakage and reliability in addition to MOSFET channel mobility. Device self-heating due to the low thermal conductivity of SiGe is shown to be the dominating factor behind compromised performance gains in short channel strained Si/SiGe MOSFETs. Novel thin virtual substrates aimed at reducing self-heating effects are investigated. In addition to reducing self-heating effects, the thin virtual substrates provide further improvements to gate oxide integrity, reliability and lifetime compared with conventional thick virtual substrates. This is attributed to the lower surface roughness of the thin virtual substrates which arises due to the reduced interactions of strain-relieving misfit dislocations during thin virtual substrate growth. Good agreement between experimental data and physical models is demonstrated, enabling gate leakage mechanisms to be identified. The advantages and challenges of using globally strained Si/SiGe to advance MOS technology are discussed.

Today MOSFET devices are approaching gate lengths on the order of 10 nm. This sets extreme demands on gate patterning technique. This paper describes a side wall transfer lithography technique to pattern decananomeer MOSFETs or nanowires. A correlated line edge roughness leading to a very low line width roughness was demonstrated for the patterned gates. Moreover, the technology was shown to be robust and reproducible with high yield and uniformity suitable for mass fabrication. Finally, integration of the sidewall transfer lithography was performed in various novel MOSFET devices.

Mobility and low-frequency (LF) noise were studied in tensile strained Si n- and pMOSFETs fabricated on relaxed SiGe virtual substrates. Both the impact of the channel orientation ((110) or (100) o ...

We investigate the bonding and electrical insulation properties of oxide layers for use in 3D monolithic integration via direct wafer bonding. Low surface roughness layers deposited on 100 mm Si wafers by atomic layer deposition (ALD) at 200 °C–350 °C, provide with adequate layer transfer bonding interfaces. Wafer scale IV measurements were performed to investigate the leakage current. We demonstrate that ALD oxide can function as a reliable bonding surface and also exhibit leakage current values below the nA range. Both properties are important pillars for a successful 3D monolithic integration.

International audience; A comprehensive study of atomic-layer deposited thulium oxide (Tm2O3) on germanium has been conducted using x-ray photoelectron spectroscopy (XPS), vacuum ultra-violet variable angle spectroscopic ellipsometry, high-resolution transmission electron microscopy (HRTEM), and electron energy-loss spectroscopy. The valence band offset is found to be 3.05±0.2eV for Tm2O3/p-Ge from the Tm 4d centroid and Ge 3p3/2 charge-corrected XPS core-level spectra taken at different sputtering times of a single bulk thulium oxide sample. A negligible downward band bending of ∼0.12eV is observed during progressive differential charging of Tm 4d peaks. The optical band gap is estimated from the absorption edge and found to be 5.77eV with an apparent Urbach tail signifying band gap tailing at ∼5.3eV. The latter has been correlated to HRTEM and electron diffraction results corroborating the polycrystalline nature of the Tm2O3 films. The Tm2O3/Ge interface is found to be rather atomically abrupt with sub-nanometer thickness. In addition, the band line-up of reference GeO2/n-Ge stacks obtained by thermal oxidation has been discussed and derived. The observed low reactivity of thulium oxide on germanium as well as the high effective barriers for holes (∼3eV) and electrons (∼2eV) identify Tm2O3 as a strong contender for interfacial layer engineering in future generations of scaled high-κ gate stacks on Ge. © 2015 AIP Publishing LLC.

The reliability of gate oxides on bulk Si and strained Si (s-Si) has been evaluated using constant voltage stressing (CVS) to investigate their breakdown characteristics. The s-Si architectures exh ...

Directly accessible, ultralong, uniform platinum silicide nanowires in PtSi and Pt"2Si are mass-fabricated by combining a sidewall transfer lithography (STL) technology and a self-aligned silicide process. The STL technology is based on standard Si technology. The self-aligned platinum silicide (PtSi"x) process consists of two sequential steps in a single run: a silicidation step in N"2 to ensure a controllable silicide formation followed by an oxidation step in O"2 to form a reliable protective SiO"x layer on top of the grown PtSi"x. The achieved nanowires are characterised by a low resistivity: 26+/-3 and 34+/[email protected]@Wcm for the Pt"2Si- and PtSi-dominated nanowires.

This paper, presents a robust spacer technology for definition of deca-nanometer gate length MOSFETs. Conformal deposition, selective anisotropic dry-etching and selective removal of sacrificial layers enabled patterning of an oxide hard mask with deca-nanometer lines combined with structures defined with I-line lithography on a wafer. The spacer gate technology produces negligible topographies on the hard mask and no residual particles could be detected on the wafer. The line-width roughness of 40nm poly-Si gate lines was 4nm and the conductance of 200@mm long lines exhibited a standard deviation of 6% across a wafer. nMOSFETs with 45nm gate length exhibited controlled short-channel effects and the average maximum transconductance in saturation was 449@mS/@mm with a standard deviation of 3.7% across a wafer. The devices exhibited a cut-off frequency above 100GHz at a drain current of 315@mA/@mm. The physical and electrical results show that the employed spacer gate technology is robust and can define deca-nanometer nMOSFETs with high yield and good uniformity.

A new source/drain formation concept based on selective Si etching followed by selective regrowth of in situ B-doped Si(1-x)Ge(x)is presented. Both process steps are performed in the same reactor t ...

Ni-salicided MOSFETs with a gate stack of ALD Al2O3/HfO2/Al2O3 high-x dielectric and poly-SiGe gate electrode were fabricated. The Si pMOSFETs with an EOT of 1.7 nm showed an expected gate leakage ...

Low-frequency noise was characterized in Si0.7Ge0.3 surface channel pMOSFETs with ALD Al2O3/HfO2/Al2O3 stacks as gate dielectrics. The influences of surface treatment prior to ALD processing and ...