A robust spacer gate process for deca-nanometer high-frequency MOSFETs

This paper, presents a robust spacer technology for definition of deca-nanometer gate length MOSFETs. Conformal deposition, selective anisotropic dry-etching and selective removal of sacrificial layers enabled patterning of an oxide hard mask with deca-nanometer lines combined with structures defined with I-line lithography on a wafer. The spacer gate technology produces negligible topographies on the hard mask and no residual particles could be detected on the wafer. The line-width roughness of 40nm poly-Si gate lines was 4nm and the conductance of 200@mm long lines exhibited a standard deviation of 6% across a wafer. nMOSFETs with 45nm gate length exhibited controlled short-channel effects and the average maximum transconductance in saturation was 449@mS/@mm with a standard deviation of 3.7% across a wafer. The devices exhibited a cut-off frequency above 100GHz at a drain current of 315@mA/@mm. The physical and electrical results show that the employed spacer gate technology is robust and can define deca-nanometer nMOSFETs with high yield and good uniformity.