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CVD Co liners are of interest for back end of the line (BEOL) interconnects due to improved Cu interconnect gapfill, especially at narrow feature widths.1-4 The stability of Co liner during downstream BEOL processing is a concern that has been discussed with respect to chemical mechanical planarization (CMP),5-6but its behavior during Cu plating has received less attention. Since Co is less noble than Cu (and its oxide is unstable at low pH), an optimized BEOL metallization process is important to prevent Co liner loss during plated Cu fill. Insufficient Cu seed coverage could expose Co to oxidation and attack in the Cu electrolyte, compromising yield and reliability. In this study, we characterize the anodic dissolution behavior of thin PVD Cu/CVD Co bilayer films using linear sweep amperometry. The thin blanket seed layers are intended to mimic the sparse Cu seed coverage that might be present over a Co liner in a narrow dual damascene geometry. An example of this type of analysis is shown in Figure 1. The top figure (1a) shows the anodic polarization behavior of two separate electrode samples (plotted together), one for thick Co, another for thick Cu. The expected potential difference in the stripping peaks is observed, with Co dissolving at less anodic potentials. The middle (1b) and bottom (1c) figures show the behavior of bilayer electrodes having Cu overlayers of varying thickness. The Cu thickness clearly affects the polarization behavior of the underlying Co, with a fairly thick overlayer required to completely suppress early Co dissolution. The impact of these effects and other Cu chemistry aspects on the interconnect yield and reliability will be discussed. 1. T. Nogami, J. Maniscalco, A. Madan, P. Flaitz, P. DeHaven, C. Parks, L. Tai et al., In Interconnect Technology Conference (IITC), 2010 International, pp. 1-3. IEEE, 2010. 2. H. Shimizu, K. Sakoda, T. Momose, Y. Shimogaki, Japanese Journal of Applied Physics, 51, 05EB02-1 (2012). 3. A. H. Simon, T. Bolom, C. Niu, F. H. Baumann, C-K. Hu, C. Parks, J. Nag et al., In Reliability Physics Symposium (IRPS), 2013 IEEE International, pp. 3F-4. IEEE, 2013. 4. M. He, X. Zhang, T. Nogami, X. Lin, J. Kelly, H. Kim, T. Spooner, D. Edelstein, and L. Zhao, J. Electrochem. Soc., 160, (12) (2013): D3040-D3044. 5. N. Heylen, L. Yunlong, K. Kellens, L. Carbonell, H. Volders, G. Santoro, V. Gravey et al. In Interconnect Technology Conference (IITC), 2010 International, pp. 1-3. IEEE, 2010. 6. K. Tanwar, D. Canaperi, M. Lofaro, W. Tseng, R. Patlolla, C. Penny, and C. Waskiewicz, J. Electrochem. Soc., 160, D3247 (2013). This work was performed by the Research Alliance Teams at various IBM Research and Development facilities. Figure 1

Mechanisms of electromigration (EM) damage in Cu interconnects through various CMOS nodes are reviewed. Pure Cu and Cu alloy interconnects that were used down to 14 nm node can no longer satisfy the electrical current used for 10 nm node and beyond in high-performance ICs. Cu interconnects with a metal cap should be used. Cu interface diffusivity with EM activation energy of 1.6 eV was found to be the dominate EM factor in Cu lines with a Co liner and cap. The median lifetime of 7 or 10 nm node Cu with TaN/Co liner and Co cap is predicted to be over ten thousand years at 140°C with $1.5\times 10^{7}\mathrm{A}/\text{cm}^{2}$ . However, the resistivity size effect and the difficulty of scaling barrier/liner layer without defects can limit the Cu BEOL roadmap below the 7 nm node.

As BEOL pitch continues to aggressively scale, contributions from pattern dimension and edge placement constrict the available geometry of interconnects. In particular, the critical minimum insulator spacing which defines a technologies max operating voltage is now limited by Vx to Mx spacing. This spacing has historically been a challenge since the introduction of self-aligned vias due to the loss of CD and chamfer control in the non-self-aligned direction. As pitch continued to shrink from self-aligned via introduction around the 22 nm node, the fraction of via CD control and edge placement compared to the dielectric spacing between interconnects has continued to grow. Alone this trend could be combated by increasing the dielectric spacing, however, the exponential increase in Cu resistivity (under scaling) has forced BEOL technologies into strong line/space asymmetry to keep line resistance under control. At pitches below 32 nm these factors reach a tipping point, either design to exponentially increasing line resistance or lower the technology Vmax. Both approaches cause performance degradation to achieve pitch scaling

A fully aligned via (FAV) integration scheme is introduced and demonstrated at 36 nm metal pitch, with extendibility to beyond the 7 nm node. Selective chemistries were developed to recess Cu and W wires and their associated barrier liner materials, so as to create local topography with no adverse effects on these wiring levels or their dielectrics. Dielectric cap layers were optimized for excellent via RIE selectivity, to act as via guiding structures during subsequent level pattern definition. This combination mitigates via overlay and critical dimension (CD) errors. FAV integration can enable line/via area scaling for 70% lower line resistances and 30% larger via contact areas at the same node. Concurrently, FAV improves TDDB reliability through increased minimum insulator spacing, and EM reliability by maximizing via/wire contact area.

48 nm pitch dual damascene interconnects are patterned and filled with ruthenium. Ru interconnect has comparable high yield for line and via macros. Electrical results show minimal impact for via resistance and around 2 times higher line resistance. Resistivity and cross section area of Ru interconnects are measured by temperature coefficient of resistivity method and the area was verified by TEM. Reliability results show non-failure in electromigration and longer time dependent dielectric breakdown. Based on the data collected, Ru could be a metallization contender at linewidth of 16 nm and below.

Chip level electromigration (EM) reliability is determined by: 1) the element level EM failure probability used for design guideline generation; and 2) the distribution of EM elements against design limits. Balancing these two factors is critical for a chip design to achieve the best performance while maintaining chip level EM reliability. This paper discusses the relationship between element level and chip level EM failure probability and provides examples of EM evaluation of chip designs.

Through-Co self-forming-barrier (tCoSFB) metallization scheme is introduced, with Cu gap-fill capability down to 7 nm-node dimensions. Mn atoms from doped-seedlayer diffuse through CVD-Co wetting layer, to form TaMn O barrier, with integrity proven by vertical-trench triangular-voltage-sweep and barrier-oxidation tests. tCoSFB scheme enables 32% and 45% lower line and via resistance, respectively at 10 nm node dimensions, while achieving superior EM performance to competitive TaN/Co and TaN/Ru-based barriers.

In this paper we show that devices in scaled technologies could undergo self-heating (SH) even in the off-state when subjected to stress conditions that would in turn adversely impact product life-time. We present a detailed methodology in analyzing the impact of off-state SH, thus preventing unintentional overstressing during product stress-screening. We propose an analytical model for modeling this effect, verifying it against detailed TCAD simulations and actual hardware (HW) data from 14nm SOI FinFET technology. We show that the amount of off-state SH depends on the actual device size and the circuit layout. Additional temperature rise (deltaT) can increase ∼2.7x for 2-finger vs. 40-finger FETs. We demonstrate the SH impact on off-state hot-carrier-injection (HCI) induced degradation based on HW data. Finally, we analyze its impact on backend electromigration (EM) showing that median-time-to-fail (MTTF) can be reduced as much as 80% in large multi-finger (MF) FETs when off-state SH is taken into account.

In the advanced on-chip interconnect Technology, the interconnect reliability has been a subject of utmost importance. As the line width is reduced to the sub -micron range, the current carrying capability of the Cu interconnect lines becomes an important issue. This paper discusses the electromigration behavior of Cu interconnects passivated with low-k dielectrics. The influences of the cap dielectrics, the liner thickness, via /liner contact and multiple via on the EM lifetime are discussed. The data on the EM kinetics are also presented.

Electromigration lifetime and failure mechanism have been investigated for Cu/low-k interconnects at intermediate interconnect levels. It was observed that extrusion fails occurred mostly before resistance shift fails were detected. The activation energy for extrusion fails was determined to be 1.13 eV, comparable to the value of 0.99 eV for the resistance shift fails. This suggests the same failure mechanism for two failure modes: Cu mass transport primarily along the Cu/cap interface. The current exponent was extracted as 1.48 and 1.36 for extrusion fails and resistance shift fails, respectively. Physical failure analysis confirmed Cu extrusion near the anode and void formation at the cathode. Samples with improved pre-clean process before the cap deposition significantly suppressed EM induced extrusions, indicating a mechanically stronger Cu/cap interface. Furthermore, effective atomic sink at the anode end appeared to reduce the compressive stress buildup during EM, as it also significantly mitigated EM induced extrusion.

We present a fully-integrated SOI CMOS 22nm technology for a diverse array of high-performance applications including server microprocessors, memory controllers and ASICs. A pre-doped substrate enables scaling of this third generation of SOI deep-trench-based embedded DRAM for a dense high-performance memory hierarchy. Dual-Embedded stressor technology including SiGe and Si:C for improved carrier mobility in both PMOS and NMOS FETs is presented for the first time. A hierarchical BEOL with 15 levels of copper interconnect including self-aligned via processing delivers high performance with exceptional reliability.

This paper introduces a highly reliable Cu interconnect technology at the 32 nm node with CuMn alloy seed. A CuMn alloy liner seed process combined with a non-gouging liner has been integrated into the minimum-pitch wiring level. Stress migration fails with CuMn seed at plate-below-via structures were shut down by a non-gouging liner process. Integration with gouging liner and non-gouging liner is compared, and results of interaction with CuMn seed are discussed in this paper.

Electromigration results are described for a Dual Damascene structure with copper metallization and a low-k dielectric material. The failure times follow a bimodal lognormal behavior with early and late failures. Moreover, there is evidence of a threshold failure time such that each failure mode is represented by a 3-parameter lognormal distribution. It is found that the threshold failure time scales differently with current density from the median time to failure, which can be explained by considering two components of the electromigration lifetime: one controlled by void nucleation and the other controlled by void growth.

The study of low-k TDDB line space scaling is important for assuring robust reliability for new technologies. Although spacing effects due to line edge roughness (LER) on low-k TDDB lifetime were reported previously (Chen et al., 2007; Lloyd et al., 2007; Kim et al., 2007), there has been a lack of an analytical model with which to link line edge roughness to experimental TDDB data in a simple quantitative format. This work reports a thorough investigation into the low-k SiCOH line LER effect on low-k TDDB covering both experimental results and finite element modeling (FEM) simulations. The maximum electric field intensity as a result of sidewall LER bump was found to depend on the bump curvature. The decrease of low-k line spacing that resulted in a shorter TDDB lifetime even under the same applied electric field was then carefully analyzed. A simple analytical model of the effect of line edge roughness on TDDB failure time reduction is presented. This model was verified by experimental results. Additionally, a method to electrically quantify an overall line edge roughness is introduced.

A high performance 45nm BEOL technology with proven reliability is presented. This BEOL has a hierarchical architecture with up to 10 wiring levels with 5 in PECVD SiCOH (k=3.0), and 3 in a newly-developed advanced PECVD ultralow-k (ULK) porous SiCOH (k=2.4). Led by extensive circuit performance estimates, the detrimental impact of scaling on BEOL parasitics was overcome by strategic introduction of ULK at 2times wiring levels, and increased 1times wire aspect ratios in low-k, both done without compromising reliability. This design point maximizes system performance without adding significant risk, cost or complexity. The new ULK SiCOH film offers superior integration performance and mechanical properties at the expected k-value. The dual damascene scheme (non-poisoning, homogeneous ILD, no trench etch-stop or CMP polish-stop layers) was extended from prior generations for all wiring levels. Reliability of the 45 nm-scaled Cu wiring in both low-k and ULK levels are proven to meet the criteria of prior generations. Fundamental solutions are implemented which enable successful ULK chip-package interaction (CPI) reliability, including in the most aggressive organic flip-chip FCPBGA packages. This represents the first successful implementation of Cu/ULK BEOL to meet technology reliability qualification criteria

Damascene processing creates special features for copper interconnect electromigration (EM). Though the fast Cu diffusion path is along the interface between Cu and the top cap layer, the early EM fails are often associated with vias, either by voiding in the via (via depletion), or by voiding underneath the via (line depletion). While most of the early EM fails for via depletion are related to the liner quality in vias, for line depletion EM the contact configuration between the via and the underlying line is critical to the failure characteristics. The contact between the via and the line liner below can effectively prevent or minimize open-circuit type EM failures. Redundant vias can significantly improve the EM performance in both the median failure time (t/sub 50/) and the distribution shape (sigma, /spl sigma/), depending on the arrangement of these vias relative to the line below. This paper presents an EM study of Cu interconnects with various via/line contact configurations. Results from single via and multiple via contacts, with and without redundancy to the underlying lines, are discussed.

The reliability of a stacked via chain stressed under various thermal cycle conditions is described. The chain consists of Cu Dual Damascene metallization with SiLK (trademark of Dow Chemical) as the organic low-k dielectric. Failure analysis indicates that cracks form in the Cu vias during thermal cycle stress. Due to the presence of two failure modes, the thermal cycle statistical behavior is described by a bimodal lognormal failure distribution. The thermal cycle lifetime exhibits a strong dependence on the temperature range and a rather weak dependence, on the maximum temperature in the cycle. Evidence of a threshold temperature range below which thermal cycle fails should not occur as well as a correlation between the test structure yield and reliability are also reported.

The integration of dual damascene copper with fluorosilicate glass (FSC) at the 0.18 /spl mu/m technology node is described. The BEOL structure has been implemented for an advanced CMOS technology, and along with an SOI FEOL is being used for high performance logic and SRAM devices. Reliability and yield is shown to be equivalent to a similar technology without FSG. Key considerations in the development of this technology are presented.

Defect-free copper damascene plating becomes more and more challenging as the BEOL interconnects continues to scale. In addition to the challenge from the small critical dimension, the thin liner/seed required for the overall resistance imposes even more challenges to the plating. The coverage of the Cu seed at the thickness used can be poor on the sidewalls of trenches and vias. The discontinuous Cu seed and the exposed or oxidized Ta liner are generally associated with the slit voids, cluster voids defects from plating. Furthermore, a non-optimized PVD etch back and re-sputtering process or its bias power could also cause a much localized variation of Cu-seed thickness along the side walls. When a trench side wall locally misses Cu seed void can easily form due to the lack of Cu nucleation during the entry and pulse step of plating, which is observed as slit hollow metal defect as being exposed after CMP. However, when the lack of Cu-seed occurs on both sidewalls of a trench a single line open hollow metal (shown below) defect is often observed, which we called HMS1 defects. A typical PLY wafer map of HMS1 defect and its corresponding typical SEM review image (inset) is shown in Fig.1. Although this particular wafer shows the HMS1 defect signature spreading from 6:00-3:00 O’clock along the edge of the wafer, this defect signature can rotate 360 degree from wafer to wafer and/or lot to lot as shown by stacked map in Fig.1b. The stacked map also indicates that the density of HMS1 defects is high along the edge of the wafers at 6:00-3:00 O’clock position. Fig.2a-b shows a typical top down SEM images of HMS1 defect and its corresponding longitudinal cross-section TEM image respectively. Although the top surface shows the absence of the copper plating across the width of the line, its cross-sectional image confirms that copper was plated from the bottom of the trenches but stopped after the trench was partially filled. In this paper we will explain the mechanism of HMS1 defects formation and its modulation by co-optimization of Cu-seed process and plating entry condition. Detail failure analysis will also be presented to correlate the post plating defect with the localized absence of Cu-seed along the trench side wall where Cu did not nucleate during plating. The methodology in achieving a low defectivity on a wafer scale will be discussed. Fig.1 (a) shows a HMS1 PLY defect map on a single wafer and (b) shows stacked map of this defect from 20 lots Fig.2. (a) shows a typical top down HMS1 defect and (b) shows its corresponding x-section TEM image

Poor process controls may cause huge line spacing variation across a semiconductor wafer during back-end-of-the-line integration in advanced semiconductor integrated circuit fabrication. As a consequence, significant degradation in yield, performance, and reliability may be observed. Line spacing variation also imposes challenges for accurate time dependent dielectric breakdown reliability lifetime projection. In this paper, a nondestructive, fast electrical method for determining a line-to-line spacing of a semiconductor chip is proposed. The method includes experimentally determining a slope from capacitance measurement (kCA), experimentally determining a slope from current-voltage measurement (kSE), and finally determining a line-to-line spacing from the slope kCA and the slope kSE. The line-to-line spacing determined from this method shows an excellent agreement with constructional analysis data.