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2,317 results on '"PACS 85.42"'

1. SMART: Selective MAC zero-optimzation for neural network reliability under radiation

Author

Rajappa, Anuj Justus, Reiter, Philippe, Sartori, Tarso Kraemer Sarzi, Laurini, Luiz Henrique, Fourati, Hassen, Mercelis, Siegfried, Hellinckx, Peter, Possamai Bastos, Rodrigo, Internet Technology and Data Science Lab (IDLab), Universiteit Antwerpen = University of Antwerpen [Antwerpen]-Universiteit Gent = Ghent University (UGENT), Architectures and Methods for Resilient Systems (TIMA-AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Dynamics and Control of Networks (DANCE), Inria Grenoble - Rhône-Alpes, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria)-GIPSA Pôle Automatique et Diagnostic (GIPSA-PAD), Grenoble Images Parole Signal Automatique (GIPSA-lab), Université Grenoble Alpes (UGA)-Grenoble Images Parole Signal Automatique (GIPSA-lab), and Universiteit Antwerpen = University of Antwerpen [Antwerpen]

Subjects
radiation, MAC, PACS 85.42, sparsity, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, sparsity radiation MAC multiply-accumulate optimization, optimization, multiply-accumulate
Abstract

This work has been partially supported by: MultiRad (PAI project funded by Région Auvergne-Rhône-Alpes); IRT Nanoelec (ANR-10-AIRT-05) and LabEx PERSYVAL-Lab (ANR- 11-LABX-0025-01), both projects funded by the French program PIA; UGA/LPSC/GENESIS platform; Bourse de mobilité Génération IA 2030, funded by French embassy in Belgium; and MOVIQ (Mastering Onboard Vision Intelligence and Quality) project funded by Flanders Innovation and Entrepreneurship (VLAIO) and Flanders Space (VRI).; International audience

Published
2023

2. Oscillator Based Bio-Sensor for Skin Sweating Detection: A Feasibility Survey

Author

Srinivassane, Naveen, Saïd, Aïcha, Hameau, Frédéric, Vauché, Rémy, Podevin, Florence, Bourdel, Sylvain, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut des Matériaux, de Microélectronique et des Nanosciences de Provence (IM2NP), Aix Marseille Université (AMU)-Université de Toulon (UTLN)-Centre National de la Recherche Scientifique (CNRS), Reliable RF and Mixed-signal Systems (TIMA-RMS), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), and IEEE

Subjects
PACS 85.42, sweat sensor, voltage-controlled oscillator, dry skin, oscillation frequency, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, wet skin
Abstract

International audience; This paper is a feasibility survey of the design of an oscillator-based bio-sensor for skin physiological parameter detection. The sensor aims to detect stress through skin sweating measurement. The proposed architecture uses an oscillator coupled to an on-skin resonator. The oscillator is based on a cross coupled pair (CCP) which is directly connected to the resonator. The on-skin resonator has been designed to have an oscillation frequency sensitive to the sweat. Oscillator outputs are driven by two buffers that act as 50 Ω impedance matching. Two test benches, one with a dry skin and one with a wet skin, have been used for the study. The oscillation frequency of this oscillator is equal to 27.876 GHz for the dry skin, and 27.911 GHz for the wet one. The difference between the two oscillation frequencies, which is equal to 35 MHz, can be easily distinguished which validates the feasibility survey. The survey provides the sizing of each block and the simulated results in 55 nm BiCMOS technology.

Published
2023

3. 128-bit Addresses for the Masses (of Memory and Devices)

Author

Bacou, Mathieu, Chader, Adam, Deshpande, Chandana S., Fabre, Christian, Fuguet, César, Michaud, Pierre, Perais, Arthur, Pétrot, Frédéric, Thomas, Gaël, Tomasi Ribeiro, Eduardo, Télécom SudParis (TSP), System Level Synthesis (TIMA-SLS), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Département Systèmes et Circuits Intégrés Numériques (DSCIN), Laboratoire d'Intégration des Systèmes et des Technologies (LIST (CEA)), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-Institut National de Recherche en Informatique et en Automatique (Inria)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-IMT Atlantique (IMT Atlantique), and Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)

Subjects
PACS 85.42, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

International audience; The ever growing storage and memory needs in computer infrastructures makes 128-bit addresses a possible long-term solution to access vast swaths of data uniformly. In this abstract, we give our thoughts regarding what this would entail from a hardware/software perspective.

Published
2023

4. We had 64-bit, yes. What about second 64-bit?

Author

Bacou, Mathieu, Chader, Adam, Deshpande, Chandana S., Fabre, Christian, Fuguet, César, Michaud, Pierre, Perais, Arthur, Pétrot, Frédéric, Thomas, Gaël, Tomasi Ribeiro, Eduardo, Télécom SudParis (TSP), System Level Synthesis (TIMA-SLS), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Département Systèmes et Circuits Intégrés Numériques (DSCIN), Laboratoire d'Intégration des Systèmes et des Technologies (LIST (CEA)), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-Institut National de Recherche en Informatique et en Automatique (Inria)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-IMT Atlantique (IMT Atlantique), and Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)

Subjects
PACS 85.42, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

International audience; High-performance architectures are increasingly heterogeneous and incorporate often specialized hardware. We have first seen the generalization of GPUs in the most powerful machines, followed by FPGAs, and now by many other accelerators such as Tensor Processor Units (TPUs) for Deep Neural Networks, or variable precision FPUs. Recent hardware manufacturing trends make it very likely that specialization will not only persist, but increase. Manually managing this heterogeneity is complex and not maintainable. We therefore propose to revisit how we design both hardware and OS in order to better hide the heterogeneity. To ensure long term viability of our proposal, we propose to entertain the use of 128-bit addressing.

Published
2023

5. Low-Throughput Event-Based Image Sensors and Processing

Author

Fesquet, Laurent, Tran, Rosalie, Lesage, Xavier, Akrarai, Mohamed, Mancini, Stéphane, Sicard, Gilles, Circuits, Devices and System Integration (TIMA-CDSI), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), and IEEE

Subjects
time to first spike pixel, event-based image processing, event-based image sensor, low power, PACS 85.42, dynamic vision sensor, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, asynchronous circuit
Abstract

International audience; This paper presents new kinds of image sensors based on TFS (Time to First Spike) pixels and DVS (Dynamic Vision Sensor) pixels, which take advantage of non-uniform sampling and redundancy suppression to reduce the data throughput. The DVS pixels only detect a luminance variation, while TFS pixels quantized luminance by measuring the required time to cross a threshold. Such image sensors output requests through an Address Event Representation (AER), which helps to reduce the data stream The resulting event bitstream is composed by time, position, polarity, and magnitude information. Such a bitstream offers new possibilities for image processing such as event-by-event object tracking. In particular, we propose some processing to cluster events, filter noise and extract other useful features, such as a velocity estimation.

Published
2023

6. Integrated Test Circuit for Off-State Dynamic Drain Stress Evaluation

Author

J. Hai, F. Cacho, X. Federspiel, T. Garba-Seybou, A. Divay, E. Lauga-Larroze, J.-D. Arnould, STMicroelectronics [Crolles] (ST-CROLLES), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Reliable RF and Mixed-signal Systems (TIMA-RMS), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), and IEEE

Subjects
PACS 85.42, dynamic stress, degradation mode, integrated test circuit, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, off-state reliability, TDDB
Abstract

International audience; Dynamic off-state stress for RF applications is investigated via integrated test circuits to enable GHz level testing. We have performed characterization of test circuits to ensure the dynamic stress signal waveform integrity, which is verified against model simulation data. We report a x2 gain on time-to-breakdown at 1GHz against DC TDDB off-state stress. Based on extraction of IDlin degradation, no frequency effect is observed from DC to 1GHz off-state stress conditions. Modeling of on-state and off-state interactions based on sum of degradations modes is then demonstrated and supported by experimental data.

Published
2023

7. Optical device for detecting an acoustic wave

Author

Lauwers, Thomas, Basrour, Skandar, Coutard, Jean-Guillaume, Glière, Alain, Laffont, Guillaume, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Circuits, Devices and System Integration (TIMA-CDSI), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), CEA Paris (FR), UGA Grenoble (FR), CNRS Paris 16 (FR), and Grenoble-INP (FR)

Subjects
PACS 85.42, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

The invention relates to a device and method for detecting an acoustic wave propagating toward a membrane, the membrane carrying a waveguide comprising an optical cavity defining a resonant frequency. Under the effect of a vibration of the membrane, the resonance frequency of the optical cavity varies. The device includes a light source for directing a light wave into the optical cavity, and a servo circuit for servo-controlling the wavelength of the light wave to the resonant wavelength of the optical cavity. Monitoring the variation in the wavelength of the light wave allows an amplitude of the acoustic wave to be estimated.

Published
2023

8. NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS

Author

Pavanello, Fabio, Marchand, Cédric, O'Connor, Ian, Orobtchouk, Régis, Mandorlo, Fabien, Letartre, Xavier, Cueff, Sébastien, Vatajelu, Ioana, Di Natale, Giorgio, Cluzel, Benoit, Coillet, Aurélien, Charbonnier, Benoit, Noé, Pierre, Kaván, František, Zoldak, Martin, Szaj, Michal, Bienstman, Peter, van Vaerenbergh, Thomas, Rührmair, Ulrich, Flores, Paulo, Guerra E Silva, Luis, Chaves, Ricardo, Silveira, Luis Miguel, Ceccato, Mariano, Gizopoulos, Dimitris, Papadimitriou, George, Karakostas, Vasileios, Brando, Axel, Cazorla, Francisco Javier, Canal, Ramon, Closas, Pau, Gusi Amigo, Adrià, Crovetti, Paolo Stefano, Carpegna, Alessio, Tzamn, Melendez Carmona, Di Carlo, Stefano, Savino, Alessandro, INL - Ingénierie et conversion de lumière (i-Lum) (INL - I-Lum), Institut des Nanotechnologies de Lyon (INL), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-École Supérieure de Chimie Physique Électronique de Lyon (CPE)-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-École Centrale de Lyon (ECL), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS), INL - Conception de Systèmes Hétérogènes (INL - CSH), Architectures and Methods for Resilient Systems (TIMA-AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Laboratoire Interdisciplinaire Carnot de Bourgogne (ICB), Université de Technologie de Belfort-Montbeliard (UTBM)-Université de Bourgogne (UB)-Université Bourgogne Franche-Comté [COMUE] (UBFC)-Centre National de la Recherche Scientifique (CNRS), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Argotech a.s., Universiteit Gent = Ghent University (UGENT), Fakultät für Physik - Ludwig-Maximilians-Universität [München/Munich] (LMU), Ludwig-Maximilians University [Munich] (LMU), Instituto de Engenharia de Sistemas e Computadores (INESC), Department of Computer Science [Verona] (UNIVR | DI), Università degli studi di Verona = University of Verona (UNIVR), Department of Informatics and Telecomunications [Kapodistrian Univ] (DI NKUA), National and Kapodistrian University of Athens (NKUA), Barcelona Supercomputing Center - Centro Nacional de Supercomputacion (BSC - CNS), Universitat Politècnica de Catalunya [Barcelona] (UPC), Albora Technologies Limited [Barcelona], Department of Electronics and Telecommunications = DET Dipartimento di Elettronica e Telecomunicazioni [Politecnico di Torino] (DET), Politecnico di Torino = Polytechnic of Turin (Polito), Department of Computer Engineering (DAUIN), IEEE, and European Project: 101070238,HORIZON-CL4-2021-DIGITAL-EMERGING-01 ,NEUROPULS(2023)

Subjects
Signal Processing (eess.SP), FOS: Computer and information sciences, PACS 85.42, Hardware Architecture (cs.AR), FOS: Electrical engineering, electronic engineering, information engineering, modeling, Electrical Engineering and Systems Science - Signal Processing, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Computer Science - Hardware Architecture, simulation, artificial neural networks
Abstract

This special session paper introduces the Horizon Europe NEUROPULS project, which targets the development of secure and energy-efficient RISC-V interfaced neuromorphic accelerators using augmented silicon photonics technology. Our approach aims to develop an augmented silicon photonics platform, an FPGA-powered RISC-V-connected computing platform, and a complete simulation platform to demonstrate the neuromorphic accelerator capabilities. In particular, their main advantages and limitations will be addressed concerning the underpinning technology for each platform. Then, we will discuss three targeted use cases for edge-computing applications: Global National Satellite System (GNSS) anti-jamming, autonomous driving, and anomaly detection in edge devices. Finally, we will address the reliability and security aspects of the stand-alone accelerator implementation and the project use cases., Comment: 10 pages, 2 figures, conference

Published
2023
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9. Photoacoustic or photothermal detector comprising an optical transducer

Author

Lauwers, Thomas, Basrour, Skandar, Coutard, Jean-Guillaume, Glière, Alain, Laffont, Guillaume, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Circuits, Devices and System Integration (TIMA-CDSI), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), CEA Paris (FR), UGA Grenoble (FR), CNRS Paris 16 (FR), and Grenoble-INP (FR)

Subjects
PACS 85.42, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

The invention is a device and method for detecting an analyte in a medium. An exciting light source produces an exciting light wave, which propagates to the medium and heats the latter. The device comprises a transducer for detecting the heating of the medium. According to one embodiment, the transducer is a thermal transducer, configured to detect a variation in the temperature of the medium. According to another embodiment, the transducer is an acoustic transducer, configured to detect a photoacoustic wave propagating from the medium. Whatever the embodiment, the transducer employs a membrane, on which a waveguide is placed. The waveguide comprises a resonant optical cavity. Transduction is achieved by analyzing a variation in a resonant wavelength of the optical cavity.

Published
2022

10. A 6.3 pJ/b Ultra-low Power Energy Detector for Non-Coherent UWB Impulse Radio Receiver

Author

Ramos Sparrow, Oswaldo, Bourdel, Sylvain, Jacquemod, Gilles, Gaubert, Jean, Qualcomm France RFFE SARL (Qualcomm France ), Reliable RF and Mixed-signal Systems (TIMA-RMS), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Laboratoire de Polytech Nice-Sophia (Polytech'Lab), Université Nice Sophia Antipolis (1965 - 2019) (UNS), COMUE Université Côte d'Azur (2015-2019) (COMUE UCA)-COMUE Université Côte d'Azur (2015-2019) (COMUE UCA)-Université Côte d'Azur (UCA), Institut des Matériaux, de Microélectronique et des Nanosciences de Provence (IM2NP), Aix Marseille Université (AMU)-Université de Toulon (UTLN)-Centre National de la Recherche Scientifique (CNRS), and IEEE

Subjects
LNA, UWB, PACS 85.42, subthreshold CMOS, ECC, FCC, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, squarer
Abstract

International audience; This paper presents a 130nm CMOS (HCMOS9 from ST-Microelectronics) 6.3 pJ/b ultra-low power energy detector circuit design and implementation. The designed energy detector is implemented with three blocks: the squarer based on a MOS transistor biased in the subthreshold region, the integrator based on a low pass amplifier and a decision circuit. The energy detector is driven by a LNA of 30 dB gain. The experimental results show that a BER of 10 –3 is achieved for a peak to peak voltage of 3.4 mV at receiver input for a data rate of 100 Mb/s, leading to a receiver sensitivity of -58.4 dBm. The energy power consumption is 0.63 mW resulting in an energy of 6.3 pJ/b. The overall Rx power consumption is 14.4 mW (100 % duty cycled) with a 1.2 V supply voltage when the receiver is always on. This value is drastically reduced with a power gating technique due to the duty cycle of the IR-UWB pulses. For example, assuming an on-stage window of 5 ns, the total power consumption becomes 7.2 mW @ 100 Mb/s. The chip area is 1.43 mm 2 .

Published
2022

11. Electromagnetic Leakage Assessment of a Proven Higher-Order Masking of AES S-Box

Author

Bordes, Nicolas, Maistri, P., Calcul Algébrique et Symbolique, Sécurité, Systèmes Complexes, Codes et Cryptologie (CASC), Laboratoire Jean Kuntzmann (LJK), Institut National de Recherche en Informatique et en Automatique (Inria)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Institut National de Recherche en Informatique et en Automatique (Inria)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Architectures and Methods for Resilient Systems (TIMA-AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), and ANR-15-IDEX-0002,UGA,IDEX UGA(2015)

Subjects
PACS 85.42, leakage assessment, masking, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, side channel
Abstract

International audience; Many digital systems need to provide cryptographic capabilities. A large part of these devices is easily accessible by the malicious user, and may be vulnerable to side channel attacks such as power or electromagnetic analysis. From one side, the designer has to protect the architecture with proven countermeasures; on the other, the actual implementation must be validated in order to prove the absence of undesired leakages. In this paper, we present an implementation of two optimized and proven masking schemes of order $3$ and $7$ for an embedded software AES, and prove its robustness by showing the absence of significant leakage in the nonlinear layer.

Published
2022

12. Secure PUF-based Authentication and Key Exchange Protocol using Machine Learning

Author

Amir Ali-pour, Fatemeh Afghah, David Hely, Vincent Beroulle, Giorgio Di Natale, Architectures and Methods for Resilient Systems (TIMA-AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Clemson University, Laboratoire de Conception et d'Intégration des Systèmes (LCIS), Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Université Grenoble Alpes (UGA), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), and IEEE

Subjects
PACS 85.42, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

International audience; Error Correction Codes and Fuzzy Extractors (FE) using publicly available helper data are used to increase the reliability of the secret value generated from noisy sources such as Physically Unclonable Functions (PUFs). Publicly available helper data is, in turn, vulnerable against Helper Data ma- nipulation attacks due to its correlation with the secret value. Instead of using helper data for FE-based error correction, we propose a locally recoverable repetition coding mechanism. Our proposed mechanism is based on sharing only the user’s generated challenge values, which is inherently secure against machine learning and PUF cloning attacks. We evaluate the reliability of our method using simulated challenge response pairs (CRP)s captured from various XOR Arbiter PUF structures at different levels of noise embedded in the PUF CRP characteristic. We show for instance that in a scenario of using PUF with 10% error-rate, our method can successfully recover the encryption key with close to zero failure-rate with a repetition code length of 10 or higher.

Published
2022

13. Methodology for Active Junction Profile Extraction in thin film FD-SOI Enabling performance driver identification in 500°C devices for 3D sequential integration

Author

T. Mota Frutuoso, X. Garros, P. Batude, L. Brunet, J. Lacord, B. Sklenard, V. Lapras, C. Fenouillet-Beranger, M. Ribotta, A. Magalhaes-Lucas, J. Kanyandekwe, R. Kies, G. Romano, E. Catapano, M. Casse, J. Lugo-Alvarez, P. Ferrari, F. Gaillard, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Reliable RF and Mixed-signal Systems (TIMA-RMS), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), and IEEE

Subjects
resistance, silicon-on-insulator, three-dimensional displays, VLSI (Very Large Scale Integration), PACS 85.42, capacitance, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, predictive models, performance evaluation
Abstract

International audience; We present, for the first time, a new CV based technique to extract the Active Dopant Profile under the spacer in thin film FDSOI devices (CV-AJP). The methodology is successfully applied to FDSOI devices fabricated at 500°C for 3D sequential integration. It shows that the ION/ IOFF trade-off relies mainly on the chemical dopant introduction below the offset spacer, as the activation level obtained with thermal activation is found to be high enough. The LT device demonstrated in this work, already outperforms the literature. The active profile extraction also allows to draw guidelines for further device performance improvement: using a scaled SiCO spacer (5,5nm) allows to circumvent the negligible dopant diffusion at 500°C without dynamic performance penalty due to its low-k dielectric value.

Published
2022

14. Ultra-fast CV methods (< 10µs) for interface trap spectroscopy and BTI reliability characterization using MOS capacitors

Author

Mota Frutuoso, Tadeu, Garros, Xavier, Lugo-Alvarez, José, Kom Kammeugne, Roméo, Mohgouk Zouknak, Louis David, Viey, Abygaël, Vandendaele, William, Ferrari, Philippe, Gaillard, Fred, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Reliable RF and Mixed-signal Systems (TIMA-RMS), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), and IEEE

Subjects
DIT, PACS 85.42, aging, High-k Oxide, semiconductor device reliability, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, CMOS technology
Abstract

International audience; Two Ultra-Fast capacitance characterization methods based on the displacement current measure are explored for MOS capacitance devices. The first method measure the variation of charge obtained from several 100ns short pulses while the second uses a (1 to 5µs/V) continuous ramp to perform the capacitance measurement. Different applications are investigated for each method depending on measurement time and precision. The short pulsed method is used to perform a CV trap spectroscopy. Thanks to distinctive charging and discharging phases we are able to separately extract the capture and emission behavior of interface traps. We demonstrate that BTI characterization can be performed on simple MOScap using CV measurements based on IV ramp as in MOSFET devices. Furthermore, both methods can be combined in oxides presenting a high hysteresis behavior, to separately characterize low frequency oxide trapping from high frequency interface state trapping.

Published
2022

15. Effectiveness of Attitude Estimation Processing Approaches in Tolerating Radiation Soft Errors

Author

Kraemer Sarzi Sartori, Tarso, Fourati, Hassen, Rajappa, Anuj Justus, Reiter, Philippe, Possamai Bastos, Rodrigo, BEN TITO, Laurence, Architectures and Methods for Resilient Systems (TIMA-AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Dynamics and Control of Networks (DANCE), Inria Grenoble - Rhône-Alpes, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria)-GIPSA Pôle Automatique et Diagnostic (GIPSA-PAD), Grenoble Images Parole Signal Automatique (GIPSA-lab), Université Grenoble Alpes (UGA)-Grenoble Images Parole Signal Automatique (GIPSA-lab), Internet Technology and Data Science Lab (IDLab), Universiteit Antwerpen = University of Antwerpen [Antwerpen]-Universiteit Gent = Ghent University (UGENT), This work was supported in part by: the MultiRad project of the Région Auvergne-Rhône-Alpes's international ambition pack (PAI), the French national research agency within the France-2030 program (ANR-15-IDEX-0002), the LabEx PERSYVAL-Lab (ANR-11-LABX-0025-01), the IRT Nanoelec (ANR-10-AIRT-0005) of the French national program PIA ('Programme d’Investissements d’Avenir), the LPSC's GENESIS platform, and the ILL's TENIS instrument (TEST-3202 and TEST-3219 experiments)., ANR-15-IDEX-0002,UGA,IDEX UGA(2015), ANR-11-LABX-0025,PERSYVAL-lab,Systemes et Algorithmes Pervasifs au confluent des mondes physique et numérique(2011), and ANR-10-AIRT-0005,NANOELEC,NANOELEC(2010)

Subjects
PACS 85.42, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

International audience

Published
2022

16. A hybrid event-based pixel for low-power image Sensing

Author

Akrarai, Mohamed, Margotat, Nils, Sicard, Gilles, Fesquet, Laurent, Circuits, Devices and System Integration (CDSI), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), European Project: 783127,H2020-EU.2.1.1.7. - ECSEL,OCEAN12(2018), and Circuits, Devices and System Integration (TIMA-CDSI)

Subjects
time to first spike pixel, event based techniques, dynamic vision sensor pixel, PACS 85.42, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

International audience; This article presents a hybrid pixel dedicated to event-based image sensors, which suppresses spatial and temporal redundancies. This pixel is a combination between two kinds of pixels, known as TFS and DVS. The first one is able to reduce - associated to a dedicated readout - spatial redundancies, while the second manages the temporal redundancies. Each pixel is classically built with a photodiode but this hybrid structure shares the photodiode between the DVS and the TFS pixels. In our design, 4 TFS pixel photodiodes are shared with 1 DVS pixel, which exploits the average current of the latter. In order to evaluate such a pixel, a comparison is made between a hybrid pixel matrix and a matrix composed of TFS and DVS pixels.The evaluation is made in terms of activity and power but also by analyzing their fill-factor, circuitry and layout. A testchip including the 2 event-based image sensors has been designed in FDSOI 28 nm technology from STMicroelecronics.

Published
2021

17. Langage et sémantique des expressions pour la synthèse de modèle Grafcet dans un environnement IDM

Author

Emmanuel Simeu, Maurice Tchuente, Gérard Nzebop Ndenoka, Université de Yaoundé I, Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Laboratoire International de Recherche en Informatique et Mathématiques Appliquées (LIRIMA), Université de Yaoundé I-Université Badji Mokhtar - Annaba [Annaba] (UBMA)-Institut National de Recherche en Informatique et en Automatique (Inria)-Université Joseph Ki-Zerbo [Ouagadougou] (UJZK)-Université d'Antananarivo-Université Gaston Bergé Sénégal-Centre National de la Recherche Scientifique et Technologique (CNRST), Université de Yaoundé I-Université Badji Mokhtar Annaba (UBMA)-Institut National de Recherche en Informatique et en Automatique (Inria)-Université Joseph Ki-Zerbo [Ouagadougou] (UJZK)-Université d'Antananarivo-Université Gaston Bergé Sénégal-Centre National de la Recherche Scientifique et Technologique (CNRST), Reliable RF and Mixed-signal Systems (TIMA-RMS), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), and Université Grenoble Alpes (UGA)

Subjects
Programming language, Computer science, Semantics (computer science), expressions Grafcet, Model synthesis, General Medicine, métamodèle, sémantique des expressions, [INFO.INFO-SE]Computer Science [cs]/Software Engineering [cs.SE], computer.software_genre, grammaire hors-contexte, Ingénierie Dirigée par les Modèles, [INFO.INFO-CL]Computer Science [cs]/Computation and Language [cs.CL], [INFO.INFO-AU]Computer Science [cs]/Automatic Control Engineering, PACS 85.42, Ingénierie Dirigé}e par les Modèles, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, analyseur syntaxique, vérification de modèle, computer
Abstract

The GRAphe Fonctionnel de Commande Étapes Transitions (GRAFCET) is a powerful graphical modeling language for the pecification of controllers in discrete event systems.It uses expressions to express the conditions of transitions and conditional actions as well as the logical and arithmetic expressions assigned to stored actions. However, several research works has focused on the transformation of Grafcet specifications (including expressions) into control code for embedded systems. To make it easier to edit valid Grafcet models and generate code, it is necessary to propose a formalization of the Grafcet expression language permitting to validate its constructs and provide an appropriate semantics. For this, we propose a context-free grammar that generates the whole set of Grafcet expressions, by extending the usual grammars of logical and arithmetic expressions. We also propose a metamodel and an associated semantics of Grafcet expressions to facilitate the implementation of the Grafcet language. A parser of the expressions Grafcet emph G7Expr is then obtained thanks to the generator of parsers ANTLR, while the metamodel is implemented in the Eclipse EMF Model Driven Engineering (MDE) environment. The combination of the two tools makes it possible to analyze and automatically build Grafcet expressions when editing and synthesizing Grafcet models. Le GRAphe Fonctionnel de Commande Étapes Transitions (GRAFCET) est un puissant lan-gage de modélisation graphique pour la spécification de contrôleurs dans des systèmes à événe-ments discrets. Il fait usage des expressions pour exprimer les conditions de franchissement des transitions et des actions conditionnelles ainsi que les expressions logiques et arithmétiques assi-gnées aux actions stockées. Cependant, de nombreux travaux se sont penchés sur la transformation de spécifications Grafcet (y compris les expressions) en code de contrôle pour systèmes embar-qués. Pour faciliter l'édition de modèles Grafcet valides et la génération du code de contrôle, il est judicieux de proposer une formalisation du langage des expressions Grafcet, permettant de valider ses constructions et d'en pourvoir une sémantique appropriée. Pour cela, nous proposons une gram-maire hors-contexte qui génère tout l'ensemble des expressions Grafcet, en étendant les grammaires usuelles des expressions arithmétiques et logiques. Nous proposons également un métamodèle et une sémantique associée des expressions Grafcet pour faciliter la mise en oeuvre du langage Grafcet sous la forme d'un parseur des expressions Grafcet G7Expr obtenu grce au générateur d'analyseurs syntaxiques ANTLR, alors que le métamodèle est mis en oeuvre dans l'environnement d'Ingénie-rie Dirigée par les Modèles (IDM) Eclipse EMF. L'association des deux outils permet d'analyser et de construire automatiquement les expressions Grafcet lors de l'édition et la synthèse des modèles Grafcet.

Published
2021

18. Evaluation of Attitude Estimation Algorithm under Soft Error Effects

Author

Sales Brum, Joao Paolo, Kraemer Sarzi Sartori, Tarso, Lin, Jiaru, Garay Trindade, Matheus, Fourati, Hassen, Velazco, Raoul, Possamai Bastos, Rodrigo, Universidade Federal de Santa Maria (UFSM), Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Dynamics and Control of Networks (DANCE), Inria Grenoble - Rhône-Alpes, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria)-GIPSA Pôle Automatique et Diagnostic (GIPSA-PAD), Grenoble Images Parole Signal Automatique (GIPSA-lab), Université Grenoble Alpes (UGA)-Grenoble Images Parole Signal Automatique (GIPSA-lab), Universidade Federal de Santa Maria = Federal University of Santa Maria [Santa Maria, RS, Brazil] (UFSM), Architectures and Methods for Resilient Systems (TIMA-AMfoRS ), This work has been partially supported by: MultiRad project funded by Région Auvergne-Rhône-Alpes (AURA)’s international ambition pack (PAI), OVNIPROM-SAT project funded in the frame of SCUSI (Soutien aux Coopérations Universitaires et Scientifiques Internationales – Région AURA), and LabEx PERSYVAL-Lab8 (ANR-11-LABX-0025-01) funded by the French government program 'Investissement d’avenir'., and ANR-11-LABX-0025,PERSYVAL-lab,Systemes et Algorithmes Pervasifs au confluent des mondes physique et numérique(2011)

Subjects
Inertial Navigation System, Attitude Estimation, PACS 85.42, Fault Injection, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Single Event Upset, ComputingMilieux_MISCELLANEOUS
Abstract

International audience; The space industry has been launching nanosatellites in order to reduce the weight of the payload and monitor space at a lower cost benefit than a conventional satellite. In this context, the use of Attitude Estimation (AE) algorithms have become more and more important. This paper evaluates the effectiveness of a processing system running an AE algorithm under an emulation-based fault injection campaign. This method is able to emulate soft errors directly in the development board's registers and allows to put in evidence critical situations, such as the wrong calculation of a reference component in space. Results and preliminary analysis suggest a predominance of matches in general-purpose registers and some failures in those called frame point, demanding extended fault injection campaign to identify further details.

Published
2021

19. Nanosatellite On-Board Computer including a Many-Core Processor

Author

Pancher, Fabrice, Vargas Vallejo, Vanessa Carolina, Ramos Vargas, Pablo Francisco, Possamai Bastos, Rodrigo, Ardiles Saravia, David César, Velazco, Raoul, Institut de Planétologie et d'Astrophysique de Grenoble (IPAG), Centre National d'Études Spatiales [Toulouse] (CNES)-Observatoire des Sciences de l'Univers de Grenoble (OSUG ), Institut national des sciences de l'Univers (INSU - CNRS)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)-Université Grenoble Alpes (UGA)-Institut national des sciences de l'Univers (INSU - CNRS)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)-Université Grenoble Alpes (UGA), Universidad de las Fuerzas Armadas [Sangolqui] (ESPE), Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), and Université Grenoble Alpes (UGA)

Subjects
PACS 85.42, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS
Abstract

International audience

Published
2021

20. Leveraging Targeted Value Prediction to Unlock New Hardware Strength Reduction Potential

Author

Arthur Perais, System Level Synthesis (SLS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), and BEN TITO, Laurence

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], micro architecture, speculation, Computer science, Pipeline (computing), general-purpose, Value (computer science), 02 engineering and technology, Parallel computing, Operand, 01 natural sciences, Footprint, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, high performance architecture, Fraction (mathematics), Rename, processeur généraliste, 010302 applied physics, micro-architecture, 020202 computer hardware & architecture, Microarchitecture, PACS 85.42, architecture hautes-performances, Hardware_CONTROLSTRUCTURESANDMICROPROGRAMMING, Instruction-level parallelism, spéculation
Abstract

International audience; Value Prediction (VP) is a microarchitectural technique that speculatively breaks data dependencies to increase the available Instruction Level Parallelism (ILP) in general purpose processors. Despite recent proposals, VP remains expensive and has intricate interactions with several stages of the classical superscalar pipeline. In this paper, we revisit and simplify VP by leveraging the irregular distribution of the values produced during the execution of common programs. First, we demonstrate that a reasonable fraction of the performance uplift brought by a full VP infrastructure can be obtained by predicting only a few "usual suspects" values. Furthermore, we show that doing so allows to greatly simplify VP operation as well as reduce the value predictor footprint. Lastly, we show that these Minimal and Targeted VP infrastructures conceptually enable Speculative Strength Reduction (SpSR), a rename-time optimization whereby instructions can disappear at rename in the presence of specific operand values.

Published
2021

21. A High-Level Design Flow for Locally Body Biased Asynchronous Circuits

Author

Laurent Fesquet, Katell Morin-Allory, Yoan Decoudu, Circuits, Devices and System Integration (CDSI), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), and European Project: 783127,H2020-EU.2.1.1.7. - ECSEL,OCEAN12(2018)

Subjects
Power management, Standard cell, Handshake, Computer science, Design flow, Biasing, FDSOI, Asynchronous communication, PACS 85.42, high-level synthesis, bundled-data circuit, Electronic engineering, power management, Place and route, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, fine-grain body biasing, Electronic circuit
Abstract

International audience; Fully Depleted Silicon on Insulator (FDSOI) technologies offer new possibilities for power management, especially with dynamic body biasing. Traditional strategies are based on a large body bias generator, which drives the IP back-gates thanks to a dedicated and often complex power management system. As asynchronous circuits use local synchronizations with handshake components, which activate only the processing parts, it is possible to take advantage of these handshake signals to implement a simple and fine-grain body biasing strategy. Instead of driving IPs with a large body bias generator, we use tiny distributed generators, locally activating small body bias regions when the circuit is processing data. These latter are based on level-shifters and implemented as standard cells. Thus, we propose a high-level design flow associating asynchronous circuits and a local body biasing strategy, which does not require complex body bias management. Indeed, the local handshake signals directly control our dedicated body bias generators. Moreover, Place and Route operations are facilitated by the use of standard cell generators. The simulations show the flow efficiency, a finer grain body biasing and a significant power reduction.

Published
2021

22. Security EDA Extension through P1687.1 and 1687 Callbacks

Author

Giorgio Di Natale, Regis Leveugle, Michele Portolan, Vincent Reynaud, Paolo Maistri, Architectures and Methods for Resilient Systems (TIMA-AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), and European Project: 172930120,PENTA,RECHADESTIMD,HADES(2017)

Subjects
Computer science, Programming language, reconfigurable scan networks, Extension (predicate logic), computer.software_genre, automated test environment, domain-specific languages, secure access, PACS 85.42, authentication, Callback, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, computer, callbacks
Abstract

International audience; In recent years, the world of VLSI testing has been living a huge transformation pushed by constraints and requirements coming from a large variety of sources and applications. The traditional need for higher accessibility and controllability led to solutions such as IEEE 1687, while the need for reuse is pushing for innovations like P1687.1. All the while, these same features are raising security concerns for malicious attacks or reverse engineering. Standards usual approach of relying on Domain-Specific Languages to convey information to the EDA tools has difficulty in handling such disparate and often conflicting needs, with the risk of a dangerous proliferation of custom and incompatible solutions. In this paper, we show how the usage of Callbacks, defined in P1687.1, can help solve this issue.

Published
2021

23. Assessment of Machine Learning Models in Computing System under Neutron Radiation

Author

Garay Trindade, Matheus, Sales Brum, Joao Paolo, Maldaner, Liége, Garibotti, Rafael, Ost, Luciano, Possamai Bastos, Rodrigo, Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Universidade Federal de Santa Maria (UFSM), Pontifícia Universidade Católica do Rio Grande do Sul [Porto Alegre] (PUCRS), Loughborough University, and Universidade Federal de Santa Maria = Federal University of Santa Maria [Santa Maria, RS, Brazil] (UFSM)

Subjects
PACS 85.42, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS
Abstract

International audience

Published
2021

24. Assessment of Attitude Estimation Processing System under Neutron Radiation Effects

Author

Kraemer Sarzi Sartori, Tarso, Fourati, Hassen, Garay Trindade, Matheus, Possamai Bastos, Rodrigo, Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Dynamics and Control of Networks (DANCE), Inria Grenoble - Rhône-Alpes, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria)-GIPSA Pôle Automatique et Diagnostic (GIPSA-PAD), Grenoble Images Parole Signal Automatique (GIPSA-lab), Université Grenoble Alpes (UGA)-Grenoble Images Parole Signal Automatique (GIPSA-lab), Architectures and Methods for Resilient Systems (TIMA-AMfoRS ), This work has been partially supported by: MultiRad project, funded by Région Auvergne-Rhône-Alpes’s international ambition pack, and IRT Nanoelec (ANR-10-AIRT-05) and LabEx PERSYVAL-Lab (ANR-11-LABX-0025-01), both funded by the French government program 'Investissement d’avenir'., ANR-10-AIRT-0005,NANOELEC,NANOELEC(2010), and ANR-11-LABX-0025,PERSYVAL-lab,Systemes et Algorithmes Pervasifs au confluent des mondes physique et numérique(2011)

Subjects
PACS 85.42, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS
Abstract

International audience

Published
2021

25. An asynchronous hybrid pixel image sensor

Author

Gilles Sicard, Mohamed Akrarai, Nils Margotat, Laurent Fesquet, Circuits, Devices and System Integration (CDSI), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), and Circuits, Devices and System Integration (TIMA-CDSI)

Subjects
time to first spike pixel, Pixel, low power, Computer science, business.industry, Event (computing), [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], ComputingMethodologies_IMAGEPROCESSINGANDCOMPUTERVISION, event-based, Sample (graphics), Reduction (complexity), Asynchronous communication, PACS 85.42, Image sensor, business, Bitstream, asynchronous circuit, Throughput (business), Computer hardware
Abstract

International audience; Today, most of the computer vision applications produce a huge computational load, which can become an issue for autonomous systems such as robots. This is mainly due to the image sensor readout, which permanently captures the image at a fixed rate and produces a relatively high throughput bitstream. Therefore, finding techniques minimizing the data throughput helps to drastically reduce power. Event-based image sensors are able to capture images with a low throughput bistream, thanks to a sample strategy eliminating temporal and spatial redundancies. This natively gives a data-compressed image, which favors lower storage and computation. This article presents an event-based image sensor incorporating a hybrid pixel matrix composed of two pixel types and an arbiterless asynchronous readout system. The results show an important bitstream reduction compared to that of a standard CMOS image sensor. A testchip of our event-based image sensor has been designed and is currently under fabrication.

Published
2021

26. To Pin or Not to Pin: Asserting the Scalability of QEMU Parallel Implementation

Author

Frédéric Pétrot, Saverio Miroddi, Marie Badaroux, System Level Synthesis (SLS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Ticketsolve, ANR-18-CE46-0011,ImPreNum,Améliorer la prédictibilité des calculs numériques(2018), and ANR-19-P3IA-0003,MIAI,MIAI @ Grenoble Alpes(2019)

Subjects
discrete event simulation, parallel simulation, Reduced instruction set computing, Computer science, Binary translation, Parallel computing, [INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation, Parsec, performance evaluation, Instruction set, ARM architecture, Parallel processing (DSP implementation), PACS 85.42, Scalability, Benchmark (computing), dynamic binary translation
Abstract

International audience; Due to its speed in cross-executing sequential code, dynamic binary translation is the unchallenged technology for full system-level simulation. Among the translators, QEMU has become the de facto solution. It introduced parallel host execution of the target cores a few years ago for the ARM instruction set architecture and this support is now also available, among others, for RISCV. Given the popularity of these instruction sets in multi and many-core systems, assessing the scalability of their parallel implementation makes sense. In this paper, we use a subset of the PARSEC benchmark to measure the execution time of QEMU's parallel implementation, to which we added the ability to pin a target processor to a host core or hardware thread. We report the results of a wealth of experiments we performed on a 16-core/32-thread x86-64 SMP machine. They show that the support of parallelism in QEMU scales well, and that, somewhat counter intuitively, pinning does not improve performance.

Published
2021

27. Distance learning is not an online face-to-face – Observations in microelectronic education

Author

Olivier Bonnaud, Laurent Fesquet, Institut d'Électronique et des Technologies du numéRique (IETR), Nantes Université (NU)-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), Coordination Nationale de la Formation en Microélectronique (CNFM), Centre National de la Recherche Scientifique (CNRS), Circuits, Devices and System Integration (CDSI), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Centre Interuniversitaire de Micro-Electronique (CIME), Institut National Polytechnique de Grenoble (INPG), Université de Nantes (UN)-Université de Rennes 1 (UR1), Université de Nantes (UN)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), and Circuits, Devices and System Integration (TIMA-CDSI)

Subjects
4. Education, distance learning, PACS 85.42, microelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

International audience; Due to the pandemic in early 2020, the French government, like many others, decided to temporarily close the universities and asked the faculties to entirely focus on online education or e-learning. In a world where digital contents exponentially increase, this pandemic has been an opportunity to develop distance e-learning. Many politicians found a unique opportunity to decrease or even eliminate face-to-face teaching activities. In engineering, this experience has shown clear limits and weaknesses. This paper highlights several problems that raised in microelectronic education and good reasons to move back to face-to-face learning especially for the acquisition of know-how. Indeed, know-how is mandatory for engineers, masters and PhDs in science and technology and this will never be replaced by a virtual experience. Real practice is the necessary price to pay for meeting the technological challenges of the upcoming decade.

Published
2021

28. Dispositif optique de détection d'une onde acoustique

Author

Lauwers, Thomas, Basrour, Skandar, Coutard, Jean-Guillaume, Glière, Alain, Laffont, Guillaume, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Circuits, Devices and System Integration (TIMA-CDSI), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), and Université Grenoble Alpes (UGA)

Subjects
PACS 85.42, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

N° et date de publication de la demande : FR3105824 - 02/07/2021 (BOPI 2021-26)N° et date de dépôt : FR1915695 - 27/12/2019; L'invention est un dispositif et un procédé de détection d'une onde acoustique se propageant vers une membrane, la membrane supportant un guide d'onde comportant une cavité optique définissant une fréquence de résonance. Sous l'effet d'une vibration de la membrane la fréquence de résonance de la cavité optique varie. Le dispositif comporte une source de lumière pour diriger une onde lumineuse dans le cavité optique ainsi qu'un circuit d'asservissement pour asservir la longueur d'onde de l'onde lumineuse à la longueur d'onde de résonance de la cavité optique. Le suivi de la variation de la longueur d'onde de l'onde lumineuse permet d'estimer une amplitude de l'onde acoustique.

Published
2021

29. Détecteur photoacoustique ou photothermique comportant un transducteur optique

Author

Lauwers, Thomas, Basrour, Skandar, Coutard, Jean-Guillaume, Glière, Alain, Laffont, Guillaume, Circuits, Devices and System Integration (TIMA-CDSI), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), and Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)

Subjects
PACS 85.42, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

N° et date de publication de la demande : FR3105827 - 02/07/2021 (BOPI 2021-26)N° et date de dépôt : FR1915696 - 27/12/2019; L'invention est un dispositif et un procédé pour détecter un analyte dans un milieu. Une source de lumière d'excitation produit une onde lumineuse d'excitation, laquelle se propage vers le milieu en produisant un échauffement de ce dernier. Le dispositif comporte un transducteur pour détecter l'échauffement du milieu. Selon un mode de réalisation, le transducteur est un transducteur thermique, configuré pour détecter une variation de la température du milieu. Selon un autre mode de réalisation, le transducteur est un transducteur acoustique, configuré pour détecter une onde photoacoustique se propageant depuis le milieu. Quel que soit le mode de réalisation, le transducteur met en œuvre une membrane, sur laquelle est disposé un guide d'onde. Le guide d'onde comporte une cavité optique résonante. La transduction est réalisée en analysant une variation d'une longueur d'onde de résonance de la cavité optique.

Published
2021

30. FPU Reduced Variable Precision in Time: Application to the Jacobi Iterative Method

Author

Mounir Benabdenbi, Noureddine Ait Said, Katell Morin-Allory, Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), and Circuits, Devices and System Integration (CDSI)

Subjects
Very-large-scale integration, business.industry, Computer science, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], transprecision computing, Jacobi method, RISC-V, computer.software_genre, Instruction set, symbols.namesake, Software, Computer engineering, Iterative refinement, PACS 85.42, symbols, Overhead (computing), Compiler, business, Real-time operating system, computer
Abstract

International audience; Floating-Point (FP) computation using standard IEEE formats has a significant hardware overhead. Moreover, these formats are over-designed for most real-world applications, especially iterative refinement algorithms. Hence there is a need for hardware FP Unit (FPU) architectures with run-time variable precision capabilities.In this work, we propose a FPU architecture that enables designers to dynamically tune FP computations’ precision at run-time, leading to significant power consumption, execution time, and energy savings. Despite its additional circuit area overhead, the proposed architecture simplifies the integration of variable precision in existing software workloads at any level of the software stack (OS, RTOS, or application-level) since it only requires light-weight software support and solely relies on traditional assembly instructions, without the need for a specialized compiler or custom instructions.We propose a modified version of the Jacobi iterative method with automatic run-time variable precision, which takes full advantage of the suggested FPU. It demonstrates up to 75.21% power consumption saving, up to 64.37% execution time saving, and up to 88.96% total energy saving w.r.t the reference double-precision implementation, and with no accuracy loss.

Published
2021

31. Microarchitecture-aware Fault Models: Experimental Evidence and Cross-Layer Inference Methodology

Author

Brice Colombier, Vincent Beroulle, Ihab Alshaer, Paolo Maistri, Christophe Deleuze, Laboratoire de Conception et d'Intégration des Systèmes (LCIS), Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Université Grenoble Alpes (UGA), Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), ANR-11-LABX-0025,PERSYVAL-lab,Systemes et Algorithmes Pervasifs au confluent des mondes physique et numérique(2011), BEN TITO, Laurence, Laboratoires d'excellence - Systemes et Algorithmes Pervasifs au confluent des mondes physique et numérique - - PERSYVAL-lab2011 - ANR-11-LABX-0025 - LABX - VALID, and IDEX UGA - - UGA2015 - ANR-15-IDEX-0002 - IDEX - VALID

Subjects
fault injection, Computer science, micro-architecture, Distributed computing, Cyber-physical system, Inference, Hardware_PERFORMANCEANDRELIABILITY, Fault injection, Fault (power engineering), Microarchitecture, [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR], PACS 85.42, Cross layer, Code (cryptography), Fault analysis, ComputingMilieux_MISCELLANEOUS, [INFO.INFO-CR] Computer Science [cs]/Cryptography and Security [cs.CR]
Abstract

Fault injection attacks are considered one of the major threats to cyber-physical systems. The increasing complexity of embedded microprocessors involves complicated behaviours in presence of such attacks. Realistic fault models are required to study code vulnerabilities and be able to protect digital systems from these attacks. However, inferring fault models using only limited observations of faulty microprocessors is difficult. In this article, we present experiments that show the difficulty of characterizing and modelling the fault injection effects. From there, we propose a complete approach for fault analysis to build proper fault models at different system levels, which will help in designing suitable countermeasures at reasonable cost.

Published
2021

32. Automated Dysfunctional Model Extraction for Model Based Safety Assessment of Digital Systems

Author

Philippe Roche, Jean-Marc Daveau, Tiziano Fiorucci, Giorgio Di Natale, STMicroelectronics [Crolles] (ST-CROLLES), Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), and IEEE

Subjects
Finite-state machine, business.industry, Process (engineering), Computer science, media_common.quotation_subject, Hardware_PERFORMANCEANDRELIABILITY, Automation, Upset, Field (computer science), Reliability engineering, PACS 85.42, Safety assurance, Quality (business), [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, Quality assurance, media_common
Abstract

International audience; In the field of automatic quality or safety assurance level evaluation, this paper proposes the first approach towards the automation of the extraction processes of both the valid and faulty state machines within a System-on-a-Chip. The data automatically extracted by this method is a relevant input for behavioural modelization and FMEA analysis. The method is based on a semi-automated approach for the systematic extraction of failure modes of a digital design in the hypothesis of a single-event upset (SEU) or stuck-at in flip-flops. This procedure aims to enhance human driven failure analysis and provide inputs for RAMS frameworks in the process of quality assurance of complex devices. The main objective is to transport and apply RAMS methods and tools in the area of SoCs design. Experimental results have been conducted on an I2C - AHB system, laying the base for a complete and more complex analysis on an entire SoC.

Published
2021

33. Comparison between an ASK Event-Based Demodulation and a Digital IQ Demodulation

Author

Sylvain Engels, Laurent Fesquet, Alexis Rodrigo Iga Jadue, Circuits, Devices and System Integration (CDSI), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), and STMicroelectronics [Crolles] (ST-CROLLES)

Subjects
Comparator, Computer science, Noise (signal processing), [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], Modulation index, SystemVerilog, Signal, Amplitude-shift keying, asynchronous logic, amplitude shift keying (ASK) demodulator, non-uniform sampling scheme, Ask price, PACS 85.42, Electronic engineering, Demodulation, event-based analog-to-digital converter, computer, computer.programming_language
Abstract

This paper presents a comparison between two ASK demodulation techniques. The first one is a digital implementation of a traditional IQ demodulation, while the second is a novel digital demodulation algorithm connected to an EB-ADC (Event-Based ADC) for minimizing the number of processed events. The EB-ADC has been designed using a reduced LCSS (Level Crossing Sample Scheme) with only 2 levels, connected to two strong-arm comparators for the digitalization process. Electrical simulations were used to characterize these comparators for integrating them in a full digital SystemVerilog (SV) simulation. An adaptation of python’s library has been modeled in SV for simulating the RF input signal and its amplitude noise. This implemented algorithm benefits from the measurement of the time elapsed between two adjacent events improving the demodulator performance and noise resiliency, reaching, for instance, a BER=$3.33\cdot 10^{-7}$ for a modulation index (MI) of 10%, a SNR of 16 dB and a bitrate of 6.78 Mbps. This proposal was recently sent to fabrication in FDSOI 28nm STMicroelectronics technology.

Published
2021

34. Efficient deep learning approach for fault detection in the semiconductor industry

Author

Andrade Porras, Liliana Lilibeth, Baumela, Thomas, Pétrot, Frédéric, Briand, David, Bichler, Olivier, Coppola, Marcello, System Level Synthesis (SLS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Laboratoire Intelligence Artificielle Embarquée (LIAE), Université Paris-Saclay-Département Systèmes et Circuits Intégrés Numériques (DSCIN), Laboratoire d'Intégration des Systèmes et des Technologies (LIST), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Laboratoire d'Intégration des Systèmes et des Technologies (LIST), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), STMicroelectronics [Crolles] (ST-CROLLES), ANR-19-P3IA-0003,MIAI,MIAI @ Grenoble Alpes(2019), System Level Synthesis (TIMA-SLS), Laboratoire d'Intégration des Systèmes et des Technologies (LIST (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Laboratoire d'Intégration des Systèmes et des Technologies (LIST (CEA)), BEN TITO, Laurence, MIAI @ Grenoble Alpes - - MIAI2019 - ANR-19-P3IA-0003 - P3IA - VALID, Département Systèmes et Circuits Intégrés Numériques (DSCIN), STMicroelectronics [Grenoble] (ST-GRENOBLE), and Ovidiu VERMESAN

Subjects
quantized neural networks, field-programmable-gate-arrays, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], deep learning, hardware acceleration of AI, HW/SW integration, wafer maps, [INFO.INFO-OH] Computer Science [cs]/Other [cs.OH], PACS 8542, classification, embedded artificial intelligence, PACS 85.42, high-level synthesis, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

International audience; The semiconductor industry is a very cost sensitive industry and yield is key to profitability. The ability to analyse and detect the faulty parts at several 1nanufacturing steps is also very in1portant to ensure the quality of the delivered integrated circuits. Severa! factors as aligninents, shifts or 1nasks rotations can lead to errors during the front-end step (wafer fabrication), or others causes such as fingerprints, scratches and stains can cause cosmetic da.nage during the back-end step (Silicon packaging). Therefore , an automatic visual inspection is required to ensure that the parts are free of any defects. In this chapter, we focus specifically on classifying wafer maps according to predefined defaults. We propose a platform which ain1s al n1aking the classification process n1ore energy efficient, by n1eans of the interconnection of two hardware parts. The first one, the microprocessor STM32MP 1, is responsible for image pre-processing and for offloading inference to a dedicated hardware accelerator. The second one, the hardware accelerator, is i1nple1nented in a Xilinx Zybo Z7-20 FPGA and uses a quantized neural network model. Preliminary results show that, for this low throughput applications that has a limited number of classes, the solution presented in this article can classify in real-time with accuracy above 80% using limited resources.

Published
2021

35. Integrated Wideband Millimeter-Wave Bias-Tee – Application to Distributed Amplifier Biasing

Author

Jean-Daniel Arnould, Mohamad El Chaar, Florence Podevin, Antonio Augusto Lisboa de Souza, Manuel J. Barragan, Sylvain Bourdel, Laboratoire de Radio-Fréquence et d'Intégration de Circuits (RFIC-Lab ), Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Université Grenoble Alpes (UGA), Universidade Federal da Paraiba (UFPB), Reliable RF and Mixed-signal Systems (RMS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), and Université Grenoble Alpes (UGA)

Subjects
Physics, business.industry, Bandwidth (signal processing), Electrical engineering, Distributed amplifier, Hardware_PERFORMANCEANDRELIABILITY, Integrated circuit, law.invention, Bias tee, CMOS, Parasitic capacitance, law, PACS 85.42, Broadband, Hardware_INTEGRATEDCIRCUITS, Wideband, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, ComputingMilieux_MISCELLANEOUS
Abstract

A wideband fully-integrated bias-tee well suited for millimeter waves is presented. Compared to conventional bias-tees, where RF-choke is optimized on the basis of its inductance value, here, the proposed RF-choke takes advantage of its low parasitic capacitance as one of the design parameters. While enabling wideband operation, in particular towards lower frequencies, this bias-tee enables ease-of-implementation, robustness against resonance, efficient power delivery to the intended wideband circuit and contributes to circuit area reduction on integrated circuit (IC) implementation. As a proof-of-concept, a wideband CMOS distributed amplifier (DA) with a lower-corner frequency (F lower ) of 5 GHz and an upper-corner frequency (F upper ) close to 100 GHz is implemented in STMicroelectronics’ 55-nm technology with the proposed bias-tee connected to its artificial drain line. The implemented bias-tee enabled a bandwidth close to 100 GHz and its RF-choke required a surface area of 82 µm x 82 µm. When integrated along with the DA, the overall chip area remained the same (0.89 mm2). Post-layout simulations showed a DC power overhead (due to inclusion of the on-chip bias-tee) limited to 17% of the DA-only consumption.

Published
2021

36. Record RF Performance (ft=180GHz and fmax=240GHz) of a FDSOI NMOS processed within a Low Thermal Budget for 3D Sequential Integration

Author

Mota Frutuoso, Tadeu, Lugo-Alvarez, José, Garros, Xavier, Brunet, Laurent, Cassé, Mickaël, Fenouillet-Beranger, Claire, Romano, Giovanni, Januel, Tarcisius, Cooper, David, Loup, Virginie, Kanyandekwe, Joël, Acosta-Alba, Pablo, Kerdiles, Sébastien, Tavernier, Aurélien, Brevard, Laurent, Ferrari, Philippe, Andrieu, François, Gaillard, Frédéric, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Laboratoire de Radio-Fréquence et d'Intégration de Circuits (RFIC-Lab ), Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Université Grenoble Alpes (UGA), and IEEE

Subjects
silicon-on-insulator, MOSFET, radio frequency (RF), three-dimensional displays, PACS 85.42, logic gate, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, mathematical model, performance evaluation
Abstract

International audience; Record RF Figure-Of-Merits (FoM) is highlighted for a 42nm NMOS transistor fully processed at Low Thermal Budget (LTB) (

Published
2021

37. Secure Test with RSNs: Seamless Authenticated Extended Confidentiality

Author

Michele Portolan, Paolo Maistri, Vincent Reynaud, Regis Leveugle, Architectures and Methods for Resilient Systems (TIMA-AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), European Project: 172930120,PENTA,RECHADESTIMD,HADES(2017), Architectures and Methods for Resilient Systems (AMfoRS ), BEN TITO, Laurence, and Hierarchy-Aware and secure embedded test infrastructure for Dependability and performance Enhancement of integrated Systems - HADES - - PENTA2017-04-01 - 0000-00-00 - 172930120 - VALID

Subjects
RSN, Authentication, Computer science, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, media_common.quotation_subject, SIB, Intellectual property, Computer security, computer.software_genre, confidentiality, Domain (software engineering), Test (assessment), IEEE 1687, Debugging, PACS 85.42, secure test, authentication, Confidentiality, State (computer science), [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, computer, Testability, media_common
Abstract

International audience; The testability of electronic devices is of critical importance and it is often supported by IEEE standards. The presence of test structures, on the other hand, paves the way for malicious attackers to access the circuit and extract confidential knowledge such as secret keys or intellectual property. Removing the access to these structures after manufacturing test may prevent security breaches, but this solution is not definitive and excludes the possibility of advanced uses such as online debugging, diagnosis of designs and on-line updates or monitoring. For this reason, it is important to maintain the test infrastructure but to protect it against threats either external (e.g., attackers) or internal (e.g., hardware trojans). This can be achieved through protocols ensuring authentication added to confidentiality capabilities. In the case of Reconfigurable Scan Networks (RSN - IEEE 1687), some solutions currently exist, but are limited to external threats. In this paper, we review the recent state of the art in the domain, and present a novel solution addressing in a comprehensive and low-cost manner authentication and confidentiality, both inside and outside the device.

Published
2021

38. Exploring and Comparing IEEE P1687.1 and IEEE 1687 Modeling of Non-TAP Interfaces

Author

Jeff Rearick, Michele Portolan, Hans-Martin von Staudt, Martin Keim, Bradford Van Treuren, Dialog Semiconductor GmbH [Munich], VT Enterprises, Advanced Micro Devices [Austin] (AMD), Advanced Micro Devices, Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), and Siemens Digital Industries Software

Subjects
Computer science, IJTAG, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], SPI, Transfer function, STAM, IEEE P2654, IEEE 1687, Computer architecture, I2C, PACS 85.42, Callback, IEEE P1687.2, SJTAG, transfer function, IEEE P1687.1, Hardware_ARITHMETICANDLOGICSTRUCTURES, Implementation
Abstract

International audience; The industry is moving forward with non-TAP, chip-level interfaces driving IEEE 1687-2014 networks. Recent literature not only describes such interfaces, like I 2 C and IEEE 1149.7 variants, but also demonstrates that such interfaces to IEEE 1687 are already proven in silicon. Common to those implementations is the need for "private" extensions of IEEE 1687 to make it support non-TAP interfaces. The goal of IEEE P1687.1 is to directly support non-TAP interfaces. In this work, we summarize the thought progression from IEEE 1687's data register callbacks to IEEE P1687.1's transfer function, which allows alignment with IEEE P2654, and possibly IEEE P1687.2.

Published
2021

39. Analysis and mitigation of timing inaccuracies in high-frequency on-chip sinusoidal signal generators based on harmonic cancellation

Author

Manuel J. Barragan, Ankush Mamgain, Salvador Mir, Reliable RF and Mixed-signal Systems (RMS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), and Université Grenoble Alpes (UGA)

Subjects
Signal generator, Noise (signal processing), Computer science, Silicon on insulator, Linearity, Integrated circuit, law.invention, Harmonic analysis, law, PACS 85.42, Limit (music), Electronic engineering, Key (cryptography), [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS
Abstract

On-chip sinusoidal signal generators are a key element for enabling a wide variety of DfT and BIST applications for AMS-RF integrated circuits. Harmonic cancellation techniques have been recently proposed for the efficient implementation of high-quality embedded sinusoidal signal generators. However, harmonic cancellation techniques, based on phase-shifting and combining a set of periodic signals, rely on precise and accurate phase-shift control which makes them very sensitive to timing issues due to mismatch, noise, etc. Timing issues can severely limit the performance of these generators especially in high-frequency applications where precise timing becomes challenging. In this paper, we analyze the effects of timing inaccuracies on high-speed harmonic cancellation generators and we propose circuit techniques for mitigating them. Electrical simulation results on a 1.45 GHz sinusoidal signal generator implemented in ST 28 nm FDSOI technology are provided to validate our proposals.

Published
2021

40. Component Based Framework for Designing and Validating Asynchronous Algorithms for Electrical Measurement and Protection

Author

Roland Bohrer, Frederic Rousseau, Benoit Leprettre, Frédéric Pétrot, Louis Bonicel, Schneider Electric ( SE), System Level Synthesis (SLS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), and Université Grenoble Alpes (UGA)

Subjects
Computer science, Distributed computing, Asynchronous processing, power system management, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], electric variables measurement, Limiting, limiting, embedded system, Asynchronous algorithms, Component (UML), PACS 85.42, Model-based design, software algorithm, Code generation, Reference architecture, computer architecture, software packages
Abstract

International audience; Component-based software engineering is appealing for industrial embedded systems design for two main reasons: these systems benefit from a strong legacy from previous iterations of the design reducing overall costs and time; and they target platform-independent development to minimize hardware dependent costs. However, such approaches are not yet developed for asynchronous algorithms, limiting the possibilities and performances of code generation. In this paper we propose a framework to describe, simulate, and test asynchronous processing algorithms via a Model Based Design (MBD) approach implemented in MathWorks Simulink. Our approach also facilitates code generation for such algorithms. We demonstrate our approach by designing and validating in simulation a reference architecture for electrical measurement and protection applications.

Published
2021

41. Estimation of Oxide Breakdown Voltage During a CDM Event Using Very Fast Transmission Line Pulse and Transmission Line Pulse Measurements

Author

Emmanuel Simeu, Jean-Daniel Arnould, Chloe Troussier, Johan Bourgeat, Blaise Jacquier, Reliable RF and Mixed-signal Systems (RMS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), STMicroelectronics [Crolles] (ST-CROLLES), Laboratoire de Radio-Fréquence et d'Intégration de Circuits (RFIC-Lab ), Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), and Université Grenoble Alpes (UGA)-Université Grenoble Alpes (UGA)

Subjects
010302 applied physics, oxide breakdown, Materials science, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], Transistor, CDM, ESD, 020206 networking & telecommunications, 02 engineering and technology, VF-TLP, 01 natural sciences, law.invention, Electric power transmission, Reliability (semiconductor), law, PACS 85.42, Logic gate, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Breakdown voltage, Event (particle physics), Transmission-line pulse, Voltage
Abstract

International audience; Using TLP (Transmission Line Pulse) and VF-TLP (Very Fast Transmission Line Pulse) to emulate a fast transient stress, a study of oxide reliability during a CDM (Charged Devise Model) event was done to establish an empirical law between the time to breakdown and the voltage applied to the gate. A wide array of transistors in different configurations was tested to reflect real situation during a CDM event.

Published
2021

42. RISC-V Online Tutor and Lab

Author

Morgan, Fearghal, Beretta, Arthur, Gallivan, Ian, Clancy, Joseph, Rousseau, Frédéric, Callaly, Franck, National University of Ireland [Galway] (NUI Galway), System Level Synthesis (SLS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), and BEN TITO, Laurence

Subjects
[SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, PACS 85.42, online training course, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

International audience; Online training and practice initiatives for learning programming have been embraced by Engineering and Computer Science communities. Codding training platforms are very effective at providing hands-on, self-paced inde-pendent learning, using a range of browser technologies, emulation tools, structured learning and assessment. Online learning with connectivity to remote integrated circuit hardware, with probing of internal signals in real time can contribute to a similar rich, learn-by-doing experience. This paper presents the RISC-V Online Tutor course which provides structured, self-paced, interactive RISC-V architecture and applications training and prac-tice, using the reported vicilogic platform. The paper presents the course structure, the interactive independent-learning pedagogy, and the resource in the vicilogic learning, prototyping and course builder platform. The course provides a relevant and topical application of digital design (RISC-V processor), and bridge s the gap between low-level processor hardware de-sign and high level C programming. The paper presents information on user practice, user opinion and analytics. Feedback indicates a high level of user satisfaction and effective independent learning and achievement, validating the technology enhanced learning strategy, and acknowledging the visually-rich interactive experience provided by the platform. RISC-V Online Tutor course availability is timely, with the growing interest in the RISC-V open-source Instruction Set Architecture, the low number of available books on RISC-V, and encouragement by the RISC-V Foundation of the development of training materials by universities and industry training providers.

Published
2021

43. Identification of Hardware Devices based on Sensors and Switching Activity: a Preliminary Study

Author

Honorio Martin, Giorgio Di Natale, Elena Ioana Vatajelu, Universidad Carlos III de Madrid [Madrid] (UC3M), Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), and IEEE

Subjects
Computer science, business.industry, 02 engineering and technology, Large range, Temperature measurement, 020202 computer hardware & architecture, Identification (information), Feature (computer vision), PACS 85.42, 0202 electrical engineering, electronic engineering, information engineering, 020201 artificial intelligence & image processing, Process variability, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Field-programmable gate array, business, Computer hardware, Voltage
Abstract

This work has been partially funded by the CNRS INS2I PUF2IOT 2020 projet and the UC3M program: Ayudas para la Movilidad del Programa Propio de Investigacion; International audience; Hardware device identification has become an im- portant feature for enhancing the security and the trust of interconnected objects. In this paper, we present a device iden- tification method based on measuring physical and electrical properties of the device, while controlling its switching activity. The method is general an applicable to a large range of devices from FPGAs to processors, as long as they embed sensors (such as temperature and voltage) and their measurements are available. The method is enabled by the fact that both the sensors and the effects of the switching activity on the circuit are uniquely affected by manufacturing-induced process variability. The device identification based on this method is made possible by the use of machine learning. The efficiency of the method has been evaluated by a preliminary study conducted on eleven FPGAs.

Published
2021

44. Scramble Cache: An Efficient Cache Architecture for Randomized Set Permutation

Author

Thomas Hiscock, Giorgio Di Natale, Amine Jaamoum, Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), IEEE, and Architectures and Methods for Resilient Systems (TIMA-AMfoRS )

Subjects
010302 applied physics, Computer science, CPU cache, business.industry, Cache-only memory architecture, Context (language use), 02 engineering and technology, 01 natural sciences, 020202 computer hardware & architecture, Set (abstract data type), Overhead (business), PACS 85.42, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Key (cryptography), Side channel attack, Cache, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, Computer network
Abstract

This work was funded thanks to the French national program ”Programme d’Investissement d’Avenir IRT Nanoelec” ANR-10-AIRT-05.; International audience; Driven by the need of performance-efficient computations, a large number of systems resort to cache memories. In this context, cache side-channel attacks have been proven to be a serious threat for many applications. Many solutions and countermeasures exist in literature. Nevertheless, the majority of them do not cope with the constraints and limitations imposed by embedded systems. In this paper, we introduce a novel cache architecture that leverages randomized set placement to defeat cache side-channel analysis. A key property of this architecture is its low impact on performance and its small area overhead. We demonstrate that this countermeasure allows protecting the system against known cache side-channel attacks, while guaranteeing small overheads, making this solution suitable also for embedded systems.

Published
2021

45. SRAM-PUF: Platform for Acquisition of Sram-Based Pufs from Micro-Controllers

Author

Vinagrero Gutierrez, Sergio, Martin, Honorio, Vatajelu, Elena Ioana, Di Natale, Giorgio, Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Universidad Carlos III de Madrid [Madrid] (UC3M), and BEN TITO, Laurence

Subjects
Hardware_MEMORYSTRUCTURES, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, PACS 85.42, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

International audience; This demonstration shows a versatile platform for the acquisition of the content of SRAM memories embedded in microcontrollers at power-up. The platform is able to power-off and -on hundreds of microcontrollers and to retrieve the content of their SRAMs thanks to a scan chain connecting all boards. The data collected is then stored in a database to enable reliability analysis.

Published
2021

46. Simulation of Ideally Switched Circuits in SystemC

Author

Fernandez-Mesa, B.J., Andrade Porras, Liliana Lilibeth, Pétrot, Frédéric, System Level Synthesis (SLS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), ANR-19-P3IA-0003,MIAI,MIAI @ Grenoble Alpes(2019), BEN TITO, Laurence, and MIAI @ Grenoble Alpes - - MIAI2019 - ANR-19-P3IA-0003 - P3IA - VALID

Subjects
[INFO.INFO-OH] Computer Science [cs]/Other [cs.OH], power system, circuits analogiques, PACS 85.42, switched circuit, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], SystemC, modeling, simulation, interrupteur idéal, electronique de puissance, modélisation
Abstract

International audience; Modeling and simulation of power systems at low levels of abstraction is supported by specialized tools such as SPICE and MATLAB. But when power systems are part of larger systems including digital hardware and software, low-level models become over-detailed; at the system level, models must be simple and execute fast. We present an extension to SystemC that relies on efficient modeling, simulation, and synchronization strategies for Ideally Switched Circuits. Our solution enables designers to specify circuits and to jointly simulate them with other SystemC hardware and software models. We test our extension with three power converter case studies and show a simulation speed-up between 1.2 and 2.7 times while preserving accuracy when compared to the reference tool. This work demonstrates the suitability of SystemC for the simulation of heterogeneous models to meet system-level goals such as validation, verification, and integration.

Published
2021

47. BenzoCycloButene-based in-Package Substrate Integrated Waveguides for sub-THz Applications

Author

Frédéric Aniel, Philippe Ferrari, Nicolas Zerounian, Loic Vincent, Florence Podevin, Giuseppe Acri, A.-S. Grimault-Jacquin, Luigi Boccia, Emmanuel Pistono, BEN TITO, Laurence, Laboratoire de Radio-Fréquence et d'Intégration de Circuits (RFIC-Lab ), Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Université Grenoble Alpes (UGA), Dipartimento di Ingegneria Informatica, Modellistica, Elettronica e Sistemistica [Calabria] (DIMES), Università della Calabria [Arcavacata di Rende] (Unical), Centre de Nanosciences et de Nanotechnologies (C2N), Université Paris-Saclay-Centre National de la Recherche Scientifique (CNRS), Centre Interuniversitaire de Micro-Electronique (CIME), and Institut National Polytechnique de Grenoble (INPG)

Subjects
Materials science, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, packaging, 02 engineering and technology, law.invention, chemistry.chemical_compound, law, Benzocyclobutene, 0202 electrical engineering, electronic engineering, information engineering, frequency measurement, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, substrates, attenuation, passive circuit, Electronic circuit, business.industry, Attenuation, 020208 electrical & electronic engineering, Q-factor, 020206 networking & telecommunications, CMOS, chemistry, PACS 85.42, Attenuation coefficient, Q factor, Interposer, Optoelectronics, attenuation measurement, business, Waveguide
Abstract

International audience; This paper introduces an experimental characterization of substrate integrated waveguide (SIW) components integrated in a benzocyclobutene-based interposer for WR10-band applications. High performance SIWs were experimentally validated, with a measured attenuation constant of 0.39 dB/mm and a quality factor of 27 at 90 GHz. The attenuation constant remains equal to 0.4 dB/mm between 85 GHz and 110 GHz and the quality factor reaches 40 in the upper end of the band. These results show the benefits offered by using benzocyclobutene 3D packaging for the realization of high performance passive circuits with lower cost and higher electrical performance as compared to standard CMOS technologies and concurrent packaging technologies.

Published
2021

48. Arbitrary and Variable Precision Floating-Point Arithmetic Support in Dynamic Binary Translation

Author

Frédéric Pétrot, Marie Badaroux, BEN TITO, Laurence, APPEL À PROJETS GÉNÉRIQUE 2018 - Améliorer la prédictibilité des calculs numériques - - ImPreNum2018 - ANR-18-CE46-0011 - AAPG2018 - VALID, MIAI @ Grenoble Alpes - - MIAI2019 - ANR-19-P3IA-0003 - P3IA - VALID, System Level Synthesis (SLS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), ANR-18-CE46-0011,ImPreNum,Améliorer la prédictibilité des calculs numériques(2018), and ANR-19-P3IA-0003,MIAI,MIAI @ Grenoble Alpes(2019)

Subjects
010302 applied physics, discrete event simulation, Floating point, Computer science, business.industry, Interface (computing), [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], Binary translation, Binary number, 02 engineering and technology, 01 natural sciences, IEEE floating point, 020202 computer hardware & architecture, Instruction set, [INFO.INFO-OH] Computer Science [cs]/Other [cs.OH], Software, Computer engineering, PACS 85.42, 0103 physical sciences, Arbitrary-precision arithmetic, arbitrary precision, 0202 electrical engineering, electronic engineering, information engineering, dynamic binary translation, business
Abstract

International audience; Floating-point hardware support has more or less been settled 35 years ago by the adoption of the IEEE 754 standard. However, many scientific applications require higher accuracy than what can be represented on 64 bits, and to that end make use of dedicated arbitrary precision software libraries. To reach a good performance/accuracy trade-off, developers use variable precision, requiring e.g. more accuracy as the computation progresses. Hardware accelerators for this kind of computations do not exist yet, and independently of the actual quality of the underlying arithmetic computations, defining the right instruction set architecture, memory representations, etc, for them is a challenging task. We investigate in this paper the support for arbitrary and variable precision arithmetic in a dynamic binary translator, to help gain an insight of what such an accelerator could provide as an interface to compilers, and thus programmers. We detail our design and present an implementation in QEMU using the MPRF library for the RISCV processor

Published
2021

49. Impact of radiation-induced soft error on embedded cryptography algorithms

Author

Vitor Bandeira, Luciano Ost, Rodrigo Possamai Bastos, Matheus Garay Trindade, Jack Sampford, Rafael Garibotti, Ricardo Reis, Universidade Federal do Rio Grande do Sul [Porto Alegre] (UFRGS), Phixos (Phixos), Pontifícia Universidade Católica do Rio Grande do Sul [Porto Alegre] (PUCRS), Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), and Loughborough University

Subjects
Computer science, Reliability (computer networking), Cryptography, 02 engineering and technology, 01 natural sciences, radiation-induced soft errors, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, XTEA, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Safety, Risk, Reliability and Quality, Field-programmable gate array, Throughput (business), ComputingMilieux_MISCELLANEOUS, FPGA, 010302 applied physics, reliability, AES, cryptography, business.industry, 020208 electrical & electronic engineering, Advanced Encryption Standard, Condensed Matter Physics, Atomic and Molecular Physics, and Optics, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, Soft error, PACS 8542, PACS 85.42, Tiny Encryption Algorithm, radiation test, business, Algorithm
Abstract

International audience; With the advance of autonomous systems, security is becoming the most crucial feature in different domains, highlighting the need for protection against potential attacks. Mitigation of these types of attacks can be achieved using embedded cryptography algorithms, which differ in performance, area, and reliability. This paper compares hardware implementations of the eXtended Tiny Encryption Algorithm (XTEA) and the Advanced Encryption Standard (AES) algorithms. Results show that the XTEA implementation gives the best relative performance (e.g., throughput, power), area, and soft error reliability trade-offs.

Published
2021

50. Automated Analog Fault Simulators: Application to Failure Analysis

Author

Melis, Tommaso, BEN TITO, Laurence, Reliable RF and Mixed-signal Systems (RMS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), and Université Grenoble Alpes (UGA)

Subjects
PACS 85.42, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS
Abstract

International audience

Published
2021

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