200 results on '"Ohji, Y."'
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2. Flat adenoma–carcinoma sequence with high-malignancy potential as demonstrated by CD10 and β-catenin expression: a different pathway from the polypoid adenoma–carcinoma sequence
3. Positron annihilation in SiO2/Si structure at low temperature
4. Positronium formation in SiO2 films grown on Si substrates studied by monoenergetic positron beams
5. Positron annihilation in a metal-oxide semiconductor studied by using a pulsed monoenergetic positron beam
6. Stoichiometry measurement and electric characteristics of thin-film Ta2O5 insulator for ultra-large-scale integration
7. Depth and lateral resolution of laser-assisted atom probe microscopy of silicon revealed by isotopic heterostructures.
8. Suppression of anomalous threshold voltage increase with area scaling for Mg- or La-incorporated high-k/Metal gate nMISFETs in deeply scaled region
9. A case of multiple carcinoid tumors of the small intestine
10. Study of Negative Vth Shift in PBTI and Positive Shift in NBTI for Yttrium Doped HfO2 Gate Dielectrics
11. Development of high-k / metal gate CMOS technology in Selete
12. Effect of Post Cap-Layer Deposition Annealing Temperature and TiN Thickness on SMDH CMOS Process using TiN Hard Mask
13. Influence of Post Cap-layer Deposition Annealing Temperature on MgO Diffusion in High-k/IFL Stacks
14. Three-Dimensional Observation of Edge-Roughness on Poly-Si/TiN Stacked Gate Using Three-Dimensional STEM
15. Effective-Work-Function Control by Varying the TiN Thickness in Poly-Si/TiN Gate Electrodes for Scaled High- $k$ CMOSFETs
16. Proposal of Single Metal/Dual High-$k$ Devices for Aggressively Scaled CMISFETs With Precise Gate Profile Control
17. Physical model of the PBTI and TDDB of la incorporated HfSiON gate dielectrics with pre-existing and stress-induced defects
18. Gate-first high-k/metal gate stack for advanced CMOS technology
19. Improvement of Metal/High-k Device Performance by 40-Milli-Second Flash Lamp Annealing by using Flexibly-Shaped-Pulse Technology
20. Dual Metal Gate Technology with Metal Inserted FUSI Stack (MIFS) using Single Phase FUSI for Scaled High-k CMOSFETs
21. Vertical Scaling of Metal/High-k Gate Stacked MOSFETs for Hp45 and Beyond
22. Vt Variation Suppressed Al2O3-Capped HfO2 Gate Dielectrics for Low Vt pMISFETs with High-k/Metal Gate Stacks
23. Impact of the Activation Annealing Temperature on the Performance, NBTI and TDDB Lifetime of High-k/Metal Gate Stack pMOSFETs
24. Full 3D string-level simulation of NAND flash device
25. Improved FET characteristics by laminate design optimization of metal gates - Guidelines for optimizing metal gate stack structure -
26. Physical understanding of the reliability improvement of dual high-k CMOSFETs with the fifth element incorporation into HfSiON gate dielectrics
27. Fabrication process controlled pre-existing and charge - discharge effect of hole traps in NBTI of high-k / metal gate pMOSFET
28. Single Metal/Dual High-k Gate Stack with Low Vth and Precise Gate Profile Control for Highly Manufacturable Aggressively Scaled CMISFETs
29. Capsule endoscopy findings in intestinal follicular lymphoma
30. Clinical impact of genetic aberrations in gastric MALT lymphoma: a comprehensive analysis using interphase fluorescence in situ hybridisation
31. Gastric MALT lymphoma with t(14;18)(q32;q21) involving IGH and BCL2 genes that responded to Helicobacter pylori eradication
32. Fermi-level pinning position modulation by Al-containing metal gate for cost-effective dual-metal/dual-high-k CMOS
33. Practical dual-metal-gate dual-high-k CMOS integration technology for hp 32 nm LSTP utilizing process-friendly TiAlN metal gate
34. Systematic studies on Fermi level pining of Hf-based high-k gate stacks
35. Wide Controllability of Flatband Voltage by Tuning Crystalline Microstructures in Metal Gate Electrodes
36. An SOI-Based 7.5/spl mu/m-Thick 0.15x0.15mm2 RFID Chip
37. Compact Modeling of Source-Side Injection Programming for 9Onm-Node AG-AND Flash Memory
38. Formation of S/D-extension using boron gas cluster ion beam doping for sub-50-nm PMOSFET
39. Impact of Vth interference suppression using a novel Poly Si shield on FLASH memories.
40. Advantages of B/sub 18/H/sub 22/ ion implantation and influence on PMOS reliability
41. Simulation of Drain Current Reduction Caused by Process-Induced Stress
42. A Novel STI Process from the View Point of Total Strain Process Design for 45nm Node Devices and Beyond
43. Suppression of Boron Penetration from S/D Extension to improve Gate Leakage Characteristics and Gate-Oxide Reliability for 65nm node CMOS and beyond
44. Pre-existing and process induced defects in high-k gate dielectrics ∼direct observation with EBIC and impact on 1/f noise∼.
45. Flexibly-Shaped-Pulse flash lamp annealing with assisted temperature control (FSP-FLAplus) to realize a wide range of annealing conditions.
46. Novel Substrate Engineering for High Performance CMOSFETs using Channeling Ion Implantation
47. Direct observation of fluctuations in both the number and individual carrier capture rate of interface traps in small gate-area MOSFETs.
48. Anomalous behavior in the dependence of carrier activation on implant dose for extremely shallow source/drain extensions activated by flash lamp annealing.
49. Multi-functional annealing using flexibly-shaped-pulse flash lamp annealing (FSP-FLA) for high-k/metal gated CMOS devices.
50. Improvement of pattern effect by optical-absorption carbon film and flexibly-shaped-pulse flash lamp annealing.
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