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This work concerns high resolution topography characterization at die scale of 28nm FDSOI CMOS technology by interferometric microscopy. It shows that usual test boxes (T-boxes) in scribe line are not representative of the full die topography. Consequently, new parameters are needed in order to take full advantage of high resolution topography characterization at die scale. In that sense, it is observed in this study that coupling full die and die @s ranges can provide new and relevant information about the Chemical Mechanical Polishing (CMP) processes. Moreover, high resolution die topography data makes possible to characterize in-die impact of a structure on its neighborhood and evaluate the pattern density dependency of the CMP processes.

For the first time, the interest of a new SiCO low-k spacer material deposited at 400°C is evaluated in the perspective of a 3D VLSI integration. The benefits of SiCO low-k (4.5 vs 7 for SiN) value is preserved throughout the whole integration and translates into a 5% decrease for both effective capacitance and delay of FO3 Ring Oscillators in a 14FDSOI technology. In addition, a NMOS breakdown voltage improvement of 3.5V and a decrease in leakage current of 0.7 decade is demonstrated on thick oxide devices. This electrical performance together with the low temperature deposition makes SiCO a very appealing candidate for 3D VLSI in a CoolCube™ integration scheme.

An enhanced trench first hard mask (TFHM) backend integration architecture has been developed to facilitate straightforward ultra low-k (ULK) material insertion and to enable rapid yield learning at the 65nm technology node. Parametric, yield, reliability, and RC performance data are presented for the fully-integrated, improved TFHM 300mm ULK backend

In this paper, an enhanced trench first hard mask (TFHM) 300mm low-k backend integration is studied for the 65nm technology node. This new integration scheme leads to new etch challenge (selectivity, residues or hard mask faceting). An approach change from full via to partial via has been evaluated. Electrical data have also shown a yield improvement for this enhanced integrated TFHM with regard to traditional TFHM

The continuous downscaling of interconnect dimensions in combination with the introduction of porous low-k materials has increased the number of integration challenges tremendously. The paper focuses mainly on the impact of porous low-k dielectrics on interconnect reliability. Numerous reliability issues are induced by their porosity compared to dense low-k materials. The impact of these mechanically inferior materials on packaging is well known. However, on top of the mechanical reliability, ultra low-k materials are extremely vulnerable to processing (especially to plasmas), due to their inherent porosity. Additionally, it is difficult to deposit a continuous, thin barrier on porous low-k interfaces. The inferior properties of porous low-k materials as compared to their dense equivalents are thought to induce numerous reliability issues, which are in addition to the ones caused by the continuous downscaling of metal lines and dielectric spacings. All of this together has an enormous impact on the reliability of the end product.

Mechanical reliability is widely recognized as the primary obstacle to productionization of porous low-k materials. The combination of weak bulk and interfacial properties with increasingly complex geometries poses a considerable challenge at the 65-nm node. The final solution must be sufficiently robust so as to ensure compatibility with multiple substrate types, interconnect configurations and packages. In this work, material engineering, modeling, design rule tailoring, and assembly optimization are employed to achieve required assembly reliability for both wirebond and flip-chip packages, for both bulk and SOI substrates.

Given the much discussed challenges of interconnect scaling at the 65-nm node, the choice of process architecture is a key determinant of performance and extendibility. An alternate trench-first with hardmask integration is described in this work, including subsequent benefits. BEOL design rules are detailed for the 65-nm architecture, supporting both "low-k" and "ultra-low-k" backends, satisfying RC scaling requirements. Electrical parametric performance and yield are presented for a fully-integrated 300mm backend utilizing 65-nm design rules demonstrating the viability of this architecture for the 65-nm node and beyond.

Dual damascene integration of porous CVD SiOC low-k material was performed for interconnects of the 65 and 45 nm technology nodes. Deposition processes with dielectric constant of 2.4 and 2.2 were developed and characterized. Low-k integration was performed with feature sizes down to 85 nm. Etch and strip processes compatible with this ultra low-k investigated and lead to the successful dual damascene integration, illustrated by physical and electrical results such as low leakage current, via chain and line resistances. The k-value after integration was preserved at its initial value.