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The parasitic bipolar amplification of silicon on insulator (SOI) devices is analyzed as a function of the technology integration from 0.8 [micro]m down to 0.1 [micro]m. Experiments and simulations show that the bipolar gain does not increase with technology downscaling. The body tie efficiency, to reduce the bipolar amplification, is measured on both transistors and circuits. Implications on the dose rate hardness are deduced on registers with and without body ties as a function of the SOI technology integration. Index Terms--Parasitic bipolar transistor, silicon on insulator (SOI) technologies, transient irradiation.

The sensitivity to heavy ions of nonhardened 0.25-[micro]m partially depleted (PD) silicon on insulator (SOI) and bulk technologies is studied with experiments, device, and circuit simulations. Comparable threshold linear energy transfer (LET) are found for both technologies. Nevertheless, SOI saturated cross section is much lower than bulk one. For nonhardened technologies, SOI is then less sensitive than bulk to heavy ions. Index Terms--Circuit and device simulations, heavy ion irradiation, silicon on insulator (SOI) and bulk technology, single event upset (SEU) sensitivity.

Charge collection measurements on SOI diodes have been performed with heavy ion microbeam and pulsed focused laser. Both irradiation techniques show that no electrical coupling occurs. However, laser measurements show an optical coupling effect when irradiation occurs close to the isolation trench. Qualitative electromagnetic simulations have been performed to confirm and describe the optical coupling. Index Terms--Charge collection, heavy ion, pulsed laser, SOI.

DMILL technology integrates mixed analog-digital very rad-hard (>10 Mrad and > [10.sup.14] neutron/[cm.sup.2]) vertical bipolar, 0.S[[micro]meter] CMOS and 1.2 [[micro]meter] PJFET transistors on SOI substrate. In this paper, after a presentation of the DMILL program goal, we discuss in more detail the main technological choices, the main milestones from the R&D to the industrial implementation, and the main results obtained after stabilization of the final process-flow in the MHS foundry.

Effects of the radial density distribution of carriers generated in a single ion track have been observed in thin silicon detectors. These devices have been irradiated with either an ion microbeam at low energy or a high-energy standard ion beam. We describe the mode of operation of the tested structure, and propose an interpretation of the experimental charge collection data to extract information on the ion track profile. Experimental results are compared to 3D simulations and simplified analytical profiles.

The impact of ion energy on single-event upset was investigated by irradiating CMOS SRAMs with low and high-energy heavy ions. A variety of CMOS SRAM technologies was studied, with gate lengths ranging from 1 to 0.5 [[micro]meter] and integration densities from 16 Kbit to 1 Mbit. No significant differences were observed between the low and high-energy single-event upset response. The results are consistent with simulations of heavy-ion track structures that show the central core of the track structures are nearly identical for low and high-energy ions. Three-dimensional simulations confirm that charge collection is similar in the two cases. Standard low-energy heavy ion tests are more cost-effective and appear to be sufficient for CMOS technologies down to 0.5 [[micro]meter]. We discuss implications for deep submicron scaling, multiple-bit upsets, and hardness assurance.

A latch effect induced by total dose irradiation is observed in short channel SOI transistors. This effect appears on NMOS transistors with either a fully or a partially depleted structure. It is characterized by a hysteresis behavior of the Id-Vg characteristics at high drain bias for a given 'critical' dose. Above this dose, we still observe a limited leakage current at low drain bias (0.1 V), but a high conduction current at high drain bias (2 V) as the transistor should be in the off-state. The critical dose above which the latch appears strongly depends on gate length, transistor structure (fully or partially depleted), buried oxide thickness and supply voltage. Two-dimensional (2D) numerical simulations indicate that the parasitic conduction is due to the latch of the back gate transistor triggered by charge trapping in the buried oxide. To avoid the latch induced by the floating body effect, different techniques can be used: doping engineering, body contacts, etc. The study of the main parameters influencing the latch (gate length, supply voltage) shows that the scaling of technologies does not necessarily imply an increased latch sensitivity. Some technological parameters like the buried oxide hardness and thickness can be used to avoid latch, even at high cumulated dose, on highly integrated SOI technologies.

Investigation of single event effects at grazing angle by both charge collection and multiple bit upset measurements evidences modified collection mechanisms with charge transfer between adjacent reverse biased structures.

This work concerns the development of a radiation hardness assurance methodology specially devoted to CMOS, JFET and bipolar transistors used in high total dose level environments. On the basis of recent studies, high temperature, high dose rate irradiations were performed. We propose a test procedure which combines high temperature irradiations and isochronal anneals for the qualification.

Radiation hardness of LiNb[O.sub.3] : Ti Mach-Zehnder optomodulators under high energy electron pulses at high dose rate is studied for the first time. Both electrical and optical measurements are performed at various dose rates and electrical bias conditions. Electrical and optical perturbations are observed to be synchronous of the irradiation pulse, below a total dose threshold of 1 krad(Si). The optical behavior of the various optomodulators under test is related to their structure. As a matter of fact, optical perturbations are due either to photocurrent which superposes to electrical bias, or to an alteration of couplers characteristics.

In this work, we study the trapping properties of Unibond[R] oxides. We measure its radiative response under different irradiation conditions using both point-contact and MOS transistors. The results obtained show both hole and electron trapping, as previously observed in SIMOX. But in the Unibond[R] case, there is a positive shift of the threshold voltage at very high doses. Using a simple model, we explain this shift by considering a second type of electron traps.

For devices irradiated from the front and the back, where ions have the same LET in the sensitive volumes, the SEU sensitivities and charge collection spectra are different. A specific test setup has been developed to make precise measurements of both collected charge and SEU in CMOS SRAMs. We present a set of new data and discuss the possible experimental artifacts that could affect these measurements. In all the cases, the device is more sensitive when irradiated from the back than from the front. This phenomenon seems related to energy transfer mechanisms from the ion to the material target, with secondary particles from both electronic and nuclear reactions being forward emitted. This effect may influence to net sensitivity of scaled down devices, with shallow sensitive layers, and heavy metal interconnects.

Individual ionizing heavy ion events are shown to cause two or more adjacent memory cells to change logic states in a high density CMOS SRAM. A majority of the upsets produced by normally incident heavy ions are due to single-particle events that causes a single cell to upset. However, for grazing angles a majority of the upsets produced by heavy-ion irradiation are due to single-particle events that cause two or more cells to change logic states. Experimental evidence of a single proton-induced spallation reaction that causes two adjacent memory cells to change logic states is presented. Results from a dual volume Monte-Carlo simulation code for proton-induced single-event multiple upsets are within a factor of three of experimental data for protons at normal incidence and 70 degrees.

We present experimental measurements of charge collection spectroscopy from high energy ion strikes in submicron CMOS/SOI devices. Due to the specific structure of SOI technology, with symmetrical source and drain junctions, a direct equivalence between upset mechanism and charge collection is established. The bipolar mechanism, responsible for the amplification of the deposited charge is discussed based on 2D device simulations. based on the experimental data we determine qualitatively the influence of transistor geometry on the bipolar gain. Finally the limits of the usual SEU concepts (LET threshold and cross section) are discussed for scaled devices.

Enhanced total dose damage of Junction Field-effect Transistors (JFETs) due to low dose rate and/or elavated temperature has been investigated for elementary p-channel structures fabricated on bulk and SOI substrates as well as for related linear integrated circuits. All these devices were fabricated with conventional junction isolation (field oxide). Large increases in damage have been revealed by performing high temperature and/or low dose rate irradiations. These results are consistent with previous studies concerning bipolar field oxides under low-field conditions. They suggest that the transport of radiation-induced holes through the oxide is the underlying mechanism. Such an enhanced degradation must be taken into account for low dose rate effects on linear integrated circuits.

We have studied the electrical and optical response of two laser diodes under transient irradiation. Both diodes exhibit a positive photocurrent, which adds to the bias current, and a decrease of the optical power until extinction when dose rate is increased. Direct carder generation in the laser cavity is a second order phenomena. The diode overall response is driven by both the substrate photocurrent and the transient conduction of current confinement regions, which decrease the net current density in the cavity and switches-off the laser emission. This behaviour is in good agreement with pulsed electrical characterizations and 2D simulations.

Multiple Bit Upsets (MBU) have been studied in a 256k CMOS static RAM irradiated at normal incidence and grazing angle. In normal incidence the sensitive areas have been identified with pulsed laser irradiation. The laser power thresholds have been determined for single to quadruple upsets in adjacent cells. Both experimental data and 3D simulations emphasize the role of delayed charge collection, by diffusion, and charge sharing between sensitive areas. Upset tracks have been recorded at grazing angle and used to determine the charge collection depth. These data revealed the existence of an LET threshold for MBU at grazing angle. As the ion LET increases different types of tracks are observed and correlated to the topological pattern in adjacent memory cells. This phenomenon is due to an unexpected charge collection mechanism, which couples adjacent sensitive areas and results in charge transfer between memory cells. The comparison with previous data on the same device indicates a strong influence of both ion energy and angle of incidence on the cross section, emphasizing the intrinsic limitation of standard characterizations with low energy ions. These results indicate that the basic assumption of a rectangular parallelepipedic volume does not take into account coupling phenomena, such as occurs in MBUs, and is no longer valid at grazing angle.

The trapped charge density in the LOCOS bird's beak resulting from irradiating a conventional NMOSFET has been analysed using a 2D finite element simulation. This paper shows a maximum of trapped charge density in the bird's beak region. The resulting voltage shift of the lateral parasitic transistor in the bird's beak region induces a high leakage current, and prevents any normal circuit operation. The silicon doping level, the supply voltage and the bird's beak shape are key parameters for device hardening of rad-tolerant technologies.

High Energy Physics experiments under preparation at CERN (Geneva, Switzerland) with the future LHC (Large Hadron collider) require a fast, low noise, very rad-hard, mixed analog-digital microelectronics VLSI technology. Readout electronics designed using such a technology for the central parts of the LHC particle detectors must withstand more than 10 Mrad (Si[O.sub.2]) and [10.sup.14] neutrons/[cm.sup.2] over 10 years of operation. We present here recent results obtained with a new rad-hard analog-digital technology called [DMILL.sup.1] [1-8], which monolithically integrates NPN bipolar, CMOS and P-JFET transistors, and which has been specifically developed to fulfill the severe constraints of LHC detector readout circuits.

We describe transient effects induced by high energy protons in shift registers processed in a CMOS/thick SOI technology. Devices are tested in dynamic mode. The dependence of cross section on frequency, signal rise time, angle of incidence and proton energy is studied and interpreted.

We have studied transient irradiation effects on the optical and electrical responses of a laser diode. The influence of dose rate, ranging from [10.sup.9] to [10.sup.12] rad(Si)/s, has been investigated through a complete experimental study. Dose rate vulnerability of the laser diode has been observed. Electrical and optical transient responses are determined by the dose rate, the diode structure, and its operating point.

We have studied the sensitivity of a 256 kbit CMOS/epi SRAM to transient phenomena (protons and ions SEU, dose rate). Local and global failure mechanisms are observed and discussed. For single particles, or at low dose rate, cell upsets are uncorrelated. When the dose rate is increased, correlated failures are due to both cell photocurrent summation (rail span collapse) and supply voltage drop in pheripheral circuits. The transition between uncorrelated to correlated failures is interpreted, on the basis of device structure and pattern influence.

Due to their limited sensitive volumes for charge collection, silicon on insulator (SOI) technologies are good candidates for any microelectronic device operating in a space environment. While being insensitive to latchup phenomena, SOI devices may experience single-event effects (SEE's). Based on the analysis of the various structures of SOI transistors, charge collection mechanisms are presented. The different models proposed to analyze the sensitivity of CMOS SRAM cells are then discussed. The available data of SEU characterizations are finally compiled.

We present experimental results from a fast charge amplifier and a wideband analog buffer processed in the DMILL BiCMOS-JFET radhard SOI technology and irradiated up to 4.5 X [10.sup.14] protons/[cm.sup.2]. In parallel, we have irradiated elementary transistors. These components were biased and electrical measurements were done 30 min after beam stop. By evaluating variations of main SPICE parameters, i. e., threshold voltage shift for CMOS and current gain variation for bipolar transistors, we have simulated the wideband analog buffer at different doses. These SPICE simulations are in good agreement with measured circuit degradations. The behavior of the charge amplifier is consistent with extraction of transconductance and pinch-off voltage shift of the PJFET.

We present a theoretical study of the behavior of basic CMOS/SOI inverter and static memory cell struck by an energetic ion. This work is based on 3D Monte Carlo device simulation. CMOS cells are made up of ultra-thin SOI film 0.25 [[micro]meter] MOSFETs without body ties operating in fully-depleted mode. The ion track is simulated by electron-hole pairs generation with an energy of 1 eV for each carrier. We took a particular care to quantify file radiation effect as a function of Linear Energy Transfer (LET) of file ion. After irradiation of the off-state N-MOS of the inverter, electrons in excess are drained-off by source and drain contacts. Due to the lack of hole contact, excess holes tend to remain accumulated in the channel initiating a parasitic bipolar transistor mechanism. The electron current, flowing from source to drain, discharges the output capacitor, which result in a transient upset. The recovery time is then controlled by recombination of excess holes. For memory cell, even after recombination of excess holes stored in the channel, the return m initial logic state could not be achieved, which constitutes a definitive single event upset (SEU). As this would occur for LET as low as 3 MeV.[cm.sup.2].[mg.sup.-1], hardening techniques for 0.25 [[mirco]meter] CMOS/SOI devices are finaly discussed.

We present here recent results obtained on a rad-hard mixed analog-digital technology currently under development, which integrates monolithically complementary MOS transistors (CMOS), complementary JFETs (CJFETs) and complementary bipolar transistors (C-bipolars). This technology is expected to fulfill the hard constraints of LHC detector electronics.

Charge trapping effects in SIMOX buried oxides have been investigated at total doses up to 100 megarad(SiO2) as a function of substrate bias. Hole and electron trapping are controlled by the oxide internal electric field.

The parasitic bipolar amplification in MOS/SOI transistors determines the SEU sensitivity of actual devices. This response is experimentally measured in a set of single transistors using a focused picosecond laser with submicrometer spatial resolution. This technique, validated by comparing the SEU behavior of registers irradiated with both laser and heavy ions, is relevant for both device physics and hardness assurance applications.

The worst case bias during total dose irradiation of partially depleted SOI transistors from two technologies is correlated to the device architecture. Experiments and simulations are used to analyze SOI back transistor threshold voltage shift and charge trapping in the buried oxide.

We present the first experimental determination of the SEB sensitive area in a power MOSFET irradiated with a high-LET heavy-ion microbeam. We used a spectroscopy technique to perform coincident measurements of the charge collected in both source and drain junctions together, with a non-destructive technique (current limitation). The resulting charge collection images are related to the physical structure of the individual cells. These experimental data reveal the complex 3-dimensional behavior of a real structure, which can not easily be simulated using available tools. As the drain voltage is increased, the onset of burnout is reached, characterized by a sudden change in the charge collection image. 'Hot Spots' are observed where the collected charge reaches its maximum value. Those spots, due to burnout triggering events, correspond to areas where the silicon is degraded through thermal effects along a single ion track. This direct observation of SEB sensitive areas as applications for, either device hardening, by modifying doping profiles or layout of the cells, or for code calibration and device simulation.