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The design and manufacturing steps of a chip typically involve several parties. For example, a chip may comprise several third-party Intellectual Property (IP) cores and the Integrated Circuit (IC) fabrication may be outsourced to a third-party foundry. IP cores and ICs are shared with potentially untrusted third parties and, as a result, are subject to piracy attacks. Even more, any legally purchased chip may be reverse-engineered to retrieve the design down to transistor-level and, thereby, it is also subject to piracy attacks. In this paper, we propose MixLock, an anti-piracy countermeasure for mixed-signal IP cores and ICs. MixLock protection is based on inserting a lock mechanism into the design such that correct functionality is established only after applying a key which is the designer’s secret. The lock mechanism acts on the mixed-signal performances by leveraging logic locking of the digital part. MixLock presents several key attributes. It is generally applicable, it is non-intrusive to the sensitive analog section, it incurs no performance penalty and has very low area and power overheads, it is fully automated, and it is capable of co-optimizing security in both the analog and digital domains. We demonstrate MixLock on a Σ Analog-to-Digital Converter (ADC) using hardware measurements and an audio demonstrator.

This paper presents an open-source framework for emulating mixed-signal chip designs on an FPGA. It includes a Python-based synthesizable model generator for mixed-signal blocks (msdsl), a fixed- and floating-point synthesizable SystemVerilog library for representing real numbers (svreal), and a Python-based tool that generates emulator control infrastructure and automates the FPGA build process (anasymod). The framework includes features for efficiently modeling analog dynamics, nonlinearity, and noise, often making use of compile-time caching to reduce the required computational resources of the FPGA. We demonstrate the framework’s generality by discussing three applications: a high-speed link receiver (DragonPHY), a firmware-controlled flyback converter, and an NFC-powered chip. Our framework makes it easy to emulate these systems, while providing runtimes 2-3 orders of magnitude faster than CPU simulations with real number functional models.

Optical receivers (ORXs) with integrated CMOS electronics enable compact, low-power solutions for 400-G Ethernet and co-packaged optics. In this article, we present a 100-Gb/s PAM-4 ORX with TIA and sampler integrated into a single 28-nm CMOS IC. ORX sensitivity is optimized using a low noise, sub-Nyquist bandwidth TIA followed by a mixed signal sampler that includes 2-tap FFE and 2-tap DFE. A distributed current-integrating summer helps meet feedback latency requirements of 50-Gbaud direct-feedback PAM-4 DFE. Measurements characterizing the CMOS linear TIA indicate ~23-GHz trans-impedance (ZT) bandwidth (BW) with-2.5 μA $_{{rms}}$ input-referred noise. Optical measurement results at 100 Gb/s show that -8.9-dBm sensitivity is achieved at 2.4e-4 BER with 3.9-pJ/bit energy efficiency.

In this paper, we propose a novel approach to designing an algebraic signature analyzer that can be employed for mixed-signal systems testing. Due to its algebraic nature, the analyzer does not contain carry propagating circuitry. This helps to improve its error immunity, as well as performance. The proposed scheme can also be used in arithmetic/algebraic error-control coding and cryptography.

Reconfigurable architectures are more prominent in modern-day multi-band radio systems. This work has been conceptualized for a flexible 8-bit digitally controlled oscillator (DCO) design to suit r...

In low output voltage and high output current LLC resonant converter applications, a synchronous rectification (SR) is essential component for high efficiency and high power density. However, stray inductances in MOSFET package and printed circuit board (PCB) pattern make premature turn- off of SR gate and large SR dead time. To compensate the stray inductance effect and increase system efficiency, a hysteresis band dead time regulation control method is proposed. In the proposed control method, SR dead time is regulated to predetermined dead time target regardless of the stray inductances by using a mixed signal, which includes instantaneous drain voltage information and previous cycle dead time information. As a result, the proposed control method can provide lower conduction losses by the dead time regulation and better transient characteristic by the instantaneous drain voltage information. To verify the validity of the proposed control method, 234-W prototype is built and experimented with the proposed controller, which is implemented with 0.25- μ m BCDMOS technology.

For precise health status monitoring and accurate disease diagnostics in the current COVID-19 pandemic, it is essential to detect various kinds of target signals robustly under high noise and strong interferences. Moreover, the health monitoring system is preferred to be realized in a small form factor for convenient mass deployments. A CMOS-integrated coherent sensing platform is proposed to achieve the goal, which synergetically leverages quadrature coherent photoacoustic (PA) detection and coherent radar sensing for achieving universal healthcare. By utilizing configurable mixed-signal quadrature coherent PA detection, high sensitivity and enhanced specificity can be achieved. In-phase ( I ) and quadrature ( Q ) templates are specifically designed to accurately sense and precisely reconstruct the target PA signals in a coherent mode. By mixed-signal implementation leveraging an FPGA to generate template waveforms adaptively, accurate tracking and precise reconstruction on the target PA signal can be attained based on the early-late tracking principle. The multiplication between the received PA signal and the templates is implemented efficiently in analog-domain by the Gilbert cell on-chip. In vivo blood temperature monitoring was realized based on the integrated PA sensing platform fabricated in a 65-nm CMOS process. With an integrated radar sensor deployed in the indoor scenario, noncontact monitoring on respiration and heartbeat rates can be attained based on electromagnetic (EM) sensing. By complementary usage of PA-EM sensing mechanisms, comprehensive health status monitoring and precise remote disease diagnostics can be achieved for the currentglobal COVID-19 pandemic and the future pervasive healthcare in the Internet of Everything (IoE) era.

Analog and mixed-signal (AMS) computer-aided design tools are of increasing interest owing to demand for the wide range of AMS circuit specifications in the modern system on a chip and faster time to market requirement. Traditionally, to accelerate the design process, the AMS system is decomposed into smaller components (called modules ) such that the complexity and evaluation of each module are more manageable. However, this decomposition poses an interface problem, where the module’s input-output states deviate from when combined to construct the AMS system, and thus degrades the system expected performance. In this article, we develop a tool module-linking-graph assisted hybrid parameter search engine with neural networks (MOHSENN) to overcome these obstacles. We propose a module-linking-graph that enforces equality of the modules’ interfaces during the parameter search process and apply surrogate modeling of the AMS circuit via neural networks. Further, we propose a hybrid search consisting of a global optimization with fast neural network models and a local optimization with accurate SPICE models to expedite the parameter search process while maintaining the accuracy. To validate the effectiveness of the proposed approach, we apply MOHSENN to design a successive approximation register analog-to-digital converter in 65-nm CMOS technology. This demonstrated that the search time improves by a factor of 5 and 700 compared to conventional hierarchical and flat design approaches, respectively, with improved performance.

We propose a Built-In Self-Test (BIST) paradigm for analog and mixed-signal (A/M-S) Integrated Circuits (ICs), called symmetry-based BIST ( SymBIST ). SymBIST exploits inherent symmetries in an A/M-S IC to construct signals that are invariant by default, and subsequently checks those signals against a tolerance window. Violation of invariant properties points to the occurrence of a defect or abnormal operation. SymBIST is designed to serve as a functional safety mechanism. It is reusable ranging from post-manufacturing test, where it targets defect detection, to on-line test in the field of operation, where it targets low-latency detection of transient failures and degradation due to aging. We demonstrate SymBIST on a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). SymBIST features high defect coverage, short test time, low overhead, zero performance penalty, and has a fully digital interface making it compatible with modern digital test access mechanisms.

Recently, there have been many studies attempting to take advantage of advancements in Artificial Intelligence (AI) in Analog and Mixed-Signal (AMS) circuit design. Automated circuit sizing optimization and improving the accuracy of performance models are the two predominant uses of AI in AMS circuit design. This paper first introduces and explains the basic concepts in AI especially the ones that are more suitable to this application. Next, it surveys some recent studies of various AI techniques for AMS circuit design. Then, it discusses the main approaches as well as the pros and cons of each method. Finally, it gives meaningful insights about the current challenges and open issues, as well as recommends approaches for specific applications.

Information flow tracking (IFT) is a widely used methodology for ensuring data confidentiality and/or integrity in electronic systems and many such methods have been developed at various software or hardware description levels. Among them, Proof-Carrying Hardware Intellectual Property (PCHIP) introduced an IFT methodology for digital hardware designs described in hardware description languages (HDLs). However, it is not only the digital domain that suffers from the risk of inadvertent information leakage. Indeed, analog signals originating from sources of sensitive information such as biometric sensors, as well as analog circuit outputs could also carry confidential information. Moreover, analog circuits are equally susceptible as their digital counterparts to malicious modifications, known as hardware Trojans, which could introduce covert channels for leaking such confidential information. Furthermore, in analog/mixed-signal circuits, such information leakage channels may cross the analog/digital or digital/analog interface, making their detection even harder and, thereby, intensifying this security concern. As a solution, we introduce a PCHIP-based methodology which enables systematic formal evaluation of information flow policies in analog/mixed-signal designs. This solution can reason on analog designs described at the transistor-level or at the block-level, where an abstract model of the analog circuit is considered. Additionally, it can handle analog circuit models developed in Verilog-A or Verilog-AMS, thereby enabling the use of circuit models developed in these HDLs for IFT purposes. By integrating IFT across the digital and analog domains, the proposed solution is able to detect sensitive data leakage from the digital domain to the analog domain and vice-versa, without requiring any modification of the current analog/mixed-signal circuit design flow.

This article introduces a re-configurable pipeline analog-to-digital converter (ADC) deliberated for implantable surveillance devices for bio-impedance monitoring systems. To improve the efficiency of the bio-impedance method, an automatic adaptation circuit is introduced. This adaptive unit is responsible for setting the resolution and sampling rate on the basis of amplitude and frequency of the signal. Using a new, low-power automatic adaptation circuit low power consumption is achieved by using Dynamic Threshold metal oxide semiconductor (DTMOS) technique, it can automatically determine its setup. The converter has two modes of operations. In high-resolution mode, the converter has a 12-bit resolution and at low resolution mode, 8-bit resolution is used. The ADC bandwidth of low-speed mode is 100 kHz and high-speed mode is 1 GHz. The architecture is designed using 180 nm technology and simulated using Cadence virtuoso tool. The results achieved, low power consumption i.e. 0.844 mw, and it is operated with 1 V power supply. For signal to noise and distortion ratio (SNDR), effective number of bits (ENOB), the converter utilizes 71.06 dB, 11.45 in 12-bit and 72.3 dB, 7.41 in 8-bit mode respectively. By using proposed method around 20% of power consumption is reduced and 40% power supply is decreased. The proposed design is also used for mixed signal circuit testing.

This article presents a fully integrated gesture and gait classification system-on-chip (SoC) for rehabilitation application. In order to reduce the power consumption and area cost on the analog front end, special analog-to-digital converter (ADC)-less mixed-signal feature extraction (MSFE) circuits were designed to directly generate eight commonly used time-domain features to eliminate the area cost of ADC. A fully connected neural network classifier was implemented supporting: 1) on-chip learning to deliver user-specific training for better classification accuracy; 2) dedicated neural network layer to support gait classification; and 3) multi-chip data communication, which transfers only low-dimensional features from the neural network to minimize the communication bottleneck in a sensor fusion environment. A 12-channel test chip was fabricated in a 65-nm low-power process to demonstrate the proposed techniques. The measurements show an average power of $1~\mu \text{W}$ per channel and a 3-ms computational latency as required by the stringent rehabilitation requirement. In addition, the MSFE circuits achieve $3\times $ saving of area compared with the conventional approach, while the communication bandwidth was reduced by $100\times $ due to the transferring of only low-dimensional feature data from the neural network among multiple chips.

The Internet of Everything (IoE), clearly a 21st century's technology, brilliantly plays with digital data obtained from analog sources, bringing together two different realities, the analog (physical/real), and the digital (cyber/virtual) worlds. Then, with the boundaries of IoE still analog in nature, the required functions at the interface involve sensing, measuring, filtering, converting, processing, and connecting, which imply that the analog layer governs the entire system in terms of accuracy and precision. Furthermore, such interface integrates several analog and mixed-signal subsystems that comprise mainly signal transmission and reception, frequency generation, energy harvesting, data, and power conversion. This paper sets forth a state-of-the-art design perspective of some of the most critical building blocks used in the analog/digital interface, covering wireless cellular transceivers, millimeter-wave frequency generators, energy harvesting interfaces, plus, data and power converters, that exhibit high quality performance achieved through low-power consumption, high energy-efficiency, and high speed.

The level shifters (LSs) are the most significant interfacing circuits in multi-supply mixed-signal systems. This letter presents a high-speed and energy-efficient voltage level shifter with wide-range conversion from sub-threshold to I/O voltage. The proposed level shifter with split-control output driver significantly enhances the speed, energy and static power performance. The proposed LS is implemented in 0.18 $$\upmu $$ m CMOS technology, and simulation results confirm that it efficiently converts sub-threshold input voltage (240 mV) to nominal output voltage (1.8 V) without employing multi-threshold devices. The proposed LS exhibits delay of 6.43 ns and energy/transition of 38.39 fJ with significantly low switching current for 0.4 V/1 MHz input signal and 1.8 V output level.

The aim of this paper is to bring forward a novel hetero-material electrically doped (ED) GAA TFET for high-performing and power efficient mixed signal applications. A number of low and high band gap III–V semiconductors were considered at source and drain channel regions, and their electrical characteristics were compared to identify the best alternative. To that end, DC/RF/linearity properties of AlGaSb/GaAsP, Ge/GaAs, Si/GaAs, Si/Ge, Silicon and SiGe/Si based ED GAA TFETs were analyzed. We found that the AlGaSb/GaAs-ED-TFET provides 16 $$\mu \hbox {A}$$ ON current at 25 mV/decade subthreshold swing and 1e13 $$I_{ON}/ I_{OFF}$$ ratio with exceptional analog and linearity characteristics. Also, we found that interface trap charges (ITC) in AlGaSb/GaAs-ED-TFET present negligible impact and have no effect on system performance. Further, improvisation is possible through mole fraction optimization of $$Al_{x}Ga_{1-x}Sb$$ . Finally, the mixed signal components that are widely available in system architectures are implemented using AlGaSb/GaAs-ED-TFET and their performance criteria are measured. All device simulations were performed using the TCAD Silvaco tool, and look-up based Verilog-A technique was used for circuit simulation in Cadence.

Resistive random access memory (RRAM)-based compute-in-memory architecture helps overcome the bottleneck caused by large memory transactions in the convolutional neural network (CNN) accelerators. However, their deployment using 2-D IC technology faces challenges, as today’s RRAM cells remain at legacy nodes above 20 nm due to high programming voltages. Besides, power-hungry analog-to-digital converter (ADC) units limit the throughput of RRAM accelerators. In this article, we present the first-ever heterogeneous (multiple technology nodes) mixed-signal monolithic 3-D IC designs of the RRAM CNN accelerator. Our RRAM remains at legacy 40-nm nodes in one tier, but CMOS periphery scales toward advanced 28/16 nm in another tier. Our 3-D designs overcome the bottleneck caused by ADCs and offer up to $4.9\times $ improvement in energy efficiency in TOPS/W and up to 50% reduction in footprint area over 40-nm 2-D IC designs. Compared with existing 2-D works, our 3-D architecture offers up to $28.6\times $ improvement in energy efficiency.

Time-series classification (TSC) is a challenging problem in machine learning and significant efforts have been made to improve its speed and computation efficiency. Among various approaches, dynamic time warping (DTW) algorithm is one of the most prevalent methods for TSC due to its succinctness and generality. To improve the throughput of the operation, this work presents a mixed-signal DTW accelerator utilizing mixed-signal time-domain (TD) computing where signals are encoded and processed using time pulses. A pipelined operation is enabled by a specially designed time flip-flop (TFF) circuit leading to dramatic improvements in performance and scalability of the operation. A 65-nm CMOS test chip was implemented and measured. The results show more than $9\times $ improvements in throughput compared with prior work on TSC. As most existing TD designs suffer from the lack of TD storage elements, this work utilizes sequential circuit elements in TD computing extending the capability of time-based circuits.

Recent integration of Resistive Random Access Memory (RRAM) with standard CMOS has spurred exploration of high-density and low-power in-memory computing. RRAM arrays are being intensely investigated for analog-domain Vector Matrix Multiplication (VMM) and Neuromorphic Computing. However, to exploit the advantages of RRAM over other forms of nonvolatile memories, mixed-signal circuit designers need to accommodate their device nonidealities, and design circuits to translate high-level deep neural network algorithms to mixed-signal hardware. This brief reviews the field of neuromorphic computing using hybrid CMOS-RRAM circuits, associated circuit design challenges, and potential approaches for their mitigation, followed by benchmarking of recent demonstrations.

This study presents the analysis and reduction of vertical crosstalk in mixed-signal 3-D integrated circuits (3-D ICs) with multilayer graphene nanoribbon (MLGNR) and multiwall carbon nanotube (MWCNT) interconnects. The 14-nm technology node is considered for both digital and analog tiers. The assessments are conducted regarding the scattering parameters (S-parameters) for the equivalent circuit model of the transmission lines using the Advanced Design System (ADS) tool. Our studies demonstrate that the MLGNR transmission lines lead to lower mismatch, insertion loss, and vertical crosstalk than their MWCNT counterparts. The results show that using MLGNR improves the area overhead by more than 67% for analog and digital wires. Moreover, our model shows that the vertical noise between the analog and digital tiers is reduced by 1 and 1.62 dB when the intermediate substrate thickness increases from 20 to 30 and $40~\mu \text{m}$ . The results demonstrate that the perpendicular routing of the MLGNR interconnects reduces the vertical noise by 6.1 dB. Moreover, a 9.21-dB reduction in the vertical coupling is achieved using vertical MLGNRs in the analog IC. Our results also show that using graphene as a shield between the analog and digital chips significantly suppresses the vertical noise between the tiers, and it becomes more effective by increasing the number of graphene layers. According to our results, using one-, two-, and three-layer graphene-shield layers reduces the vertical crosstalk by 10.1, 14.9, and 19.2 dB, respectively. Moreover, the HSPICE simulations demonstrate that the MLGNR interconnects have a lower delay, power, and energy consumption than their MWCNT counterparts in the 3-D mixed-signal architecture.

Advent in VLSI technology made digital signal processing to take over analog signal processing. Analog to digital converter plays a vital role in modern digital signal processing applications. Various signal processing applications incorporated sigma delta ADC among different analog to digital converters because of its digital dominant architecture. This paper presents the design of a low pass continuous time sigma delta analog to digital converter on-chip architecture with a very few passive components connected externally to FPGA suitable for signal processing applications, wireless application, sonar and radar beamforming. Schematic level architecture of high speed comparator working at a differential swing which is not allowed by FPGA standard differential pads is designed. By applying various differential swings at the input to LVPECL, the performance and power is analyzed. High performance comparator schematic is designed as on-chip continuous-time sigma-delta analog to digital converter architecture. SPICE simulations are carried out to verify the maximum input frequency for given RC values. Xilinx provided Spartan 6 I/O pad and package SPICE models are used. Power analysis is carried out with LVPECL logic family based differential buffers along with external RC circuit. The analog and digital sections simulations along with mixed signal simulations at different stages are performed. Power and performance analysis are carried out using h-Spice and questasim simulations. schematic level architecture of a high speed comparator at a differential swing of 1.65 ± 1.5 V which is not allowed by standard differential pads is designed. Analysis illustrates that proposed on-chip continuous-time sigma-delta analog to digital converter exhibits a sampling rate of 400 MHz designed with high speed comparator with varied differential swing. Power analysis resulted with 1.86 mW for an input signal of 1 MHz. Optimal filtering is achieved with total decimation of 400, out of which the decimation of 100 is achieved by CIC filter and PFIR filter achieves remaining decimation factor of 4. Output data rate of 1 MHz with a dynamic range of 72 dB is achieved with less bill of material that suites for signal processing applications.

An analog signal processing (ASP) circuit used for CMOS image sensor (CIS) readout is presented. The proposed ASP mainly includes a two-stage programmable gain amplifier (PGA), a sample-and-hold amplifier (SHA) merged by a pipelined analog–digital converter (ADC), and a digital-analog converter (DAC). Compared with conventional readout architecture, the proposed can provide finer gain, level shifting as well as offset calibrating function. A 1.5-Mpixel 60-fps CIS with the ASP is fabricated in a 0.13 μm 1P4M CMOS mixed signal process. The experiment results indicate the sensor can normally capture images without missing code. Moreover, the measured maximum gain error of the PGA is 1.6%, and the power dissipation is 16.5 mW for single ASP.

Mixed-signal artificial neural networks (ANNs) that employ analog matrix-multiplication accelerators can achieve higher speed and improved power efficiency. Though analog computing is known to be susceptible to noise and device imperfections, various analog computing paradigms have been considered as promising solutions to address the growing computing demand in machine learning applications, thanks to the robustness of ANNs. This robustness has been explored in low-precision, fixed-point ANN models, which have proven successful on compressing ANN model size on digital computers. However, these promising results and network training algorithms cannot be easily migrated to analog accelerators. The reason is that digital computers typically carry intermediate results with higher bit width, though the inputs and weights of each ANN layers are of low bit width; while the analog intermediate results have low precision, analogous to digital signals with a reduced quantization level. Here we report a training method for mixed-signal ANN with two types of errors in its analog signals, random noise, and deterministic errors (distortions). The results showed that mixed-signal ANNs trained with our proposed method can achieve an equivalent classification accuracy with noise level up to 50% of the ideal quantization step size. We have demonstrated this training method on a mixed-signal optical convolutional neural network based on diffractive optics., Comment: Manuscript prepared for submission to IEEE Access

In this article, an overview of the most recent fully-depleted silicon on insulator technology (FD-SOI) design techniques in the field of mixed-signal circuits and systems are given. Cutting edge performance is achieved by using dynamic as well as static body-biasing techniques. 22FDX® is a 22nm CMOS FD-SOI technology providing both, a unique wide-band body-bias tuning range in conjunction with minimized parasitic device loads, due to the significant reduced pn junctions in the signal path. As a result, transistor transit frequencies exceeding 400GHz with improved linearity is achieved. With a linear threshold voltage sensitivity of around 75mV per Volt, 22FDX® gives designers a competitive additional degree of freedom. After introducing 22FDX®, a 5-bit 18.5GS/s flash ADC is presented utilizing body-biasing to generate accurate threshold voltage offsets within the comparators and thus omitting a power-hungry resistive ladder. Then, dynamic body-biasing is used for a 1.5GS/s track-and-hold circuit to improve the bandwidth while the leakage is reduced obtaining 80dBc SFDR up to the fourth Nyquist zone. Furthermore, a 26GHz ring oscillator is presented, which utilize the strong threshold voltage sensitivity to fully compensate corner dependency. Finally, a body-biasing controlled DAC linearization technique for multi-bit Sigma-Delta modulators enabling 90dBc SFDR, as well as a DAC driver termination impedance control for a 6GS/s 10-bit automotive Ethernet SST-DAC-Driver are presented.

System-on-Chip (SoC) is one of the main driving forces that have been re-shaping the consumer electronics industry. The SoC alternative to conventional systems design is growing in popularity as the device packing densi escalates due to the evolution of semiconductor technology. Moreover, the decrease in semiconductor feature size is permitting the increase of clock frequencies and component operating speed. These advancements necessitate the integration of system components due to package parasitics and lengthy interconnect. Furthermore, SoC devices offer a cheaper and more compact solution to the consumer electronics industry.An integrated mixed-signal test core approach to SoC data acquisition is a valued alternate solution to many of the problems involving conventional test. One such test core data conversion architecture incorporates a sub-sampling algorithm known as the multipass method of digitization. This method occupies a very small silicon area in exchange for an increased data conversion time. Time-interleaved test core digitizers provide the capability to reduce test time, increase sampling frequency and increase signal bandwidth. As an implicit result of this compact circuit and multipass processing methodology, significant reductions in noise and spurious tones are observed.

Advancements in the field of flexible electronics have enabled many novel applications such as wearables, flexible large-area displays, and textile-based sensor systems. A widely used semiconductor material for flexible electronics is amorphous indium gallium zinc oxide (a-IGZO). When compared to other semiconductors suitable for flexible technologies, this material is attractive for its higher mobility, better bias stability and improved uniformity. This paper presents an overview of current trends in analog and mixed signal circuit design and in architectures for a-IGZO TFT based sensor systems. We highlight the specific design challenges associated with the main sub-blocks found in sensors and bio-signal acquisition systems based on a-IGZO TFT technologies: front-end amplifiers and data converters. We then present an overview of several state-of-the-art sensor systems based on a-IGZO TFTs and their applications. Finally, conclusions are drawn, and a roadmap for the future development of analog and mixed signal circuit design in a-IGZO TFT is presented.

Modern deep neural networks (DNNs) require billions of multiply-accumulate operations per inference. Given that these computations demand relatively low precision, it is feasible to consider analog computing, which can be more efficient than digital in the low-SNR regime. This overview article investigates the potential of mixed analog/digital computing approaches in the context of modern DNN processor architectures, which are typically limited by memory access. We discuss how memory-like and in-memory compute fabrics may help alleviate this bottleneck and derive asymptotic efficiency limits at the processing array level. It is shown that single-digit fJ/op energy efficiencies are feasible for 4-bit mixed-signal arithmetic. In this analysis, special consideration is given to the SNR and amortization requirements of the analog–digital interfaces. In addition, we consider the pros and cons for a variety of implementation styles and highlight the challenge of retaining high compute efficiency for a complete DNN accelerator design.

An 8-bit switched-capacitor multiply-and-accumulator (MAC) in 65nm CMOS is presented. Based on a cascaded low-power ring-amplifier-based switched-capacitor DACs, the MAC circuit features a programmable accumulation length in MAC computation. Fabricated in 65nm CMOS, the prototype MAC circuit achieves a precision-scaled energy efficiency of 1.32fJ per MAC operation, which is comparable to other state-of-the-art MAC circuits, along with best-in-class linearity. The noise performance has been verified using four real-world convolutional neural networks (CNNs) and 10,000-image data sets with up to 1,000 classes with an accuracy drop of less than 2% compared to the baseline 32-bit floating-point MAC.

Direction of arrival (DOA) estimation is an important topic in array signal processing. Currently, most research activities are focused on the single signal transmission (SST) type of signals, i.e. only one physical signal is used to carry the information from a transmitter to a receiver with a given polarisation setting. However, to make full use of the degrees of freedom in spatial domain, signals based on the dual signal transmission (DST) model are more and more widely used, i.e., two signals with different polarisations carrying different information are employed for communication between the transmitter and the receiver. But there is rarely any work on DOA estimation of DST signals. Motivated by such a problem, the paper proposes two methods for DOA estimation of signals based on a mixed signal transmission (MST) model, i.e., a mixture of SST and DST signals. The first method provides a two-step solution and estimate the DOA of the SST signals first and then the DST signals second. The second method estimates the DOA of all signals in one step. Moreover, CRB (Cramér-Rao Bound) for the estimation model is derived to evaluate the performance the proposed methods.

Today’s mixed-signal SoCs are challenging to validate. Running enough test vectors often requires the use of event-driven simulation and hardware emulation, which in turn necessitates the creation of analog behavioral models. This paper reviews different approaches proposed to address that modeling challenge, and shows how they can be divided by the methods used to solve for analog circuit values, represent analog waveforms, and validate analog functional models. We illustrate the power of these techniques as applied to a 16 Gb/s PHY, demonstrating a 10, $000\times $ speedup vs. SPICE simulation using event-driven models in Verilog simulation, and a further 5, $000\times $ speedup using synthesizable analog models in FPGA emulation.

Technology-assisted People-to-People (P2P) interactions, embedded in a global environment, will be at the core of 21st century communications and will command the technological development of the forthcoming future. The intelligent interactivity of people, process (delivering the right information to the right person/machine at the right time), data and things, incorporates the Internet-of-Everything (IoE) that expands itself beyond the Internet-of-Things (IoT). In general, IoT comprises all physical or cyber objects (things) with an address that can transmit data (without human-to-machine interactions), while the IoE also involves communications among the users and the whole universe of electronic gadgets. Further, they both operate with data acquired from analog sources, thus connecting two different realities, the analog (physical/real) and the digital (cyber/virtual) worlds. Since the interface between the two realms deals with analog signals, its mandatory functions integrate several analog and mixed-signal sub-systems that include signal sensing, transmission and reception, frequency generation, energy harvesting, in-memory processing, data and power conversion. This publication presents state-of-the-art designs of the most critical building blocks of the analog/digital interface highlighting new and innovative circuit architectures and techniques. It addresses capacitive sensor interfaces, ultra-low-power wireless transceivers, key technologies for wireline transceivers, oscillators and frequency generators, integrated energy harvesting interfaces, in-memory processing, as well as, data and power converters, all exhibiting high quality performance with low power consumption, high energy-efficiency and high speed, thus enabling a reliable and consistent development of the IoE while enlarging its frontiers. In the coming decades, with the continuous evolution of electronics downscaling, the challenges that the above-mentioned sub-systems face will be tremendous in terms of the requirements for ultra-low power and ultra-high speed, obtained with the maximum energy-efficiency. Thus, the analog and mixed-signal very large scale integration area of work will continue to be an attractive field for research for design engineers both in the academia and in the industry, as it has been always the case since the emergence of silicon planar electronics 6 decades ago.

This paper presents an approach for runtime software-based fault injection, applied to a commercial mixed-signal programmable system-on-chip (PSoC). The fault-injection scheme is based on a pseudo-random sequence generator and software interruption. A fault tolerant data acquisition system, based on a design diversity redundant scheme, is considered as case study. The fault injection is performed by intensively inserting bit flips in the peripherals control registers of the mixed-signal PSoC blocks, as well as in the SRAM memory of the device. Results allow to evaluate the applied fault tolerance technique, indicating that the system is able to tolerate most of the generated errors. Additionally, a high fault masking effect is observed, and different criticality levels are observed for faults injected into the SRAM memory and in the peripherals control registers.

This paper demonstrates a compact mixed-signal (MS) convolutional neural network (CNN) design procedure by proposing a MS modular neuron unit that alleviates analog circuit related design issues such as noise. Through the first step of the proposed procedure, we design a CNN in software with a minimized number of channels for each layer while satisfying the network performance to the target, which creates low representational and computational cost. Then, the network is reconstructed and retrained with a single modular neuron that is recursively utilized for the entire network for the maximum hardware efficiency with a fixed number of parameters that consider signal attenuation. For the last step of the proposed procedure, the parameters of the networks are quantized to an implementable level of MS neurons. We designed the networks for MNIST and Cifar-10 and achieved compact CNNs with a single MS neuron with 97% accuracy for MNIST and 85% accuracy for Cifar-10 whose representational cost and computational cost are reduced to least two times smaller than prior works. The estimated energy per classification of the hardware network for Cifar-10 with a single MS neuron, designed with optimum noise and matching requirements, is $0.5\mu $ J, which is five times smaller than its digital counterpart.

Traditional literature on analog testing deals with the propagation of faults to the output ports of a circuit. Often the percentage of detected faults remains low because suitable stimuli cannot be found for propagating certain faults to the outputs. Existing technology supports monitoring internal nets of a circuit, thereby improving fault detection by observing their effect on internal nets. However, this approach is feasible only if the number of internal nets probed by the built-in test structure is limited. This paper presents a structured approach that identifies a small well-chosen subset of internal nets which, when probed, can increase the coverage of analog faults. Further, it describes a formal methodology to identify distinct sub-circuits in a given design, that could be independently probed for detection of faults. Thus, for a given fault universe, the complexity of simulations can be reduced significantly by simulating only the sub-circuits rather than the entire design. We utilize the speed of DC analysis, some common features of analog signals, and partitioning of the transistor netlist using a Channel Connected Graph to accomplish this outcome. We report significant improvement in fault coverage on several circuits including some Analog/Mixed-Signal benchmarks.

The rapid increase of wearable sensor devices poses new challenges for implementing continuous real-time processing of physiological data. Neuromorphic sensory-processing devices can enable both the measurement of bio-signals and their processing locally in compact embedded wearable systems. In particular, mixed-signal spiking neural networks implemented on neuromorphic processors can be integrated directly with the sensors to extract temporal data-streams in real-time with very low power consumption. In this work, we present a neuromorphic approach for classifying spatio-temporal data from electromyography (EMG) signals, which paves the way toward the realization of compact wearable solutions for neuroprosthetic control. Here we extend previously proposed delta-encoding methods to transform bio-signals into spike trains and use a spiking Recurrent Neural Network (SRNN) architecture to extract features from them. The SRNN was first simulated in software to find the optimal set of hyperparameters, and then validated on the neuromorphic hardware, with a difference in the performance of less than 2%. We describe how biologically plausible mechanisms such as Spike-Timing Dependent Plasticity (STDP) and soft Winner-Take-All (WTA) networks can be exploited to classify the EMG signals and show how their combined use in EMG data classification achieves competitive results with different datasets. Specifically, the classification performance for the Roshambo EMG dataset, which has three different classes, is above 85%, and for the basic finger movements dataset from the Ninapro database, which has eight different classes, reaches 55% accuracy.

Advanced power amplifier (PA) architectures are critical for 5G communication which requires PAs to have sufficient output power, high linearity, and high energy efficiency. The time-variant operational environment further demands the self-reconfigurability in the PA design. Recent developments in bandit-problems and reinforcement learning (RL) have led to data-driven control algorithms. This paper presents various RL-based algorithms for Doherty PA control, which achieve robust adaptive operation over environmental changes. Multiple RL frameworks are incorporated in the control algorithms including multi-armed bandit (MAB), continuum-armed bandit (CAB), contextual-bandit (CB), and actor-critic with experience replay (AC). The control algorithms based on the latter three frameworks leverage on the prior information about the Doherty PA’s characteristics to improve learning efficiency. In our simulation test where the optimal policy needs to be adjusted due to transmitter output load impedance mismatch, the MAB-based control learns the optimal policy within 25,000 samples. The control algorithms based on CAB and CB learn the optimal policy within 5,000 samples. The fastest learning rate is achieved by the control algorithm based on AC, which learns the optimal policy within 1,500 samples.

A digitally programmable analog Fuzzy Logic Controller (FLC) is presented. Input and output signals are processed in the analog domain whereas the parameters of the controller are stored in a built-in digital memory. Some new functional blocks have been designed whereas others were improved towards the optimization of the power consumption, the speed and the modularity while keeping a reasonable accuracy, as it is needed in several analogue signal processing applications. A nine-rules, two-inputs and one-output prototype was fabricated and successfully tested using a standard CMOS 2.4μ technology, showing good agreement with the expected performances, namely: a 2.7% RMSE, from 2.22 to 5.26 Mflips (Mega fuzzy logic inferences per second) at the pin terminals (@CL=13pF), 933 μW power consumption per rule (@Vdd=5V) and 5 bits of resolution. Since the circuit is intended for a subsystem embedded in an application chip (@CL≤ 5pF) up to 8 Mflips may be expected.

We present a novel mixed-signal single-output outphasing RF Pulse Width Modulator (RF PWM) realized in 40nm CMOS. Two Digital-to-Time Converters (DTCs) synchronously phase shift an external LO according to two 9-bit outphasing input words. Coarse time quantization is provided by tapping the internal nodes of passive integrated LC delay lines. Finer resolution is added using switching capacitors of a Gm-C circuit attaining minimum time steps of 6ps/750fs respectively. “Hair-pin” inductors with minimized footprint have been employed for the silicon realization of each LC delay line. Measurement yields an ACLR of approx. −42 dBc from a 32 MHz BW multi-tone signal on a 2.65 GHz carrier.

The study discusses selected issues of modelling and designing current-mode devices. The authors propose the design flow that covers abstract behavioural models, the schematic and SPICE-level netlists and the post-layout parasitic parameters. The considerations related to the analogue functional blocks with a dual-stage complexity. The theoretical backgrounds of the current-mode basic building blocks are introduced. Special attention has been paid to a new current-mode active component, digitally programmable modified current differencing transconductance amplifier (MCDTA). Based on the idea of an MCDTA, the authors have developed their own cell, which integrates the digital control feature (programmability) into current-mode analogue devices. This original solution enables the dual control techniques, coarse digital control and precise analogue control to be used. The presented examples of continuous-time active filters show that such a solution enables flexibility in the digital control of the parameters of analogue blocks. In order to facilitate the integration of the analogue and mixed-signal models in a single environment, VHSIC Hardware Description Language - Analogue Mixed Signal (VHDL-AMS) language was selected for the behavioural modelling methodology. The authors have used the back annotating mechanism to update behavioural models based on an estimation of the post-layout parameters. The approach is presented on examples that were implemented in TMSC 40 nm complementary metal–oxide–semiconductor technology.

This article discusses a new approach to size an analog-to-digital converter (ADC) for the simultaneous acquisition of two signals. It allows evaluating the resolution, which fulfills a certain dynamic range (DR) in the case of multiple signals with different powers. Experimental results with software-defined radios (SDRs) confirm our simulations. It shows that we are able to acquire an intra-quantum signal due to the contribution of a stronger transmission, which makes it cross the quantization levels. Some insights about another way to exceed the theoretical DR with the inherent noise in electrical systems are also provided. Thus, we propose to give the ADC required resolution to detect an intra-quantum signal when simultaneously received with a stronger one which, to the best of our knowledge, has never been thoroughly studied.

A mixed-signal adaptive ripple canceller for reducing switching noise and spurious emissions in switching regulators is presented. The proposed mixed-signal ripple suppression technique tracks and cancels the switching noise by utilizing two schemes: A primary mixed-signal adaptive ripple canceller that provides large signal ripple cancellation up to 20 dB, and an auxiliary linear amplifier-based ripple canceller that minimizes the residual ripple content, achieving a combined ripple rejection of 24 dB. Proposed approach operates without the need for external components, reducing overall printed circuit board area without loss of efficiency. The adaptive ripple canceller is designed and fabricated in a 250 nm CMOS process with four levels of metal. The ripple-canceller is integrated with an on-chip buck regulator to characterize its rejection effectiveness. The ripple canceller can also be utilized as a stand-alone ripple cleaner module with an external commercial-off-the-shelf (COTS) switching regulator. The proposed ripple canceller can track and cancel power supply ripple up to 1 MHz with 24 dB rejection and reduces ripple content up to fourth harmonic by at least 20 dB while supporting dc loads up to 1 A and ripple currents up to 350 mApk-pk. The proposed approach achieves 30% lower quiescent current than using a linear low-dropout regulator without the need for any external components.

This paper concerns the issue of unbalanced output power among cells in cascaded H-bridge multilevel (CHBM) converters with conventional staircase modulation techniques under low modulation signals. This is a common condition in high-voltage/frequency hybrid power amplifiers (HPAs) consisting of a CHBM converter in series with a linear power amplifier (LPA). The online implementation of a modulation technique called split-voltage first-in first-out (SV-FIFO) that mitigates this issue is presented in this study. Differently from conventional techniques, it needs to take into consideration the magnitude and frequency of the reference voltage to generate the gating signals of the CHBM converter. This paper also introduces a design procedure for a series-type HPA and a means for generating online the gating signals of the CHBM converter, with SV-FIFO, and the reference signal for the LPA in closed loop with a mixed signal controller. Experimental results for a series-type HPA with a six-cell CHBM converter and a commercial LPA are provided to validate the design procedure of the HPA and demonstrate the enhanced (active) power balance of SV-FIFO and the effectiveness of the proposed control scheme for the HPA under transient and steady-state conditions.

Pervasive computing requires to build systems every day more complex and heterogeneous. Smart devices must be able to carry on sensing and actuation alongside with computation and communication. As such, many different technologies must be packed within the same object. Digital HW and SW coexist with analog components and Micro-Electro-Mechanical systems capable of sensing and controlling the physical environment. For this reason, the design of such devices must rely on the integration of many different descriptions belonging to different design domains. The high-level of heterogeneity involved in the modeling phase of the system development makes harder the validation of the system functionality, since holistic system simulation would require the integration of many different simulators. In this article, we propose a set of automatic abstraction techniques for multi-disciplines analog components. Then, we define a scheduling strategy to integrate the execution of continuous-time analog sub-components with automatically abstracted models of the digital HW parts of the system. As a final result, the proposed methodology produces a C++ virtual platform providing a holistic simulation of complex and heterogeneous devices.

This paper applies new analytical techniques to evaluate the stability and mean-square error (MSE) convergence of a multi-loop LMS pseudo-random noise canceller which applies to a variety of known mixed-signal circuit calibration techniques. To the authors’ knowledge, it is the first published MSE analysis of any multi-loop LMS system, and, unlike most published MSE analyses of single-loop LMS systems, it does not make any simplifying assumptions. The analysis proves that the noise canceler can be made unconditionally stable by design, and provides guidance on how to choose design parameters to achieve a desired level of noise cancellation.