Mixed-Signal Design and Verification Flow of an Integrated Circuit

In this thesis, work is focused on the Mixed-Signal Design and Verification Flow of an Integrated Circuit A comprehensive literature review of the state-of-the-art design and verification methodologies as well as a quick review of functional safety for automotive IC was carried out. The Mixed-Signal Project Environment at Monolithic Power Systems (MPS) where the analog and digital databases are integrated has been explained and a review of the Mixed-Signal design and verification flow (Architecture Mapping, Verification plan, Modelling Plan, Validation Plan) has been carried out. An I2C Master Verification IP (VIP), which follows and includes the minimum required set of features, was developed to ease the burden on the Analog and Mixed-Signal Designers efforts to run top level simulations involving I2C communication and to standardise it across the company. Behavioural models of simulation intense analog blocks were developed and validated to allow for significant increase on mixed-signal simulation performance. Finally, the functional requirements of an MPS DC-DC Mixed-Signal Automotive IC were explained, and a top-level mixed-signal verification plan was developed based on those requirements. Then simulation of some of the test defined in the verification plan was carried out with the help of the previously developed I2C Master VIP and behavioural models.