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Compressive sensing (CS) is a promising technique for transmitting signals in power-critical applications such as Internet of Things (IoT) devices. Nonuniform CS optimizes this process by adjusting sampling frequency based on the relative importance levels characterized by the signal of interest. Recent advances have yielded energy-efficient hardware implementations of CS sampling, leveraging spin-based crossbar architectures for in-memory vector-matrix multiplication and through the use of probabilistic bit (p-bit) devices to generate tunable random outputs for writing the array. Thus, a region of interest is generated via column-ordered density of on-state devices. Herein, we propose a simple design for supplying inputs to the p-bit devices, based on Ohmic voltage attenuation occurring along the word lines of the crossbar array. The technique embeds some required computations to be conducted intrinsically by the cross-points of the memristive array, thus bypassing overheads of conventional instruction execution and eliminating the need for costly hardware components, such as lookup tables (LUTs) and data converters. The design is shown to be robust for various array sizes and parasitics while generating the appropriate tuning signals within a single clock cycle duration of 1.6 ns, and at an energy overhead of 333 fJ. Compared with a standard approach using LUTs and digital to-analog converters, the design herein achieves a 583-fold reduction in energy and 23-fold reduction in transistor count. [ABSTRACT FROM AUTHOR]

The VMM3a is a custom low-noise application-specific integrated circuit. It is intended to be used in the front-end readout electronics of both the Micromegas and sTGC detectors of the ATLAS New Small Wheels upgrade project at CERN. It is fabricated in the 130-nm GlobalFoundries 8RF-DM process. The 64 channels with highly configurable parameters, although designed for a specific project, can meet the processing needs of signals from various detector types in several other applications. In this note, the VMM3a, which is the production version of the VMM family, will be presented along with the features incorporated and its performance. [ABSTRACT FROM AUTHOR]

A low-complexity stochastic dynamic element matching (DEM) technique to mitigate the distortions caused by the nonlinearity of multi-bit digital-to-analog converters (DACs) in sigma-delta modulator is proposed. Multi-bit DAC noise is analyzed in detail from a signal processing point-of-view in this research, and then implementation of the basic stochastic unit named swapper cell which includes bar state and cross state controlled by a 1-bit pseudo-random noise signal, is illustrated. To reduce the hardware complexity, a multi-layer scheme for multi-input multi-output stochastic encoder is presented and demonstrated based on rigorous mathematical derivation. For a n-input n-output version, the number of the switch elements employed in the proposed encoder is reduced to 2nlog2n from the conventional n!. Simulation results show that, with the use of the stochastic encoder, severe harmonic distortions resulted by the DAC elements mismatch errors are suppressed effectively. When the proposed encoders are applied to the internal multi-bit DACs in sigma-delta (ΣΔ) modulators, large improvements of the linearity performance of the modulators are achieved. Additionally, the analyses and explanations for this stochastic scheme provide a theoretical foundation for the future development of noise shaping DEM. [ABSTRACT FROM AUTHOR]

Mixed-signal components, such as low dropouts (LDOs) and phase locked loops (PLLs), are widely used inside the on-chip power management fabric of low power integrated system-on-chip (SoC) designs. The digital brain of the power management logic that is responsible for regulating the power delivery to different power domains in the chip has to consider the real time latencies of the analog components, which otherwise leads to functional errors in the domains being driven. The latencies may be viewed as contracts between the digital and the analog. This article presents an approach for generating assertions for protecting such mixed-signal latency contracts and using them to rule out timing bugs in the power management logic. Our tool flow enables the verification of the power management fabric, combining a novel mixed-signal assertion checking method in a simulation setting, and a full formal verification method for the digital brain of the power management logic. To the best of our knowledge, this is the first framework where assertions are used for binding analog latency contracts on the digital logic of power management. [ABSTRACT FROM AUTHOR]

We describe a capacitance sensor array that has been incorporated into a lab-on-CMOS system for applications in monitoring cell viability. This paper presents analytical models, calibration results, and measured experimental results of the biosensor. The sensor has been characterized and exhibits a sensitivity of 590 kHz/fF. We report results from benchtop tests and in vitro experiments demonstrating on-chip tracking of cell adhesion as well as monitoring of cell viability. Human ovarian cancer cells were cultured on chip, and measured capacitance responses were validated by comparison with images from photomicrographs of the chip surface. Analysis was performed to quantify cell proliferation and adhesion, and responses to live cells were estimated to be 100 aF/cell. [ABSTRACT FROM AUTHOR]

This paper presents a switching scheme-based placement method to reduce the effect of various sources of nonlinearity arising due to layout routing parasitic in a current-steering digital-to-analog converter (DAC), thereby providing excellent static and dynamic performance. The proposed technique reduces both the individual and the cumulative effect of different nonidealities. Improvement in both the static and the dynamic performance is observed when compared with that provided by conventional common centroid placement. A 10-bit 500-MHz differential current-steering DAC has been designed and evaluated in 65-nm CMOS process as a case study, which provides a $\sim 72$ -dB spurious-free dynamic range at a 122-Ms/s input frequency. [ABSTRACT FROM PUBLISHER]

Digital fractional-N phase-locked loops (PLLs) are an attractive alternative to analog PLLs in the design of frequency synthesizers for wireless applications. However, the main obstacle to their full acceptance in the wireless-systems arena is their higher content of output spurious tones, whose level is ultimately set by the nonlinearity of the time-to-digital converter (TDC). The known methods to improve the linearity of the TDC either increase its dissipation and phase noise or require slow foreground calibrations. By contrast, the class of digital PLLs based on a one-bit TDC driven by a multibit digital-to-time converter (DTC) substantially reduces power dissipation and eliminates the TDC nonlinearity issues. Although its spur performance depends on DTC linearity, the modified architecture enables the application of a background adaptive pre-distortion which does not compromise the PLL phase-noise level and power consumption and is much faster than other calibration techniques. This paper presents a 3.6-GHz digital PLL in 65-nm CMOS, with in-band fractional spurs dropping from -39 to -52 dBc when the pre-distortion is enabled, in-band phase noise of -103 dBc/Hz and power consumption of 4.2 mW. [ABSTRACT FROM AUTHOR]

An integrated converter controller with maximum power point (MPP) regulation in 0.35 μm CMOS for photovoltaic (PV) applications is reported. The implemented MPP tracker bases on a perturb and observe algorithm and acquires the information concerning the power flow via an analog processing circuit which is connected at the switched mode converter input respectively the output of the attached PV string of nine cells. There the solar cell current is measured via a very low-ohmic shunt resistor of 1 mΩ and analogously multiplied with the cell voltage. As output the fabricated test chip directly generates a 530 kHz PWM signal for the external switched mode converter. Measurements show that under similar conditions analog MPP tracking of the converter input power improves the robustness with respect to settling times of the power path compared to those topologies at which the power is measured at the converter output. Between 0.4 and 7.5 A photocurrent the chip achieves tracking efficiencies better than 99.5 % while the power consumption is only 750 μW and a very low chip area demand of 0.043 mm for the MPP tracking core is achieved. [ABSTRACT FROM AUTHOR]

In this paper, we describe the design of Neurogrid, a neuromorphic system for simulating large-scale neural models in real time. Neuromorphic systems realize the function of biological neural systems by emulating their structure. Designers of such systems face three major design choices: 1) whether to emulate the four neural elements—axonal arbor, synapse, dendritic tree, and soma—with dedicated or shared electronic circuits; 2) whether to implement these electronic circuits in an analog or digital manner; and 3) whether to interconnect arrays of these silicon neurons with a mesh or a tree network. The choices we made were: 1) we emulated all neural elements except the soma with shared electronic circuits; this choice maximized the number of synaptic connections; 2) we realized all electronic circuits except those for axonal arbors in an analog manner; this choice maximized energy efficiency; and 3) we interconnected neural arrays in a tree network; this choice maximized throughput. These three choices made it possible to simulate a million neurons with billions of synaptic connections in real time—for the first time—using 16 Neurocores integrated on a board that consumes three watts. [ABSTRACT FROM PUBLISHER]

In this paper, a model of power supply noise (PSN) effects on an analog-to-digital converter (ADC) in a hierarchical structure is proposed. The ADC performance is determined by not only on-chip characteristics but also off-chip characteristics. Therefore, chip-package-printed circuit board (PCB) coanalysis and comodeling are required to accurately evaluate the performance of the ADC. We propose the comodel which allows the estimation and analysis of PSN effects on the ADC including off-chip characteristic. The proposed model includes three separate submodels: a power distribution network (PDN) model from the power/ground of the PSN source to the ADC power/ground, an on-chip circuit model from the ADC power/ground to the ADC inputs, and an ADC behavioral model from the ADC inputs to the factor of the effective number of bits (ENOB), which is one of the ADC performance factors. By applying a segmentation method for the PDN model, an analytical model for the on-chip circuit model, and a MATLAB model for the ADC behavioral model, fast, precise, and broadband estimations of the PSN effects are achieved. To validate the proposed models, an ADC was fabricated by a 0.13-μm CMOS process and wire bonded to the designed PCB. The ENOB of the ADC was measured by sweeping the PSN's frequency from 1 MHz up to 3 GHz, which was injected into the PCB to discover which noise frequency is critical to an ADC designed with a chip-PCB hierarchical structure. The results estimated by the proposed model correlated well with the cosimulated and measured results. The proposed modeling procedure saves the chip, package, and PCB designers time and computation resources to achieve high-quality analog devices or mixed-mode systems and provides an intuitive understanding of the noise effect. [ABSTRACT FROM PUBLISHER]

An integrated CMOS controller with fast maximum power point regulation for module-integrated automotive solar converters with nine solar cells per string is reported. It provides the 530-kHz switching signals for the module-integrated converter whereby the mean output current of the module is maximized. The on-chip “perturb and observe” algorithm bases on a quasi-analog principle and performs more than 1000 tracking cycles/s at a power consumption around 560 μW. In order to maximize the precision, the duration of the measurement intervals is automatically adjusted to the output current. Due to the use of a very small shunt resistance of 1 mΩ for the current measurement, the insertion loss is small and the circuit complexity is kept low. Between 0.25- and 5-A photocurrent, the tracker achieves a tracking efficiency better than 99.5%. [ABSTRACT FROM AUTHOR]

A low-power switched-capacitor third-order sigma- delta (\Sigma \Delta) modulator suitable for portable sensor systems is described. The architecture uses only one operational amplifier working in a time-interleaved fashion. The architecture employs swing reduction techniques to limit the swing and the slew-rate requirements of all internal nodes. Realized in a 0.18-\mum 2P6M CMOS technology, the modulator provides 84-dB SNDR and 88-dB dynamic range in a signal bandwidth of 100 kHz and clock at 3.2 MHz. The 1.5-V supplied prototype dissipates 140 \muW with a FoM of 54 fJ/conversion-level. [ABSTRACT FROM AUTHOR]

In this work, we have demonstrated a fully-integrated, high-efficiency CMOS inverse Class-D PA. Such efficient switching amplifiers can form the core of mixed-signal polar transmitters. A comprehensive analytical framework has been developed to determine optimum component values to maximize efficiency. Operating from a 1-V supply, the PA achieves a peak efficiency of 44% without any RF process options. This is comparable to that of state-of-the-art CMOS switching PAs despite using a much simpler output matching network. [ABSTRACT FROM PUBLISHER]

A 65-nm digitally modulated polar transmitter incorporates a fully integrated, efficient 2.4-GHz switching Inverse Class-D power amplifier. Low-power digital filtering on the amplitude path helps remove spectral images for coexistence. The transmitter integrates the complete LO distribution network and digital drivers. Operating from a 1-V supply, the PA has 21.8-dBm peak output power with 44% efficiency. Simple static predistortion helps the transmitter meet EVM and mask requirements of 802.11g 54-Mb/s WLAN data with 18% average efficiency. [ABSTRACT FROM AUTHOR]

A discrete-time (DT) fast Fourier transform (FFT) processor is presented as an architectural approach to Fourier transform processing multigigahertz of spectral bandwidth. The processor is considered with the specific application of demodulating orthogonal frequency-division multiplexing (OFDM) modulation. The processor enables increased receiver linearity beyond that which is typically limited by the signal-to-noise-and-distortion ratio of high sample rate ADCs by performing OFDM demodulation in the DT domain. The circuit design of the prototype DT-FFT processor is presented and measurement results from the CMOS 0.13-\mu\ m test chip are shown. Results show that the processor demodulates OFDM at 1 GS/s with an accuracy better than 2.8% error vector magnitude while drawing 25 mW from a 1.2-V power supply. The processor demonstrates a measured dynamic range of 49 dB, a 13-dB improvement over that of a 6-bit quantization limited all-digital FFT processor and ADC pair. The DT-FFT is also shown to better tolerate large blocking signals with an 8-dB dynamic range improvement. The DT-FFT core area is \ 450\ \mu\ m\times \ 450\ \mu\ m. [ABSTRACT FROM AUTHOR]

This work introduces application of the Kalman Filter in linearity test of Analog-to-Digital Converters (ADCs). The Kalman Filter can be used to suppress errors in the histogram counts, based on characteristics of the test environment and the device under test, and achieve high accuracy within short test time. In this paper, appropriate system and noise models, and a corresponding form of the Kalman Filter are developed, while all necessary parameters are obtained from experimental measurements. Simulation and experiment results show that the INL test errors are reduced by more than 50% by applying the proposed method. Consequently, this method can achieve desired accuracy with significantly fewer samples as compared to the conventional algorithm, and shorten the linearity test time by a factor of four or higher. This method is valuable for effectively reducing the production test time and cost for ADCs. [ABSTRACT FROM AUTHOR]

Analog & digital circuits implemented in a dual threshold voltage (VT) p-channel organic technology are presented. The dual VT organic technology is compatible with large-area and mechanically flexible substrates due to its low processing temperature (\leq \95\ ^\circ\C) and scalable patterning techniques. We demonstrate the first analog & digital organic integrated circuits produced by a dual-gate metal process. The analog circuits are powered by a 5-V supply and include a differential amplifier and a two-stage uncompensated operational amplifier (op-amp). A dynamic comparator is measured to have an input offset voltage of 200 mV and latching time of 119 ms. Both the comparator and the op-amp dissipate 5 nW or less. Area-minimized digital logic is presented. Inverters powered by a 3-V supply were measured to have positive noise margins and consumed picowatts of power. An 11-stage ring oscillator, also powered by a 3-V supply, swings near rail to rail at 1.7 Hz. These results demonstrate dual threshold voltage process feasibility for large-area flexible mixed-signal organic integrated circuits. [ABSTRACT FROM PUBLISHER]

Abstract: The problem of computing the capacitance coupling in Very Large Scale Integrated (VLSI) circuits is studied in this work. The proposed method is an approximate extended version of the method of images. The initial problem is formulated here as an optimization problem for the solution of which a genetic algorithm (GA) is employed. The proposed method is fast, general, does not rely on fitting techniques and is applicable to an arbitrary 2D or 3D geometry configuration of conductors. Extensive simulation results are presented for several practical case studies. Comparative results are given with other methods from literature and a commercial tool employing the Finite Element Method (FEM). The results show that the capacitance value computed by our method is in close agreement to the value obtained by the other methods from literature and also by the commercial tool with the average difference ranging between 2% and 5% while demonstrating better scalability as the problem complexity rises. [Copyright &y& Elsevier]

This paper demonstrates the first fully integrated built-in self-test (BIST) ∑-Δ analog-to-digital converter (ADC) chip to the best of our knowledge. The ADC under test (AUT) comprises a second-order design-for-digital-testability ∑-Δ modulator and a decimation filter. The purely digital BIST circuitry conducts single-tone tests for the signal-to-noise-and-distortion ratio (SNDR), the dynamic range, the offset, and the gain error of the AUT. The BIST design is based on the proposed modified controlled sine-wave fitting procedure to address the component overload issues, reduce the setup parameter numbers, and eliminate the need for parallel multipliers. The total gate count of the whole BIST circuitry is only 13 300. The hardware overhead is much less than the BIST design using the traditional fast Fourier transform (FFT) analysis. Measurement results show that the peak SNDR results of the proposed BIST design and the conventional FFT analysis are 75.5 and 75.3 dB, respectively. The subtle SNDR difference is already within analog test uncertainty. The BIST ∑-Δ ADC achieves a digital test bandwidth higher than 17 kHz, very close to the rated 20-kHz bandwidth of the AUT. [ABSTRACT FROM AUTHOR]

A time-of-flight depth sensor is presented employing a correlation based concept. The pixels are able to suppress contributions of ambient light up to 150 klx autonomously and directly in the electronic circuits consuming only 2 µA, each. All 16 x 16 pixels capture the depth information simultaneously at maximally 16 frames per second using an external A/D converter (ADC). Additionally, an embedded 12-bit ADC can be used for converting the analog output values of the pixels to the digital domain at lower frame rates. Distance measurements in a range of 0-3.2 m show standard deviations in the centimeter range and a linearity error within -1/+2 cm. The influence of extraneous light is expressed as a relative distance error which is also in the centimeter range. A complete impression of the sensor system is given by discussing the pixel circuits, the ADC design, the design of the modulated light source providing 0.9W optical power in the near infrared, and the auxiliary setup including an FPGA board. Additionally, a sensor model is provided to predict the measurement error due to stochastic sources. Three-dimensional snapshots as well as a comparison with state-of-the-art sensors and products complete the paper. [ABSTRACT FROM AUTHOR]

Abstract: This paper describes the design and experimental characterization of a 0.13μm CMOS switched-capacitor reconfigurable cascade ΣΔ modulator intended for multi-standard GSM/Bluetooth/UMTS hand-held devices. Both architectural- and circuital-level reconfiguration strategies are incorporated in the chip in order to adapt the effective resolution and the output rate to different standard specifications with optimized power dissipation. This is achieved by properly combining different reconfiguration modes that include the variation in the order of the loop filter (3rd- or 4th-order), the clock frequency (40 or 80MHz), the internal quantization (1 or 2bits), and the bias currents of the amplifiers. The selection of the modulator topology and the design of its building blocks are based on a top-down CAD methodology that combines simulation and statistical optimization at different levels of the modulator hierarchy. Experimental measurements show a correct operation of the prototype for the three standards, featuring dynamic ranges of 83.8/75.9/58.7dB and peak signal-to-(noise+distortion) ratios of 78.7/71.3/53.7dB at 400ksps/2/8Msps, respectively. The modulator power consumption is 23.9/24.5/44.5mW, of which 9.7/10/24.8mW are dissipated in the analog circuitry. The multi-mode ΣΔ prototype shows an overall performance that is competitive with the current state of the art. 1 [1] This work has been supported by the Spanish Ministry of Science and Education (with support from the European Regional Development Fund) under contract TEC2007-67247-C02-01/MIC and the Andalusian (Regional) Council of Innovation, Science and Enterprise under contract TIC-2532. [Copyright &y& Elsevier]

Predicting substrate cross-talks in mixed-signal circuits has become a critical issue to preserve signal integrity in future integrated systems. Phenomena that involve substrate parasitic voltage and substrate propagation are discussed. A simple methodology to predict the substrate cross-talk and some associated tools are presented. A typical study shows the possibility of such a method and measurements finally demonstrate its efficiency. [ABSTRACT FROM AUTHOR]

The "split analog-to-digital converter (ADC)" architecture enables fully digital calibration and correction of offset, gain, and aperture-delay mismatch errors in time-interleaved ADCs. The calibration of M interleaved ADCs requires 2M + 1 half-sized ADCs, a minimal increase in analog complexity. Each conversion is performed by. a pair of half-sized ADCs, generating two independent outputs that are digitally corrected using estimates of offset, gain, and aperture-delay errors. The ADC outputs are averaged to produce the ADC output code. The difference of the outputs is used in a calibration algorithm that estimates the error in the correction parameters. Any nonzero difference drives a least-mean-square feedback ioop toward zero difference, which can only occur when the average error in each correction parameter is zero. A simulation of a 4: 1-time-interleaved 16-bit 12-MSps successive-approximation-register ADC shows calibration convergence within 400 000 samples. [ABSTRACT FROM AUTHOR]

In this paper, a low power 6-bit ADC that uses reference voltage and common-mode calibration is presented. A method for adjusting the differential and common-mode reference voltages used by the ADC to improve its linearity is described. Power dissipation is reduced by using small device sizes in the ADC and relying on calibration to cancel the large non-ideal offsets due to device mismatches. The ADC occupies 0.13 mm[sup2] in 65 nm CMOS and dissipates 12mW at a sample rate of 800 MS/s from a 1.2 V supply. [ABSTRACT FROM AUTHOR]

We present a mixed-signal CMOS front-end cell designed for semiconductor pixel detectors for X-γ ray imaging and spectroscopy. The Readout Pixel Cell (RPC) comprises an analog and a digital section to accomplish all the functionality of a spectroscopic-grade signal readout. The analog section includes a low noise charge preamplifier, a two stage shaper amplifier with digitally selectable shaping times from 1 μs to 10 μs, a baseline restorer, a high precision peak stretcher and an output amplifier. The digital section includes an amplitude discriminator with coarse and fine digital control of the threshold level, a peak discriminator, a current-mode trigger generator, a logic circuit to accomplish the pulse pile-up rejection and the RPC reset after the A/D conversion, the disable functions of the preamplifier and of the discriminators. The RPC has been designed and manufactured in 0.35 μm CMOS technology with a size of 300 μm × 300 μm. The full functionality of the RPC has been successfully tested. At room temperature, the intrinsic equivalent noise charge is 15.7 electrons r.m.s. at 3.3 jis and the minimum noise slope is 22 electrons/pF at 8 μs, the linearity error is between -1.4% and + 1.2% within 1.9 fC input signal dynamic. The RPC has separate voltage supplies (+3.3 V) and grounds for the analog and digital sections and the total power consumption is 495 μW. [ABSTRACT FROM AUTHOR]

The T2K (Tokai-to-Kamioka) experiment is a long baseline neutrino oscillation experiment in Japan, for which a near detector complex (ND280), used to characterize the beam, will be built 280 m from the target in the off-axis direction of the neutrino beam produced using the 50 GeV proton synchrotron of J-PARC (Japan Proton Accelerator Research Complex). The central part of the ND280 is a detector including 3 large Time Projection Chambers based on Micromegas gas amplification technology with anodes pixelated into about 125,000 pads and requiring therefore compact and low power readout electronics. A 72-channel front-end Application Specific Integrated Circuit has been developed to read these TPCs. Each channel includes a low noise charge preamplifier, a pole zero compensation stage, a second order Sallen-Key low pass filter and a 511-cell Switched Capacitor Array. This electronics offers a large flexibility in sampling frequency (50 MHz max.), shaping time (16 values from 100 ns to 2 ), gain (4 ranges from 120 fC to 600 fC), while taking advantage of the low physics events rate of 0.3 Hz. Fabricated in 0.35 CMOS technology, the prototype has been validated and meets all the requirements for the experiment so that mass production has been launched at the end of 2007. [ABSTRACT FROM PUBLISHER]

In this paper, passive continuous-time (CT) ΣΔ modulators are briefly reviewed and compared with conventional active CT ΣΔ modulators. A fifth-order CT ΣΔ modulator with a hybrid active-passive loop filter is realized with only three active integrators. The hybrid CT ΣΔ modulator is robust to the excess loop delay, clock jitter, and RC product variations. The prototype chip is designed in a 0.25-μm CMOS technology targeting for GPS or WCDMA applications. The experimental results show that the prototype ΣΔ modulator achieves a 68-dB dynamic range and a -75 dB IM3 over a 2-MHz bandwidth with a 150-MHz clock, consuming 1.8 mA from a 1.5-V supply. [ABSTRACT FROM AUTHOR]

Voltage-controlled oscillators (VCOs) have been shown to dominate the single-event transient (SET) response of mixed-signal circuits such as the phase-locked loop (PLL). An analytical model is presented to determine the VCO design parameters and the associated SET vulnerability. Additionally, radiation-hardened-by-design (RIIBD) techniques to mitigate SETs in current-starved VCOs are presented; The proposed mitigation techniques reduce the phase displacement in the output of the VCO following a single-event (SE) by approximately 66%. The availability of the analytical model and RHBD techniques will improve the SE performance of VCO and PLL designs to ensure a specified tolerance to SEs. [ABSTRACT FROM AUTHOR]

A radiation-hardened-by-design phase-locked loop (PLL)—designed and fabricated in 130 nm CMOS—is shown to mitigate single-event transients (SETs). Two-photon-absorption (TPA) laser tests were used to characterize the error signatures of the PLL and to perform single-event upset (SEU) mapping of the PLL sub-components. Results show that a custom, voltage-based charge pump reduces the error response of the PLL over conventional designs by more than two orders of magnitude as measured by the number of erroneous PLL clock pulses following a single-event. Additionally, SEU mapping indicates a 99% reduction in the vulnerable area of the radiation-hardened-by-design (RHBD) charge pump over a conventional design. Furthermore, the TPA experiments highlight the importance of the voltage-controlled oscillator in the overall SET response of the PLL implementing the RHBD charge pump. [ABSTRACT FROM AUTHOR]

During the last decade, ADCs using single ramp architecture have been widely used in integrated circuits dedicated to nuclear science applications. These types of converters are actually very well suited for low power, multi-channel applications. Moreover their wide dynamic range and their very good differential non-linearity are perfectly matched to spectroscopy measurement. Unfortunately, their use is limited by their long conversion time, itself limited by their maximum clock frequency. A new architecture is described in this paper. It permits speeding up the conversion time of the traditional ramp ADC structures by a factor of 32 while keeping a low power consumption. Measurement results on a 4-channel, 12-bit prototype using a 3.2 GHz virtual clock are then presented in detail, showing excellent performances of linearity and noise. [ABSTRACT FROM AUTHOR]

Meeting performance specifications in the design of analog and RF (A/RF) blocks and integrated circuits (IC) continues to require a high degree of skill, creativity, and expertise. However, today's A/RF designers are increasingly faced with a new challenge. Functional complexity in terms modes of operation, extensive digital calibration, and architectural algorithms is now overwhelming traditional A/RF design methodologies. Functionally verifying A/RF designs is a daunting task requiring a rigorous methodology. As occurred in digital design, analog verification is becoming a separate and critical task. This paper describes the verification issues faced by the A/RF designer and presents a verification methodology to address these challenges. It presents a systematic approach to A/RF verification, the concept of an analog verification engineer, how to establish the methodology, and concludes with an example. [ABSTRACT FROM AUTHOR]

We describe an integrated circuit for sensing the substrate coupling capacitance of anchorage-dependent living cells in a standard culture environment. Capacitance is measured using charge redistribution in response to weak, low frequency electric field excitations. The underlying biophysical phenomenon results primarily from the insulating nature of the cell structure and the counterionic polarization in the surrounding aqueous medium. The measured capacitance depends on a variety of factors related to the cell, its growth environment and the supporting substrate. These include membrane integrity, morphology, extracellular ionic concentration, adhesion strength, and substrate proximity. The measured capacitance is an indication of both the interaction between cells and substrate and cell health. The capacitance sensor uses the principle of charge sharing and translates sensed capacitance values to output voltages. The sensor chip has been fabricated in a commercially available 0.5-mum, 2-poly 3-metal CMOS technology. The sensing technique does not require direct electrical connection to the aqueous culture medium. We report results from experiments demonstrating on-chip tracking of cell adhesion as well as long term monitoring of cell viability in vitro [ABSTRACT FROM PUBLISHER]

This paper describes a novel method for the digital synthesis of high quality signals by means of 1-bit digital-to-analog converters. The aim of this paper is the identification of the best binary sequences for signal generation and the analysis of their properties. Such sequences are obtained by genetic algorithms, either independently of a physical implementation of the analog-to-digital converter, or by optimizing the parameters of an over- sampled conversion. [ABSTRACT FROM AUTHOR]

Issues related to substrate noise in system-on-chip design are described including the physical phenomena responsible for its creation, coupling transmission mechanisms and media, parameters affecting coupling strength, and its impact on mixed-signal integrated circuits. Design guidelines and best practices to minimize the generation, transmission, and reception of substrate noise are outlined, and different modeling approaches and computer simulation methods used in quantifying the noise coupling phenomena are presented. Finally, experiments that validate the modeling approaches and mitigation techniques are reviewed. [ABSTRACT FROM AUTHOR]

Abstract: This paper presents the impact of low-frequency substrate disturbances on a fully integrated voltage-controlled oscillator (VCO) spectrum. A 4.5GHz VCO test-chip is presented; two substrate taps are placed inside the VCO core to measure or to inject disturbances into the substrate. The VCO carrier frequency sensitivity function of the tuning voltage and the bias current are measured. Then, the VCO spurious side-bands caused by harmonic substrate noise disturbances are analyzed to find a relation between the substrate noise characteristics and spur magnitudes. Theoretically the impulse sensitivity function (ISF) approach is used to analyze device sensitivity to substrate noise. Finally, a significant link between device sensitivity functions, low-frequency substrate disturbances and the VCO side-band spectral power, is demonstrated. According to this study, we conclude that a global approach which only considers power supply bounces in mixed IC''s is not sufficient to analyze the sensitivity of RF integrated oscillators to low frequency substrate noise. [Copyright &y& Elsevier]

A mixed-signal ASIC that implements an ultrasound front-end receiver in a 0.6 μm BiCMOS HotASIC technology that features metal/metal capacitors and polyl/poly2 resistors is described. The ASIC includes a low-noise amplifier (LNA), a programmable gain amplifier (PGA), an output differential amplifier (ODA), and a second-order sigma-delta modulator (SDM), and is the most compact system for high-temperature ultrasound applications reported in literature. The circuit has a programmable gain and is designed for measuring the signal response (200 kHz to 700 kHz) from an ultrasound transducer. At 48 MHz clock frequency and 200 °C, the power consumption is 85 mW from a single 5 V supply. The die area of the chip is 5.52 mm². [ABSTRACT FROM AUTHOR]

This paper describes a low-power 22-bit incremental ADC, including an on-chip digital filter and a low-noise/low-drift oscillator, realized in a 0.6-μm CMOS process. It incorporates a novel offset-cancellation scheme based on fractal sequences, a novel high-accuracy gain control circuit, and a novel reduced-complexity realization for the on-chip sinc filter. The measured output noise was 0.25 ppm (2.5 μVRMS), the DC offset 2 μV, the gain error 2 ppm, and the INL 4 ppm. The chip operates with a single 2.7–5 V supply, and draws only 120 μA current during conversion. [ABSTRACT FROM AUTHOR]

This paper desribes the design and realization of a 15-bit 30-MS/s three-step ADC for imaging applications with a peak-to-peak signal to rms noise ratio (DRpp) of 85 dB. The offsets of the residue amplifiers are independently background calibrated. The ADC is realized in single-poly, 0.18-μm CMOS, measures 1.4 mm², and dissipates 145 mW from 1.8-V and 3.3-V supplies. [ABSTRACT FROM AUTHOR]

With semiconductor technology feature size scaling below 100 nm, mixed-signal design faces some important challenges, caused among others by reduced supply voltages, process variation, and declining intrinsic device gains. Addressing these challenges requires innovative solutions, at the technology, circuit, architecture, and design-methodology level. We present some of these solutions, including a structured platform-based design methodology to enable a meaningful exploration of the broad design space and to classify potential solutions in terms of the relevant metrics. [ABSTRACT FROM AUTHOR]

This paper describes a new noise-shaping technique for reducing the noise of the internal digital-analog conversion (DAC) in multi-bit low-pass sigma-delta modulators. The proposed technique works with most existing dynamic element matching (DEM) algorithms to provide noise shaping to the DAC noise. The simulation shows that a 10-dB improvement in the signal-to-noise conversion ratio can be obtained with the proposed noise-shaping with DEM (NSDEM) technique. A dithered DAC employing NSDEM is realized in a 0.35-µm CMOS process and the test result shows the first-order high-pass noise shaping to the DAC noise, and validates the proposed concept. [ABSTRACT FROM AUTHOR]

Abstract: This paper describes a novel method for the digital synthesis of high quality signals by means of one-bit digital-to-analog converters. The aim of the work is the analysis of the best binary sequences for signal generation, obtained using evolutionary algorithms. [Copyright &y& Elsevier]

Self-calibration in approximately 10 000 conversions is demonstrated in a 16-bit, 1-MS/s algorithmic analog-to-digital converter (ADC). Continuous digital background calibration is enabled by introduction of a "split ADC" architecture, in which the die area of a single ADC design is split into two independent converters, each converting the same input signal. The two independent outputs are averaged to produce the ADC output code. The difference of the two outputs provides information for the background calibration process. Since both ADCs convert the same input, when correctly calibrated their outputs should be equal and the difference should be zero. Any nonzero difference provides information to an error estimation process which adjust calibration parameters in each ADC. For the specific realization of an algorithmic ADC described in this paper, a multiple residue mode amplifier is used to ensure different decision trajectories and provide valid calibration information. The analog sub-system of the ADC is implemented in 0.25-µm CMOS, consumes 105 mW, and has a die size of 1.2 mm × 1.4 mm. [ABSTRACT FROM AUTHOR]

We present a high-bandwidth Hartmann-Shack sensor for adaptive optics implemented in a standard 0.35 µm CMOS process technology. Hartmann-Shack sensors reconstruct an optical wavefront from the displacement of focal points as imaged by a microlens array. This image is usually captured by CCD cameras and then processed by software, limiting the wavefront bandwidth to a few hertz. The presented CMOS-based sensors achieves a frame rate of up to 4 kHz by analog image processing on the focal plane. The implemented position sensitive detectors consist of a resistive-ring network of Winner-Take-All circuits with reduced sensitivity to transistor mismatch and fixed-pattern noise. This CMOS-based wavefront sensor allowed the first high-bandwidth wavefront measurements at the human eye. [ABSTRACT FROM AUTHOR]

This paper describes a 0.35-pm CMOS chopper-stabilized switched-capacitor 2-1 cascade ΣΔ modulator for automotive sensor interfaces. The modulator architecture has been selected from an exhaustive comparison among multiple topologies in terms of resolution, speed and power dissipation. To obtain a better fitting with the characteristics of different sensor outputs, the circuit can be digitally programmed to yield four input-to-output gain values (x0.5, x1, x2, and x4) and has been designed to operate within the stringent environmental conditions of automotive electronics (temperature range of -40 ° to 175 °C). In order to relax the amplifier's dynamic requirements for the different modulator input-to-output gains, switchable capacitor arrays are used for all the capacitors in the first integrator. The design of the building blocks is based on a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The circuit is clocked at 5.12 MHz and the overall power consumption is 14.7 mW from a single 3.3-V supply and occupies 5.7 mm² silicon area. Experimental results show a maximum SNR of 87.3 dB within a 20-kHz signal bandwidth and 90.7 dB for 10-kHz signals, and an overall DR of 110 and 113.8 dB, respectively. These performance features place the reported circuit at the cutting edge of state-of-the-art high-resolution ΣΔ modulators. [ABSTRACT FROM AUTHOR]

Adding two clocked tunnel diode pairs to the output ports of a differential amplifier enables high-speed current-mode switching at a tower tail current than in a transistor-only differential pair. The addition of the tunnel diodes also lowers the output open-circuit time constant of the differential pair leading to faster switching speed. As a design example, a return-to-zero D flip-flop is simulated for use as the decision circuit in a single-bit oversampling digital-to-analog converter. Indium phosphide-based heterojunction bipolar transistors and resonant tunneling diodes are used in the model simulation; both conventional and tunnel-diode-augmented circuits are compared. Power dissipation of 35 mW/latch at 100-GHz clock frequency with 60-dBc spur-free dynamic range (SFDR) is obtained in the tunnel diode/transistor flip-flop. In comparison with the transistor-only approach, power is reduced by approximately 1.6 × at the same speed and SFDR. [ABSTRACT FROM AUTHOR]

A cascade of sigma-delta modulator stages that employ a feedforward architecture to reduce the signal ranges required at the integrator inputs and outputs has been used to implement a broadband, high-resolution oversampling CMOS analog-to-digital converter capable of operating from low-supply voltages. An experimental prototype of the proposed architecture has been integrated in a 0.25-µm CMOS technology and operates from an analog supply of only 1.2 V. At a sampling rate of 40 MSamples/sec, it achieves a dynamic range of 96 dB for a 1.25-MHz signal bandwidth. The analog power dissipation is 44 mW. [ABSTRACT FROM AUTHOR]

In mixed analog-digital designs, digital switching noise is an important limitation for the performance of analog and RF circuits. This paper reports a physical model describing the impact of digital switching noise on LC-tank voltage-controlled oscillators (VCOs) in lightly doped substrates. The model takes into account the propagation from the source of substrate noise to the different components in the VCO and the resulting modulation of the oscillator frequency. The model is validated with measurements on a 3.5-GHz LC-tank VCO designed in 0.18-µm CMOS. It reveals that for this VCO, impact occurs mainly via the nonideal metal ground lines for lower frequencies and low tuning voltage and via the integrated inductors for higher frequencies and high tuning voltage. To make the design immune to substrate noise, the parasitic resistance of the on-chip ground interconnect has to be kept as low as possible and inductors have to be shielded. Hence, the developed model allows investigating the dominant mechanisms behind the impact of substrate noise on a VCO, which is crucial information for achieving a substrate noise immune design. [ABSTRACT FROM AUTHOR]

This paper presents a mixed-signal application-specific integrated circuit (ASIC) for a frequency-modulated differential chaos shift keying (FM-DCSK) communication system. The chip is conceived to serve as an experimental platform for the evaluation of the FM-DCSK modulation scheme, and includes several programming features toward this goal. The operation of the ASIC is herein illustrated for a data rate of 500 kb/s and a transmission bandwidth in the range of 17 MHz. Using signals acquired from the test platform, bit error rate (BER) estimations of the overall FM-DCSK communication link have been obtained assuming wireless transmission at the 2.4-GHz ISM band. Under all tested propagation conditions, including multipath effects, the system obtains a BER = 10-3 for Eb/No lower than 28 dB. [ABSTRACT FROM AUTHOR]

Noise, especially clock jitter effects, in a DSP-based mixed-signal test system severely limits its measurement accuracy. This is especially acute in high-frequency sampling systems. This paper illustrates an efficient method to improve measurement accuracy and precision by reducing the uncertainty of a DSP-based measurement without an increase in test time. A new digitizer architecture is introduced. The digitizer was fabricated in a 0.18-pm CMOS process. Experimental results were obtained validating the proposed technique. [ABSTRACT FROM AUTHOR]