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The effective thickness of the amorphous chalcogenide part within the active element of a phase-change memory cell is estimated through electrical measurements. Current–voltage characteristics obtained at various intermediate cell states are fitted with the trap-limited subthreshold transport model of [9] and the amorphous part thickness is then extracted. Several cell electrical measures, such as the resistance and the threshold voltage, are shown to closely relate to the estimated parameter. The results serve to further validate the trap-limited conduction model, as well as the series phase distribution hypothesis in the active layer of a phase-change memory cell.

The resistance of phase-change-memory (PCM) cells measured during RESET programming (dynamic resistance, Rd) is found to be inversely proportional to the amplitude of the programming current, as Rd = [A/I] + B. We show that parameters A and B are related to the intrinsic properties of the memory cell, and demonstrate by means of experimental data that they could be used to characterize the cell-to-cell process-induced variability of PCM cells.

Transistors have been fabricated with a photoresist mask placed in close proximity to the gate so as to effectively block the angled halo implant from the gate region. Devices for which the halo has been eliminated demonstrate superior drain conductance, while devices with the halo implant show the short-channel effect required for high performance. Asymmetric devices have also been fabricated in a similar manner, producing devices with improved analog characteristics without an additional masking layer.

We study the effect of programming current on the endurance failure of phase change memory and propose a general scheme of optimizing programming currents for the most endurance cycles. We consider two major endurance failure modes, stuck-SET and open failure. We show that higher current does not necessarily cause, and even prevents the earlier open failure and attribute it to phase-dependent open-failure mechanisms. As for the stuck-SET failure, RESET current is optimized to balance material segregation effect and RESET current margin. The overall programming conditions are optimized by combining open and stuck-SET failure characteristic curves.

Various aspects of ultra-low leakage static random-access memories (SRAM) cell design are considered. It is shown that the high threshold voltage relative to the power supply so improves the stability of the cell that the beta ratio of the design may be made very small for improved performance. Also, the ramifications of threshold uncertainty due to random dopant fluctuations are investigated, and it is shown that chip performance will be adversely affected by this phenomenon.

A new cell-state metric is proposed for multilevel phase-change memory (PCM) that is more representative of the fundamental programmed entity, i.e., the amorphous/crystalline phase configuration in the PCM cell. This metric exhibits improved performance in terms of drift and better sensing resolution of cell states with a large amorphous-phase fraction when compared to the conventional low-field resistance metric. Experimental results using PCM test devices of mushroom type demonstrate the efficacy of the new metric.

Phase change memory has long suffered from conflicting material properties between switching speed and thermal stability. This study explores the engineering of GeSbTe ternary alloys along an isoelectronic tie line and the Ge/Sb 2 Te 3 tie line with the hope of finding a high performance material. Our efforts resulted in a new material that considerably outperforms the conventional GST-225. The switching speed is similar to undoped GST-225, with ∼ 30% lower reset current, and nearly 100°C higher T x , thus much better thermal stability. The promising properties of this new material are demonstrated in a 128Mb chip and tested both at wafer level and as packaged dies. These devices showed 1E8 cycling endurance and withstood 190 °C testing.

Application of phase change memory (PCM) has been limited by the high power required to reset the device (changing from crystalline to amorphous state by melting the phase change material). Utilizing the poor thermal and electrical conductivity of TaN we have designed a simple structure that thermally insulates the bottom electrode and thus drastically reduces the heat loss. A 39nm bottom electrode with a TaN thermal barrier and 1.5nm of TiN conductor has demonstrated 30µA reset current, representing a 90% reduction. The benefit of thermal insulation is understood through electrothermal simulation, and the benefit is demonstrated in a 256Mb test chip. The low reset current also improves the reliability and excellent cycling endurance >1E9 is observed. This low power device is promising for expanding the application for PCM.

Multilevel-cell (MLC) storage is a typical way for achieving increased capacity and thus lower cost-per-bit in memory technologies. In phase-change memory (PCM), however, MLC storage is seriously hampered by the phenomenon of resistance drift. Reference cells may be used to offer some relief, however their effectiveness is limited due to the stochastic nature of drift. In this paper, an alternative way to cope with drift in PCM is introduced, based on modulation coding. The new drift tolerant coding technique encodes information in the relative order of resistance levels in a codeword. Experimental results from a 90-nm PCM prototype chip demonstrate the effectiveness of the proposed method in offering high resilience to drift. Most notably, 4 levels/cell storage with raw bit-error-rates in the order of 10 -5 is achieved in a 200 kcell array and maintained for over 30 days after programming at room temperature.

This paper presents a novel reconfigurable sensing scheme with the flexibility to change reading precision of analog resistance levels for MLC PCM. A 2Mcell PCM chip was fabricated in 90nm CMOS technology and was tested. Operating at 8-bits precision (adequate for 7b/cell PCM i.e., 128 resistance levels), read access latency is 5μs (measured at 50MHz clock), compared to 35-50μs in state-of-art 2b/cell NAND Flash.

Phase-change memory (PCM) has emerged as one among the most promising technologies for next-generation nonvolatile solid-state memory. Multilevel storage, namely storage of non-binary information in a memory cell, is a key factor for reducing the total cost-per-bit and thus increasing the competitiveness of PCM technology in the nonvolatile memory market. In this paper, we present a family of advanced programming schemes for multilevel storage in PCM. The proposed schemes are based on iterative write-and-verify algorithms that exploit the unique programming characteristics of PCM in order to achieve significant improvements in resistance-level packing density, robustness to cell variability, programming latency, energy-per-bit and cell storage capacity. Experimental results from PCM test-arrays are presented to validate the proposed programming schemes. In addition, the reliability issues of multilevel PCM in terms of resistance drift and read noise are discussed.

We demonstrate novel designs for Content Addressable Memory (CAM) and Ternary CAM (TCAM) using Phase Change Memory (PCM) technology, which can potentially improve density and power consumption by >;5X as compared with conventional SRAM based implementations. Using Monte-Carlo simulations, we also predict the desired characteristics of PCM devices for realizing large, high performance CAM/TCAM chips.

We present a comprehensive investigation of noise in multi-bit phase-change memory (PCM). The impact of noise on data integrity was quantified with a combination of experiments and simulations. A prototype chip was fabricated to support our system-level analysis, which shows that a raw bit error rate of ∼10−4 is achievable at 3-bit/cell. At the circuit level, we identified the bit line capacitance and the voltage regulator noise as the critical elements determining the electronic readout circuit noise. In addition, device-level measurements showed that 80% of the total noise can be traced back to the fluctuations in the PCM cell current itself. Our analysis captures for the first time how these fluctuations ultimately limit the achievable bit error rate in future multi-level-cell (MLC) PCM chips.

Phase-change memory (PCM) has emerged in recent years as one among the most attractive technologies for future non-volatile solid-state memory. PCM relies on the reversible phase transition in chalcogenide materials between different states, i.e., amorphous and poly-crystalline, which are characterized by very different electrical properties. Multilevel storage, namely storage of multiple bits in a memory cell, is a key factor for the competitiveness of PCM technology in the nonvolatile memory market. This paper presents experimental characterization of multilevel PCM devices and addresses the feasibility and reliability issues of multilevel storage using adaptive program-and-verify schemes.

The high current density induced failure in Ge 2 Sb 2 Te 5 (GST)-based phase change memory (PCM) is investigated. A strong dependence of cycling endurance on the polarity of the operation current is observed and reported for the first time. The cycling endurance is reduced by 4 orders of magnitude when the current polarity is reversed. Careful TEM analysis of failed cells revealed a thin void in GST over the bottom electrode, but only in the reverse polarity samples. This phenomenon can be explained by hole-induced electromigration at the electrode/GST interface. The impact of electromigration on scaled phase change memory is discussed.

Selective Chemical Vapor Deposition of Crystalline Ge-Sb-Te alloys initiating at the bottom metal contact of vias of various sizes has been accomplished. The method is based on selecting Sb and Te precursors which do not decompose on dielectric surfaces in the utilized temperature range.

We survey the current state of phase change memory (PCM), a non-volatile solid-state memory technology built around the large electrical contrast between the highly-resistive amorphous and highly-conductive crystalline states in so-called phase change materials. PCM technology has made rapid progress in a short time, having passed older technologies in terms of both sophisticated demonstrations of scaling to small device dimensions, as well as integrated large-array demonstrators with impressive retention, endurance, performance and yield characteristics. We introduce the physics behind PCM technology, assess how its characteristics match up with various potential applications across the memory-storage hierarchy, and discuss its strengths including scalability and rapid switching speed. We then address challenges for the technology, including the design of PCM cells for low RESET current, the need to control device-to-device variability, and undesirable changes in the phase change material that can be induced by the fabrication procedure. We then turn to issues related to operation of PCM devices, including retention, device-to-device thermal crosstalk, endurance, and bias-polarity effects. Several factors that can be expected to enhance PCM in the future are addressed, including Multi-Level Cell technology for PCM (which offers higher density through the use of intermediate resistance states), the role of coding, and possible routes to an ultra-high density PCM technology., Comment: Review article

A method based on Frenkel-Poole emission is proposed to model the amorphous state (high resistance state) in mushroom-type phase-change memory devices. The model provides unique insights to probe the device after amorphizing (RESET) operation. Even when the resistance appears the same under different RESET conditions, our model suggests that both the amorphous region size and the defect states are different. With this powerful new tool, detailed changes inside the amorphous GST for MLC operation and retention tests are revealed.

The effective thickness of the amorphous chalcogenide part within the active element of a phase change memory (PCM) cell is estimated through electrical measurements. Current-voltage characteristics obtained at various intermediate cell states are fitted with the trap-limited subthreshold transport model and the amorphous part thickness is then extracted. Several cell electrical measures, such as the resistance and the threshold voltage, are shown to closely relate to the estimated parameter. The results serve to further validate the trap-limited conduction model, as well as the series phase distribution hypothesis in the active layer of a PCM cell.

We describe a cycling failure mode in Ge 2 Sb 2 Te 5 -based phase change memory, based on density difference of GST in different phases and the SET/RESET thermal operations. Voids that develop and merge with each other within GST programming volume after cycling eventually lead to cell failure. By adding suitable amount of doping material into GST, we are able to delay this void formation process and to significantly improve the cell endurance to more than 10 9 cycles.

We demonstrate poly-Silicon emitter vertical PNP Bipolar Junction Transistors (BJTs) that could be used as access devices for Phase Change Memory. The device arrays fabricated using a 180nm BiCMOS process exhibit current drive capability in excess of 10mA/µm2, On-Off ratio greater than six orders of magnitude and excellent cross-talk immunity. Our process integration scheme could be extended to enable a high-density Phase Change Memory technology.

This chapter reviews the basic process integration and structural design issues regarding the phase change random access memory cell. Basic memory cell design, phase change device characteristics and access device requirements will be reviewed, and then a detailed discussion of the phase change memory device design follows. Various cell designs, including the mushroom cell, cell, μTrench cell and pore cell will be evaluated in terms of RESET current (the current to switch the cell to the amorphous state by melting and rapidly quenching) and RESET current variability minimization. Finally, multi-level phase change random access memory will be discussed.

Data retention loss from the amorphous (RESET) state over time in Phase-Change Memory cells is associated with spontaneous crystallization. In this paper, the change in the threshold voltage (VT) of memory cells in the RESET state before and after heating is used as a probe into the nature of the retention loss mechanisms. Two mechanisms for the retention loss behavior are identified, responsible for the main distribution and the tail distribution, respectively. Experimental results suggest that (i) an optimized RESET operation produces a fully amorphized Ge2Sb2Te5 (aGST) active region, with no crystalline domains inside, (ii) cells in the tail distribution fail to retain their RESET state due to spontaneous generation of crystallization nuclei and grain growth, and (iii) cells in the main distribution fail due to grain growth from the amorphous/crystalline GST boundary, instead of nucleation within the active region.

We present a novel analytical model for the RESET operation of Phase Change Memory (PCM) that explicitly describes the dependency of the programming current on various cell dimensions and material parameters. This model also explains, for the first time, the fundamental physics behind the inverse relationship between dynamic resistance(Rd) and the amplitude of the programming current.

This paper will give an introduction to the emerging technology of Phase Change Memory (PCM) and review the state of the art, focusing on basic phase change material properties, critical PCM device characteristics, PCM device scaling, reliability issues, and processing challenges.

A novel characterization metric for phase change memory based on the measured cell resistance during RESET programming is introduced. We show that this dasiadynamic resistancepsila (Rd) is inversely related to the programming current (I), as Rd = [A/I] + B. While the slope parameter A depends only on the intrinsic properties of the phase change material, the intercept B also depends on the effective physical dimensions of the memory element. We demonstrate that these two parameters provide characterization and insight into the degradation mechanisms of memory cells during operation.

In this paper, a detailed study on the etching characteristics of nitrogen doped Ge2Sb2Te5 (N:GST) thin films is performed to elucidate the relationship between pattern fidelity and material modification. Multiple methodologies ranging from physical sputtering to chemically driven reactive etching are shown to successfully pattern highly anisotropic features in N:GST films while the advantages and limitations of each are discussed. Subsequently, the presence of material modification during patterning has been identified using a combination of depth profiled X-ray photoelectron spectroscopy (XPS), transmission electron microscopy and electron energy loss spectroscopy (TEM-EELS). Results indicate the selective removal of antimony and nitrogen along with an increased amount of oxidized tellurium. Lastly, a novel method to selectively remove damaged N:GST material is presented.

We discuss novel multi-level write algorithms for phase change memory which produce highly optimized resistance distributions in a minimum number of program cycles. Using a novel integration scheme, a test array at 4 bits/cell and a 32 kb memory page at 2 bits/cell are experimentally demonstrated.

We have successfully demonstrated a novel "pore" phase change memory cell, whose critical dimension (CD) is independent of lithography. Instead, the pore diameter is accurately defined by intentionally creating a "keyhole" with conformal deposition. Fully integrated 256 kbit test chips have been fabricated in 180nm CMOS technology. We report SET times of 80 ns, RESET currents less than 250 muA, and accurate sub-lithographic CDs that can be less than 20% the size of the lithographically -defined diameter.

A novel Pillar phase change memory based on fully integrated test arrays in 180nm CMOS technology has been successfully fabricated. A current-confining Pillar structure leads to a self-heating at the center of the chalcogenide layer, and needs only one additional mask level for its fabrication. Switching characteristics with write currents less than 900muA at 75nm diameter and multilevel operation are reported

This paper presents challenges in creating high quality RF FET layouts and models in CMOS technologies spanning 0.25 /spl mu/m to 90 nm nodes. The focus is on developing a comprehensive methodology to provide robust, high performance parameterized RF FET layout cells and corresponding scalable RF models to enable RF designs that fully leverage the cost benefit potential of CMOS technology.

The effort to design RF circuits in CMOS is motivated by low cost and significant capacity for on-chip integration. We discuss some of the challenges of implementing RF designs in CMOS, focusing on those introduced by the changing properties of FETs as technology nodes scale and devices shrink. We present methods and tools, using which, designers can ease these challenges and reduce the risk of implementing RF circuits in CMOS.

Exponential growth in leakage power density with physical scaling is driving ULSI technology towards innovative device architectures. Double-gate CMOS (DGCMOS), achieved through use of the Delta Device (D.Hisamoto et al, IEDM 1989, p.833-836), or FinFET (X.Huang et al, IEDM 1999, p.67-70), provides both a tactical solution to the gate-leakage challenge and a strategic scaling advantage. FinFET fabrication is very close to that of the conventional CMOS process, with only minor disruptions, yielding the potential for a rapid deployment to manufacturing. Planar circuit designs have been converted to FinFET-DGCMOS without disruption to physical area.

An operational six-transistor SRAM cell is experimentally demonstrated using Double Gate CMOS FinFET technology. A cell size of 4.8 /spl mu/m/sup 2/ was achieved in 180 nm node technology, with stable operation at 1.5 V using a single level of copper interconnect. To our knowledge this represents the first experimental demonstration of a fully integrated FinFET SRAM Cell.

An ultra-thin phase-change bridge (PCB) memory cell, implemented with doped GeSb, is shown with < 100muA RESET current. The device concept provides for simplified scaling to small cross-sectional area (60nm2) through ultra-thin (3nm) films; the doped GeSb phase-change material offers the potential for both fast crystallization and good data retention