Write Strategies for 2 and 4-bit Multi-Level Phase-Change Memory

Authors :: T.D. Happ
J.B. Phipp
Min Yang
S. Raoux
R. Cheek
A.G. Schrott
Shoaib Hasan Zaidi
Y. Zhu
Y.-C. Chen
M. Lamorey
Hsiang-Lan Lung
T. Nirschl
Ming-Hsiu Lee
Bipin Rajendran
Matthew J. Breitwisch
R. Bergmann
C.-F. Chen
Geoffrey W. Burr
Chung H. Lam
Shih-Hung Chen
Eric A. Joseph
Source :: 2007 IEEE International Electron Devices Meeting.
Publication Year :: 2007
Publisher :: IEEE, 2007.
Abstract: We discuss novel multi-level write algorithms for phase change memory which produce highly optimized resistance distributions in a minimum number of program cycles. Using a novel integration scheme, a test array at 4 bits/cell and a 32 kb memory page at 2 bits/cell are experimentally demonstrated.