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In recent years, silicon nanocrystals embedded in insulator thin layers have attracted much interest for developing metal–insulator–semiconductor optoelectronic devices, but crystalline silicon quantum wells not yet developed because of the difficulty of making a crystalline quantum well-embedded in an amorphous dielectric layer. In this work, we report an original method for the fabrication of single-crystalline silicon quantum wells embedded in an SiO2 thin layer for high-performance photodetectors and solar cell applications. The fabrication method is based on thermal treatment of ultra-thin silicon-on-insulator (UT-SOI) fabricated via smart-cut. High-resolution transmission electron microscopy (HR-TEM) and spectroscopic ellipsometry structural investigations show that the silicon quantum well-embedded in the SiO2 layer is single-crystalline, free of structural defects, and has a uniform thickness perfectly suitable for optoelectronic applications. Opto-electrical studies using current–voltage spectroscopy (I–V) and photocurrent spectroscopy show that silicon quantum wells inserted into a metal–insulator–semiconductor (MIS)-based device improve electrical transport and increase very high photocurrent more efficiently than silicon nanocrystals. The results obtained show that these single-crystalline silicon quantum wells embedded in SiO2 are very promising for developing high-performance silicon photodetectors and solar cells compatible with CMOS technology. [ABSTRACT FROM AUTHOR]

HgCdTe detectors are a key technology for space-based infrared imagery. Radiation in the space environment affects the performance of these detectors. Gamma and protons irradiation are performed in order to assess the impact of total ionising dose and displacement damage dose on the dark current of mid-wavelength infrared HgCdTe photodiodes. Parameters such as dark current contributions, lateral collection length and activation energy are studied following irradiation. Metal–insulator–semiconductor devices were also irradiated in order to study the mechanisms of interface contributions to the dark current. A focal plane array was used to measure response evolution with irradiation. This study also analyses the impact of a post-irradiation thermal cycle on the evolution of the dark current. [ABSTRACT FROM AUTHOR]

We present a planar three terminal device fabricated on a silicon-on-insulator substrate. The device is based on a two-layer dielectric stack comprising SiO2 tunneling and HfO2 layers. A so-called gate electrode is placed between two other contacts, of the source and drain, all deposited on the insulator stack. In the dark as well as under illumination, the current-voltage characteristic can be shifted in an ideal linear manner with changes in a positive gate voltage with the shift being somewhat larger under illumination. The reason for the change of shift is the ability of high-density oxygen vacancies, arranged in the filament regions within an HfO2 sublayer that was voltage stress. Namely, holes or electrons are trapped in the HfO2 sublayer, respectively, from the inverted or accumulated Si layer. This process is controlled by the gate and drain bias levels. Moreover, under illumination and at negative gate and drain voltages, the device exhibits negative differential resistance caused by capture of photo-generated minority carriers induced in the depletion region of the Si after they tunnel through the SiO2 layer by negative oxygen vacancies that migrate to the SiO2/HfO2 interface through the filament regions. Finally, the low level of saturation current in the dark and the ability to precisely control its value by illumination intensity, together with a large sensitivity of 80-85 A/W and 25 A/W, at 490 nm and 365 nm, respectively, allow additional applications that cannot be achieved with conventional MIS devices. [ABSTRACT FROM AUTHOR]

In this work, homogeneous surface oxidation of hafnium disulfide (HfS2) is achieved by an extremely simple thermal treatment, i.e., mild oxidization in air. Due to the high thermal stability of hafnium dioxide (HfO2), atomically flat HfO2 is formed on top of unoxidized HfS2 and unlimited layer-by-layer oxidation is observed. The thickness of HfO2 can be controlled by oxidation temperature and time. The HfO2 layer fabricated by the oxidation of HfS2 is smooth and atomically flat with roughness comparable to that of pristine HfS2. Growth of a high-quality, uniform, atomically flat oxide film on top of semiconductor is the first step for the fabrication of field effect transistors and metal-insulator-semiconductor devices. Thus, our results will facilitate the future fabrication of HfO2 films with atomic-scale thickness. [ABSTRACT FROM AUTHOR]

Toward interface charge engineering in AlTiO/AlGaN/GaN metal-insulator-semiconductor (MIS) devices, we systematically investigated insulator-semiconductor interface fixed charges depending on the composition of the AlTiO gate insulator obtained by atomic layer deposition. By evaluating the positive interface fixed charge density from the insulator-thickness dependence of the threshold voltages of the MIS devices, we found a trend that the interface fixed charge density decreases with the decrease in the Al composition ratio, i.e., increase in the Ti composition ratio, which leads to shallow threshold voltages. This trend can be attributed to the large bonding energy of O-Ti in comparison with that of O-Al and to consequent possible suppression of interface oxygen donors. For an AlTiO gate insulator with an intermediate composition, the MIS field-effect transistors exhibit favorable device characteristics with high linearity of transconductance. These results indicate a possibility of interface charge engineering using AlTiO, in addition to energy gap engineering and dielectric constant engineering. [ABSTRACT FROM AUTHOR]

In this work, a comprehensive characterization of metal-insulator-semiconductor structures by impedance spectroscopy is demonstrated for the case of electrically insulating, highly c-axis oriented, 600 nm sputter-deposited AlN films on n-Si substrates with Al top electrodes. Direct visual analysis and equivalent circuit fitting of the dielectric data were performed. For the latter procedure, the circuit model consisted of three series resistor-capacitor connection elements for the three dielectric contributions detected. The three contributions were identified as the AlN film, n-Si substrate, and an interface barrier effect. Several essential device parameters were determined separately, by visual or equivalent circuit fitting analysis, such as the dielectric permittivity of the AlN layer, the temperature dependence of the AlN permittivity, and the resistances of the AlN layer, the n-Si substrate, and the interface contribution. Furthermore, DC bias dependent impedance measurements allowed the identification of a Schottky-type interface barrier. [ABSTRACT FROM AUTHOR]

We describe a new metal-insulator-semiconductor (MIS) device in which cobalt based nano particles (NPs) in a core-shell structure (Co–core and Co3O4-shell) are embedded between a thermally grown SiO2 layer and a HfO2 film deposited by atomic layer deposition. Two additional structures were prepared for comparison. One had no NPs and the other included the Fe NPs, prepared using the same procedure as used for the Co film. All devices exhibited the classic behavior of a voltage variable MIS capacitor with or without a large hysteresis as in non-volatile memory (NVM) systems. However, only the device with the Co core-shell structure exhibits a negative photoconductivity (NPC) effect as well as NVM capabilities in both the capacitance-voltage (C-V) and current-voltage (I-V) characteristics. The dependence of C-V and current voltage I-V characteristics on illumination intensity and wavelength (from ultraviolet to near infrared) as well as on temperature was characterized. Illumination enhances the NPC effect as well as the flat-band voltage shift determined from C-V characteristics and hence the memory width. Illumination in the wavelength range of 735–780 nm caused a current decrease, at a given voltage, by up to a factor of two. The NPC effect stimulates an annihilation of the stored charges and therefore erases the system instantly at a small applied bias. The main cause of the NPC effect under illumination is the photo excitation of supplementary trap channels in the Co3O4 shell, which lowers the free carrier density and hence the conductivity of the MIS structure. [ABSTRACT FROM AUTHOR]

We have investigated insulator-semiconductor interface fixed charges in AlGaN/GaN metal-insulator-semiconductor (MIS) devices with Al2O3 or AlTiO (an alloy of Al2O3 and TiO2) gate dielectrics obtained by atomic layer deposition on AlGaN. Analyzing insulator-thickness dependences of threshold voltages for the MIS devices, we evaluated positive interface fixed charges, whose density at the AlTiO/AlGaN interface is significantly lower than that at the Al2O3/AlGaN interface. This and a higher dielectric constant of AlTiO lead to rather shallower threshold voltages for the AlTiO gate dielectric than for Al2O3. The lower interface fixed charge density also leads to the fact that the two-dimensional electron concentration is a decreasing function of the insulator thickness for AlTiO, whereas being an increasing function for Al2O3. Moreover, we discuss the relationship between the interface fixed charges and interface states. From the conductance method, it is shown that the interface state densities are very similar at the Al2O3/AlGaN and AlTiO/AlGaN interfaces. Therefore, we consider that the lower AlTiO/AlGaN interface fixed charge density is not owing to electrons trapped at deep interface states compensating the positive fixed charges and can be attributed to a lower density of oxygen-related interface donors. [ABSTRACT FROM AUTHOR]

A trade-off between the memory window and the endurance exists for transition-metal-oxide RRAM. In this work, we demonstrated that HfOx/Ge-based metal-insulator-semiconductor RRAM devices possess both a larger memory window and longer endurance compared with metal-insulator-metal (MIM) RRAM devices. Under DC cycling, HfOx/Ge devices exhibit a 100× larger memory window compared to HfOx MIM devices, and a DC sweep of up to 20,000 cycles was achieved with the devices. The devices also realize low static power down to 1 nW as FPGA's pull-up/pull-down resistors. Thus, HfOx/Ge devices act as a promising candidates for various applications such as FPGA or compute-in-memory, in which both a high ON/OFF ratio and decent endurance are required. [ABSTRACT FROM AUTHOR]

A standard experimental setup for Inelastic Electron Tunneling Spectroscopy (IETS) performs the measurement of the second derivative of the current with respect to the voltage ( d 2 I / d V 2 ) using a small AC signal and a lock-in based second harmonic detection. This avoids noise arising from direct differentiation of the current-voltage characteristics (I–V) by standard numerical methods. Here we demonstrate a noise-filtering algorithm based on Tikhonov Regularization to obtain IET spectra (i.e. d 2 I / d V 2 vs. V) from measured DC I–V curves. This leads to a simple and effective numerical method for IETS extraction. We apply the algorithm to I–V data from a molecular junction and a metal-insulator-semiconductor tunneling device, demonstrating that the computed first/second derivatives have a workable match with those obtained from our lock-in measurements; the computed IET spectral peaks also correlate well with reported experimental ones. Finally, we present a scheme for automated tuning of the algorithm parameters well-suited for the use of this numerical protocol in real applications. [ABSTRACT FROM AUTHOR]

This study was formed by the β-naphthol orange/p-Si metal–insulator–semiconductor (MIS) structure by obtaining β-naphthol orange on the p-Si surface using the sol–gel and spin-coating techniques. FTIR, EDX, and NMR analyzes of the synthesized dye-sensitized β-naphthol orange were performed. At room temperature, the current–voltage (I–V) measurements of the Al/β-naphthol orange/p-Si MIS structure showed that the device has a high rectification ratio of 3 × 105. Series resistance values were calculated as 385 and 38 Ω by Norde and Cheung methods, respectively. It was determined that the interface state density of the device was at the level of 1013 eV−1 cm−2 and increased exponentially from the middle of the bandgap to the upper edge of the valence band. Frequency-dependent capacitance–voltage (C–V) measurements at room temperature showed that the interface state densities in the device are effective in determining device parameters. [ABSTRACT FROM AUTHOR]

Metal-insulator-metal (MIM) tunnel junctions with the aluminum Oxide tunnel barriers confined between cobalt electrodes exhibit less resistance drift over time than junctions that utilize a thick, unconfined aluminum electrode. The improved long time stability is attributed to better initial Oxide quality achieved through confinement (use of a potential energy well for the Oxygen) and plasma Oxidation. In this work, Co/AlOx/Co and Co/Al/AlOx/Co tunnel junction aging is compared over a period of apprOximately 9 months using transport measurements and Wentzel-Kramers-Brillouin (WKB) based modelling. The Co/AlOx/Co (confined) tunnel junction resistance increased by (32?±?6) % over 5400?h, while Co/Al/AlOx/Co (unconfined) tunnel junction resistance increased by (85?±?23) % over 5200?h. Fit parameters for the tunnel barrier width and potential energy barriers were extracted using WKB transport modelling. These values change only a small amount in the confined Co/AlOx/Co tunnel junction but show a significant drift in the unconfined Co/AlOx/Co tunnel junction. [ABSTRACT FROM AUTHOR]

The effect of replacing a conventional metal with an organic conductive polymer in a metal-insulator- semiconductor (MIS) diode is examined theoretically and experimentally. Two sets of MIS diodes, one with gold and the other with poly(3,4-ethylenedioxythiophene) as the top “metal”, have been manufactured in parallel. Despite the two conductors having similar reported work functions of 5.1 eV to 5.2 eV, the hybrid devices exhibited far lower current densities as compared to their inorganic counterparts. Simulating the device behaviour reveals the limited width of the energy bands in the conductive polymer as the reason for low current density in the hybrid MIS. [ABSTRACT FROM AUTHOR]

We fabricated amorphous selenium (a-Se) photodetectors with a lateral metal-insulator-semiconductorinsulator- metal (MISIM) device structure. Thermal aluminum oxide, plasma-enhanced chemical vapor deposited silicon nitride, and thermal atomic layer deposited (ALD) aluminum oxide and hafnium oxide (ALD-HfO2) were used as the electron and hole blocking layers of the MISIM photodetectors for dark current suppression. A reduction in the dark current by three orders of magnitude can be achieved at electric fields between 10 and 30 V/μm. The effective dark current suppression is primarily ascribed to electric field lowering in the dielectric layers as a result of charge trapping in deep levels. Photogenerated carriers in the a-Se layer can be transported across the blocking layers to the Al electrodes via Fowler-Nordheim tunneling because a high electric field develops in the ultrathin dielectric layers under illumination. Since the a-Se MISIM photodetectors have a very low dark current without significant degradation in the photoresponse, the signal contrast is greatly improved. The MISIM photodetector with the ALD-HfO2 blocking layer has an optimal signal contrast more than 500 times the contrast of the photodetector without a blocking layer at 15 V/μm. [ABSTRACT FROM AUTHOR]

The interfacial chemical state and the band alignment of the sputtering-deposited CaF2/p-GaN hetero-structure were investigated by angle-resolved X-ray photoelectron spectroscopy. The dependence of Ga 3p core-level positions on the collection angles proves that the downward band bending of p-GaN is reduced from 1.51 to 0.85eV after the deposition of CaF2, which may be due to the reduction of Mg-Ga-O-related interface states by the oxygen-free deposition of CaF2. The band gap of sputtering-deposited CaF2 is estimated to be about 7.97eV with a potential gradient of 0.48eV obtained by the variation of the Ca 2p3/2 position on different collection angles. By taking into account the p-GaN surface band bending and potential gradient in the CaF2 layer, large valence and conduction band offsets of 2.66±0.20 and 1.92±0.20eV between CaF2 and p-GaN are obtained. These results indicate that CaF2 is a promising gate dielectric layer on the p-GaN for the application of metal-insulator-semiconductor devices. [ABSTRACT FROM AUTHOR]

Electron doped SrTiO3, a complex-oxide semiconductor, possesses novel electronic properties due to its strong temperature and electric-field dependent permittivity. Due to the high permittivity, metal/n-SrTiO3 systems show reasonably strong rectification even when SrTiO3 is degenerately doped. Our experiments show that the insertion of a sub nanometer layer of AlOx in between the metal and n-SrTiO3 interface leads to a dramatic reduction of the Schottky barrier height (from around 0.90V to 0.25 V). This reduces the interface resistivity by 4 orders of magnitude. The derived electrostatic analysis of the metal-insulator-semiconductor (n-SrTiO3) system is consistent with this trend. When compared with a Si based MIS system, the change is much larger and mainly governed by the high permittivity of SrTiO3. The non-linear permittivity of n-SrTiO3 leads to unconventional properties such as a temperature dependent surface potential non-existent for semiconductors with linear permittivity such as Si. This allows tuning of the interfacial band alignment, and consequently the Schottky barrier height, in a much more drastic way than in conventional semiconductors. [ABSTRACT FROM AUTHOR]

We assessed the effects of ultra dry-air plasma surface treatments on the properties of Al2O3-GPTMS-PMMA hybrid dielectric layers for applications to high-performance amorphous Indium Gallium Zinc Oxide (a-IGZO) thin film transistors (TFTs). The hybrid layers were deposited by an easy dip coating sol-gel process at low temperature and then treated with dry-air plasma at 1, 2 and 3 consecutive cycles. Their properties were analyzed as a function of the number of plasma cycles and contrasted with those of the untreated ones. The dielectric characteristics of the hybrid layers were determined from I–V and C–f measurements performed on metal–insulator–metal and metal–insulator–semiconductor devices. The results show that the plasma treatments increase the surface energy and wettability of the hybrid films. There is also a reduction of the OH groups and oxygen vacancies in the hybrid network improving the dielectric properties. The incorporation of nitrogen into the hybrid films surface is also observed. The plasma-treated hybrid dielectric layers were applied as dielectric gate in the fabrication of a-IGZO TFTs. The best electrical performance of the fabricated TFTs was achieved with the 3 cycles plasma-treated hybrid dielectric gate, showing high mobility, 29.3 cm2 V−1 s−1, low threshold voltage, 2.9 V, high ION/OFF current ratio, 106, and low subthreshold swing of 0.42 V dec−1. [ABSTRACT FROM AUTHOR]

We present an analysis method for GaN-based metal-insulator-semiconductor (MIS) devices by using capacitance-frequency-temperature (C-f-T) mapping to evaluate the gate-control efficiency and the interface state density, both exhibiting correlations with the linear-region intrinsic transcon-ductance. The effectiveness of the method was exemplified by application to AIN/AlGaN/GaN MIS devices to elucidate the properties of AIN-AlGaN interfaces depending on their formation processes. Using the C-f-T mapping, we extract the gate-bias-dependent activation energy with its derivative giving the gate-control efficiency, from which we evaluate the AIN-AlGaN interface state density through the Lehovec equivalent circuit in the DC limit. It is shown that the gate-control efficiency and the interface state density have correlations with the linear-region intrinsic transconductance, all depending on the interface formation processes. In addition, we give characterization of the AIN-AlGaN interfaces by using X-ray photoelectron spectroscopy, in relation with the results of the analysis. [ABSTRACT FROM AUTHOR]

We have systematically investigated low-frequency noise (LFN) in AlN/AlGaN/GaN metalinsulator- semiconductor (MIS) devices, where the AlN gate insulator layer was sputteringdeposited on the AlGaN surface, in comparison with LFN in AlGaN/GaN Schottky devices. By measuring LFN in ungated two-terminal devices and heterojunction field-effect transistors (HFETs), we extracted LFN characteristics in the intrinsic gated region of the HFETs. Although there is a bias regime of the Schottky-HFETs in which LFN is dominated by the gate leakage current, LFN in theMIS-HFETs is always dominated by only the channel current. Analyzing the channel-current-dominated LFN, we obtained Hooge parameters α for the gated region as a function of the sheet electron concentration ns under the gate. In a regime of small ns, both the MIS- and Schottky-HFETs exhibit α ∝ ns–1. On the other hand, in a middle ns regime of the MIS-HFETs, α decreases rapidly like ns–ξ with ξ~2-3, which is not observed for the Schottky- HFETs. In addition, we observe strong increase in α ∝ ns3 in a large ns regime for both the MIS- and Schottky-HFETs. [ABSTRACT FROM AUTHOR]

Implementation of new materials in Metal-Oxide-Semiconductor stacks requires capabilities to predict long-time degradation as well as the impact of process changes on degradation processes. In this work, the degradation under constant voltage stress of metal gate/Al2O3/InGaAs stacks is studied for different pre-dielectric deposition treatments. The results show that the degradation, particularly under negative bias, is strongly affected by the oxide-semiconductor surface treatment of the samples. Two contributions (interface states and bulk traps) dominate depending on the stress conditions. Surface treatment with NH4OH shows a better quality of the interface in term of interface states; however, it contributes to generation of positive charge on the dielectric layer. [ABSTRACT FROM AUTHOR]

This work presents the junction capacitance-voltage characteristics of highly textured/epitaxial Ni nanoparticle embedded in TiN matrix (TiN(Ni)) metal-insulator-semiconductor TiN(Ni)/SiO2/p-Si (100) heterojunction in the temperature range of 10-300 K. This heterojunction behaves as metal-semiconductor junction with unavoidable leakage through native oxide SiO2 layer. The clockwise hysteresis loop has been observed in the capacitance-voltage characteristics measured at various frequencies mainly due to presence of trap centers at the TiN(Ni)/SiO2 interface and these are temperature dependent. The spin-dependent trap charge effect at the interface influences the quadratic nature of the capacitance with magnetic field. The junction magnetocapacitance (JMC) is observed to be dependent on both temperature and frequency. The highest JMC of this heterojunction has been observed at 200 K at higher frequencies (100 kHz-1 MHz). It is found that there is not much effect of band structure modification under magnetic field causing the JMC. [ABSTRACT FROM AUTHOR]

Metal-insulator-semiconductor (MIS) structures were fabricated by depositing an Al2O3 dielectric on top of the contact layer of a mid-wave infrared nBn detector based on n-Hg1-xCdxTe grown by molecular beam epitaxy on GaAs (013) substrates. It is shown that when creating a backward electrode on the absorbing layer, the form of the capacitance–voltage characteristics depends not only on the properties of the contact layer, but also on the properties of the barrier and absorbing layers. An equivalent circuit of MIS structure based on nBn detector with mesa configuration is proposed. It is shown that measurements of the admittance of MIS structures with mesa configuration allow one to study the properties of the barrier layer in the nBn structure. The influence of infrared radiation on the temperature dependence of the barrier layer resistance is studied. [ABSTRACT FROM AUTHOR]

New high- k gate dielectrics are highly necessary in facilitating the continuous down-scaling of metal–oxide–semiconductor devices to the sub-10 nm range. This study presents ultrathin organic hydrocarbon (HC) films as a novel high- k gate insulator for metal–insulator–semiconductor (MIS) devices. During inductively-coupled plasma chemical vapor deposition with CH 4 and H 2 gases, the growth temperature greatly affects the structure of the carbon layers and consequently their dielectric characteristics. Specifically, sp 2-rich dielectric HC layers are formed below 600 °C, whereas highly-ordered sp 2-hybridized graphene is formed at 950 °C. The k value of the resulting HC films increases up to a maximum value of 90 at 350 °C. Moreover, the MIS devices exhibit excellent gate-insulating properties, including almost no hysteresis in the capacitance–voltage curve, low leakage current, and high dielectric strength, which surpass those of existing high- k gate oxides. These results reveal that the organic HC films are a promising next-generation high- k gate dielectric material for sub-10 nm node Si and organic semiconductor technologies. Image 1 • Synthesis of high- k (up to 90) hydrocarbon films by chemical vapor deposition. • Excellent gate dielectric properties superior to current high- k gate oxides. • Promising as a gate dielectric for next-generation Si MOS technologies. [ABSTRACT FROM AUTHOR]

In this work, a novel GaN MIS‐HEMT (metal‐insulator‐semiconductor high electron mobility transistors) featuring a floating clamp (FC) electrode is proposed for suppressing the short‐channel effect. By inserting the FC electrode near to the drain‐side gate edge, the transverse potential at the gate edge can be clamped to less than 2 V, thereby the short‐channel effect can be suppressed. Compared to the conventional short‐channel GaN MIS‐HEMT, the proposed device exhibits much decreased off‐state electron density at the drain voltage of 10 V, which leads to the off‐state leakage current decreasing from 10–1 to 10–7 A/mm, without an obvious sacrifice of the on‐state current. Meanwhile, the proposed GaN MIS‐HEMT also delivers a much lower reverse gate‐to‐drain capacitor. The excellent characteristics of the proposed GaN MIS‐HEMT show that the device is promising for the future power applications. [ABSTRACT FROM AUTHOR]

Metal Insulator Semiconductor (MIS) capacitors are commonly used as a test structure for characterization of semiconductor/insulator interface. However, MIS devices do not provide useful information in strong accumulation or inversion mode as the capacitance saturates to a constant value. An MIS capacitor with area asymmetry on the other hand, exhibits a gate voltage dependent capacitance in strong accumulation mode and can be used to obtain additional useful information about the semiconductor/insulator interface. The present work describes the use of asymmetrical metal–insulator–semiconductor device for characterization of the threshold voltage in metal–insulator–organic test structures. Simulation results are presented to show that the threshold voltage extracted from these devices not only matches with that extracted from current–voltage characteristics of organic thin film transistors in the linear region but is also much less sensitive to source contact resistance. The experimental results obtained with pentacene as active semiconductor and poly-vinyl-phenol as the dielectric are also presented to demonstrate the operation and merits of the proposed technique. [ABSTRACT FROM AUTHOR]

Co-doped Si-NCs have been introduced into MIS structures gate dielectric layers. The fabricated test devices were characterized by means of stress-and-sense measurements in terms of device capacitance, flat-band voltage shift, and retention time. Comparison between results for HfO x and SiO 2 gate dielectric layers is shown and discussed. Presented findings are promising for possible applications of Si-NCs in memory structures. [ABSTRACT FROM AUTHOR]

• Charge trapping effects are considered as one of the most severe reliability issues in GaN/AlGaNMIS-HEMTs. • Thus, the identification of the origin and the physical properties of active defects is one of the key factors to improve the stability of GaN technology. • In this work, we suggest two neighboring nitrogen vacancies as the origin of correlated random telegraph noise (RTN) emissions in a GaN/AlGaN fin-MIS-HEMT. • Electrostatic coupling between these two defects is calculated using three different approaches and the results are verified using a Hidden Markov Model (HMM). Charge trapping effects are considered as one of the most severe reliability issues in gallium nitride (GaN)/aluminium gallium nitride (AlGaN) metal-insulator-semiconductor HEMTs (MISHEMTs). Thus, the identification of the origin and the physical properties of active defects is one of the key factors to improve the stability of GaN technology. In this work, we suggest two neighboring nitrogen vacancies as the origin of correlated random telegraph noise (RTN) emissions in a GaN/AlGaN fin-MISHEMT. We determine the magnitude of electrostatic coupling between these two defects by using three different approaches and verify the results by simulating the RTN emissions of a similar system using a Hidden Markov Model (HMM). [ABSTRACT FROM AUTHOR]

Various applications of quantum devices call for an accurate calibration of cryogenic amplification chains. To this end, we present an experimentally feasible calibration scheme and use it to accurately measure the total gain and noise temperature of an amplification chain by employing normal-metal–insulator–superconductor (NIS) junctions. Our method is based on the radiation emitted by inelastic electron tunneling across voltage-biased NIS junctions. We derive an analytical expression that relates the generated power to the applied bias voltage which is the only control parameter of the device. After the setup has been characterized using a standard voltage reflection measurement, the total gain and the noise temperature are extracted by fitting the analytical expression to the microwave power measured at the output of the amplification chain. The 1σ uncertainty of the total gain of 51.84 dB appears to be of the order of 0.10 dB. [ABSTRACT FROM AUTHOR]

Abstract: The influence of electric field and current flow on the current-voltage (I-V) characteristics of TlGaSe2 layered semiconductor was investigated by using a two-point probe measurement system. Threshold-type switching in I-V characteristics associated with current-controlled memory effect was observed in all investigated samples. Observed switching characteristic is close to the most experimentally realizable memristive systems. Experimental findings were analyzed by using a model of metal-insulator-semiconductor-insulator-metal (MISIM) structure having memristive behavior. [ABSTRACT FROM AUTHOR]

A novel early gate dielectric AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs) process is reported. With the high-quality Si3N4 dielectric by low-pressure chemical vapor deposition and damage free, self-terminating passivation layer etching at the gate area, the MIS-HEMTs on 150-mm Si substrate demonstrate excellent output performance and good uniformity. The interface trap density between the gate insulator and the barrier layer is as low as $2 \times 10^{{12}}{\mathrm {cm}}^{- {2}}\,\,\cdot \,\,{\mathrm {eV}}^{- {1}}$ extracted by the conductance method. The MIS-HEMT fabricated on the wafer delivers an extremely small gate leakage current of 10−9 mA/mm and a high ${I}_{\mathrm{\scriptscriptstyle {ON}}}/{I}_{{\mathrm{\scriptscriptstyle {OFF}}}}$ ratio of 1011. The subthreshold swing (SS) is around 80 mV/dec, and the saturated output current density is 750 mA/mm. The dynamic on-resistance increases about 42% at a quiescent drain bias of 600 V. The ${V}_{ {th}}$ shift is −0.63 and −0.89 V at a high temperature of 200 °C and negative gate-bias stress of −25 V, respectively, indicating a comparable stability with the state-of-the-art MIS-HEMTs. An excellent threshold voltage and SS uniformity ($ {1} - \sigma /\mu)$ with the value of 94.5% and 95.2% are achieved on the 150-mm wafer. [ABSTRACT FROM AUTHOR]

Abstract: In this work, the ATOM (intrinsic a‐Si:H/TiOx/low work function metal) structure is investigated to realize high‐performance passivating electron‐selective contacts for crystalline silicon solar cells. The absence of a highly doped Si region in this contact structure is meant to reduce the optoelectrical losses. We show that a low contact resistivity (ρc) can be obtained by the combined effect of a low work function metal, such as calcium (Φ 2.9 eV), and Fermi‐level depinning in the metal‐insulator‐semiconductor contact structure (where in our case TiOx acts as the insulator on the intrinsic a‐Si:H passivating layer). TiOx grown by ALD is effective to achieve not only a low ρc but also good passivation properties. As an electron contact in silicon heterojunction solar cells, inserting interfacial TiOx at the i‐a‐Si:H/Ca interface significantly enhances the solar cell conversion efficiency. Consequently, the champion solar cell with the ATOM contact achieves a VOC of 711 mV, FF of 72.9%, JSC of 35.1 mA/cm2, and an efficiency of 18.2%. The achievement of a high VOC and reasonable FF without the need for a highly doped Si layer serves as a valuable proof of concept for future developments on passivating electron‐selective contacts using this structure. [ABSTRACT FROM AUTHOR]

Metal-insulator-semiconductor devices having different oxide thicknesses (10, 6, 4 and 2 nm) were fabricated using atomic-layer deposited ultra-thin amorphous TiO2 as gate dielectric. From Ig-Vg measurements it was determined that the main conduction mechanism is Schottky emission for all thicknesses and even after passivation of the semiconductor-insulator interface using SiOx. Furthermore, the Schottky barrier height (ΦB) increases when the oxide thickness decreases; this was further corroborated using semi empirical models and SILVACO simulations having excellent agreement. From this analysis, important physical parameters like barrier height (ΦB), effective mass (m*) and optical dielectric constant (εr) were extracted, and could be used to effectively understand the performance and reliability of these devices. From the extraction of physical parameters associated to the conduction mechanism, a correlation between materials’ properties with device performance could be obtained (higher barrier height (ΦB) would result in a decrease in leakage current). Also, the high reproducibility enables enhanced performance and therefore, better reliability predictions for electron devices based on these oxides. [ABSTRACT FROM AUTHOR]

The effects of proton irradiation energy on the electrical properties of SiNx/AlGaN/GaN metal-insulator semiconductor high electron mobility transistors (MISHEMTs) using in situ grown silicon nitride as the gate dielectric were studied. The SiNx/AlGaN/GaN MISHEMT devices were irradiated with protons at energies of 5, 10, or 15 MeV at a fixed fluence of 2.5 × 1014 cm−2. The largest amount of device degradation was shown in the samples irradiated with the lowest irradiation energy of 5 MeV. The DC saturation current was reduced by 10.4%, 3.2%, and 0.5% for MISHEMTs irradiated with proton energies of 5, 10, and 15 MeV, respectively. Device performance degradation was more pronounced in the irradiated samples under high-frequency operation. At a frequency of 100 kHz, the percent saturation drain current reduction at a gate voltage of 3 V was 40%, 19%, and 17% after proton irradiation at 5, 10, and 15 MeV, respectively. The carrier removal rates for the MISHEMT devices were in the range of 21–144 cm−1 for the proton irradiation energies studied. The measured DC degradation and carrier removal rates are lower than the values reported for AlGaN/GaN metal-gate high electron mobility transistor devices irradiated at similar conditions, which can be attributed to the SiNx insulating layer reducing the total damage on the AlGaN surface. [ABSTRACT FROM AUTHOR]

In this study, a Ti/Al/W ohmic contact and the factors that determine the optimal annealing temperature are investigated to obtain Au‐free high‐electron mobility transistor (HEMT) with a low thermal budget. The results show that a thin‐Ti layer of 2.7 nm with a low specific contact resistance of 2.54 × 10−6 Ω · cm2 (0.358 Ω mm) is realized in 10 min at a low annealing temperature of 500 °C. It is found that a thinner Ti layer leads to a lower annealing temperature because Al needs to diffuse through the Ti layer and make contact with AlGaN to obtain linear I–V characteristics. In addition, Ti is essential in removing the natural oxide film on AlGaN surface, and the minimum thickness of the Ti layer is 2 nm. The Au‐free AlGaN/GaN HEMT on a silicon wafer shows comparable characteristics with the conventional Au‐containing HEMT, which leads to low cost manufacturing of HEMTs in existing silicon‐device fabrication lines. [ABSTRACT FROM AUTHOR]

In this letter, we investigated the threshold voltage V\text {TH} stability under reverse-bias step-stress in the E-mode LPCVD-SiNx/PECVD-SiNx/GaN MIS-FET. Under the OFF-state reverse-bias stress with the same net gate-to-drain voltage ( V\text {GD} ), the V\text {TH} shift shows an obvious dependence on the negative gate bias. With a V\text {GS} of 0 V, the V\text {TH} shift is small and recoverable, while the V\text {TH} shifts are substantially larger with more negative gate bias ( V\text {GS}=-20 V). This larger V\text {TH} shifts caused by the negative V\text {GS} can be explained with a hole-induced degradation model. An important indication revealed by this model is that negative gate bias should be well confined in high-power switching applications of GaN E-mode MIS-FET for a stable V\text {TH} . [ABSTRACT FROM PUBLISHER]

In this work, we have fabricated low-temperature sol-gel spin-coated and oxygen (O) plasma treated ZrO thin film-based metal-insulator-semiconductor devices. To understand the impact of plasma treatment on the Si/ZrO interface, deep level transient spectroscopy measurements were performed. It is reported that the interface state density ( D ) comes down to 7.1 × 10 eV cm from 4 × 10 eV cm, after plasma treatment. The reduction in D is around five times and can be attributed to the passivation of oxygen vacancies near the Si/ZrO interface, as they try to relocate near the interface. The energy level position ( E ) of interfacial traps is estimated to be 0.36 eV below the conduction band edge. The untreated ZrO film displayed poor leakage behavior due to the presence of several traps within the film and at the interface; O plasma treated films show improved leakage current density as they have been reduced from 5.4 × 10 A/cm to 1.98 × 10 A/cm for gate injection mode and 6.4 × 10 A/cm to 6.3 × 10 A/cm for substrate injection mode at 1 V. Hence, we suggest that plasma treatment might be useful in future device fabrication technology. [ABSTRACT FROM AUTHOR]

In this work, the fabrication and characterization of fully solution-processed flexible Metal-Insulator-Semiconductor (MIS) diodes are presented. The MIS structure was fabricated using aluminum doped zinc oxide and spin-on glass as semiconductor and insulator, respectively. The maximum temperature used was 200 °C. The electrical characteristics of the flexible devices show a good agreement with the typical characteristics of a semiconductor diode even while bent to 5 mm tensile radius. [ABSTRACT FROM AUTHOR]

The characteristics of a MIS varicap with charge transfer designed for control microwave devices are analyzed. The limiting frequency of the device is shown to be at least twice as high as that of the standard MIS varicap based on a MIS system with a thicker dielectric in the varicap with charge transfer. A method for parameter measurements in the microwave range is developed. Some device samples are fabricated based on thin substrates of monocrystalline silicon with epitaxial layers. The correspondence between the theoretical and experimental characteristics of the varicap is established. [ABSTRACT FROM AUTHOR]

Device-quality crystallographically oriented epitaxial (100)Ge and (110)Ge were grown on GaAs substrates using a large bandgap AlAs buffer. Electrical characteristics of p-type metal-oxide-semiconductor (pMOS) capacitors, fabricated from the aforementioned material stacks, are presented for the first time. High-resolution cross-sectional transmission electron microscopy analysis demonstrated atomically abrupt heterointerfaces between Al2O3/Ge as well as Ge/AlAs for both (100) and (110) orientations. Various process conditions were implemented during MOS capacitor fabrication to study their impact on the Al2O3/Ge interface. The fabricated pMOS devices demonstrated excellent electrical characteristics with efficient modulation of the Fermi level from midgap to the conduction band edge, corresponding to a minimum Dit value of 1.2 × 1011 cm-2·ev-1 on (100)Ge, indicative of a high-quality oxide/Ge heterointerface, and an effective electrical passivation of the Ge surface. Postdeposition annealing under O2 was found to be less effective at reducing oxide trap density (NOT) as compared to forming gas or O2 postmetallization anneals (PMA), indicating that metal-induced bandgap states at the gate metal/dielectricinterface have a notable impact on Ge pMOS NOT. On the other hand, a tradeoff must be made between NOT and the equivalent oxide thickness when performing PMA under O2 or forming gas ambient. [ABSTRACT FROM PUBLISHER]

Electrical properties of epitaxial La 2 O 3 /germanium (Ge) structures can be significantly improved by using epitaxially grown Lutetium(Lu)- or Yttrium(Y)-doped La 2 O 3 passivation layers. For the metal-insulator-semiconductor (MIS) devices, hysteretic nature of capacitance-voltage ( C - V ) characteristics becomes negligibly small and the interface trap density ( D it ) is estimated to be less than 10 12 cm −2 eV −1 at around the midgap. We discuss a possible mechanism of the improvement of the electrical properties. [ABSTRACT FROM AUTHOR]

TCAD simulation is calibrated to experimental I D V D , I D V G and f T data from an H-terminated diamond MISFET from the literature. With one set of self-consistent parameters, experimental data are all well matched. In the calibration process, TCAD is used to study the possible cause of current degradation in some of the devices fabricated in the same process and it is conjectured that the degradation of low field mobility of the two-dimensional hole gas (2DHG) under the gate is the main cause of current degradation. With the calibrated parameters, a highly scaled MISFET is simulated and it is predicted that with the given fabrication process, one can achieve f T > 100 GHz if the gate length can be scaled down to ~ 0.1 μm. [ABSTRACT FROM AUTHOR]

Heterostructures based on n-Hg 1-x Cd x Te (x = 0.23–0.40) with near-surface graded-gap layers were grown by molecular beam epitaxy on Si (013) substrates. At 77 K, the admittance of the In/Al 2 O 3 /Hg 1-x Cd x Te metal-insulator-semiconductor (MIS) structures with grown in situ CdTe intermediate layer and without such a layer was investigated. It has been established that MIS structures of In/Al 2 O 3 /Hg 1-x Cd x Te with an interlayer of in situ grown CdTe are characterized by the electrical strength of the dielectric and the qualitative interface. The hysteresis of the capacitive characteristics is practically absent within a small range of variation in the bias voltage. The density of fast surface states at the minimum does not exceed 2.2 × 10 10 eV −1 cm −2 . MIS structures of In/Al 2 O 3 /Hg 1-x Cd x Te without an intermediate layer of CdTe have significantly higher densities of fast and slow surface states, as well as lower values of the differential resistance of the space-charge region in the regime of strong inversion. [ABSTRACT FROM AUTHOR]

In this paper, a new current-mode precision full-wave rectifier is presented. The proposed circuit employs a single active element namely extra-X current conveyor and two NMOS transistors without using any passive element which is suitable for IC implementation. The circuit exhibits low input impedance and high output impedance, so it is easily cascadable. The non-idealities and the parasitics effects on the circuit are also discussed. The detailed Monte Carlo analysis and distortion study is also carried out along with supporting results. The functionality of the proposed current-mode precision full-wave rectifier is verified through PSPICE simulation using 0.25 $$\upmu \hbox {m}$$ TSMC CMOS technology parameters. The proposal is also supported by experimental result. [ABSTRACT FROM AUTHOR]

A novel topology for realizing voltage-mode (VM) full-wave rectifier/sinusoidal frequency doubler based on current feedback operational amplifiers (CFOAs) and n-channel metal-oxide semiconductor (NMOS) transistors is proposed in this study. The proposed full-wave rectifier structure employs two CFOAs and three enhancement-mode NMOS transistors. With a slight modification, the sinusoidal frequency doubler circuit can be adopted from the full-wave rectifier circuit by replacing a grounded resistor instead of one of the NMOS transistors. Both of the proposed circuits enjoy low output and high input impedance properties which make them convenient for cascading easily with other VM circuits without needing any extra buffer circuits. No passive component matching conditions are needed. The proposed circuits are simulated by using SPICE program to verify the theoretical analysis. [ABSTRACT FROM AUTHOR]

The effect of a 2D graphene layer (GL) on top of the silicon nitride (SiN) passivation layer of AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors has been systematically analyzed. Results showed that in the devices without the GL, the maximum drain current density ( \textI\text {D,max} ) and the maximum transconductance ( \textg\text {m,max} ) decreased gradually as the mist exposure time increased, up to 23% and 10%, respectively. Moreover, the gate lag ratio increased around 10% during mist exposure. In contrast, devices with a GL showed a robust behavior and not significant changes in the electrical characteristics in both dc and pulsed conditions. The origin of these behaviors has been discussed and the results pointed to the GL as the key factor for improving the moisture resistance of the SiN passivation layer. [ABSTRACT FROM AUTHOR]

Even though the introduction of high-dielectric constant (high-κ) materials has enabled the continuous advancement of Moore's Law into the nanometer regime, accurate predictions ensuring long-term operation of these devices is now more complicated due to several physical and electronic considerations: 1) precise atomic control of the high-k material in the ultra-thin regime (thickness, stoichiometry, dielectric constant, etc.), 2) excessively large gate leakage currents, 3) appearance of several conduction mechanisms able to degrade the performance and reliability of the devices, 4) interfacial defects at the high-k/silicon interface and 5) low thermodynamic stability of the high-k materials after exposure to inherent thermal treatments during several processing stages. In order to provide better device performance/reliability predictions, this work offers a consistent and accurate verification of the precise carrier conduction mechanisms of Metal-Insulator-Semiconductor (MIS) capacitors (biased under substrate injection conditions) when ultra-thin Al 2 O 3 films (5 and 10 nm in thickness and deposited by thermal atomic-layer deposition) are used as the gate oxide before and after a post-metallization annealing in a H 2 /N 2 atmosphere. From experimental Current-Voltage data of these MIS devices, along with the use of SILVACO simulations and well established semi-empirical models, the precise conduction mechanisms as well as important physical and electronic parameters (consistent with the conduction models) were extracted. We show that even though an H 2 -based anneal is able to passivate silicon dangling bonds, gate leakage current for Al 2 O 3 increases while keeping the same conduction models thus offering clues for better reliability predictions before failure. [ABSTRACT FROM AUTHOR]

GaN field-effect transistors with impressive power switching characteristics have been demonstrated. Preventing their widespread field deployment are reliability and instability concerns. Some emanate from the use of a dielectric in the gate stack. Under typical operation, the gate dielectric comes periodically under intense electric field. This causes trapping and detrapping of electrons and introduces transient shifts in the threshold voltage, a phenomenon known as Bias-Temperature Instability (BTI). A high electric field also results in the formation of defects inside the dielectric. Over time, the defects accumulate and eventually result in the abrupt creation of a conducting path that shorts the dielectric and renders the device inoperable. This process, known as Time-Dependent Dielectric Breakdown (TDDB), often imposes a maximum lifetime for the FET technology. This article presents a methodology for the study of BTI and TDDB in insulated-gate GaN FETs. Our findings paint a picture of BTI and TDDB that in many respects is similar to that of Si transistors but with some unique characteristics. Understanding the physics and developing appropriate lifetime models is essential to enabling the deployment of this important new power electronics technology. [ABSTRACT FROM AUTHOR]

The impact of states at the Al 2 O 3 /Si interface on the capacitance-voltage C-V characteristics of a metal/insulator/semiconductor heterostructure (MIS) capacitor was studied by a numerical simulation, by solving Schrodinger-Poisson equations and taking the electron emission rate from the interface state into account. Efficient computation and accurate physics based capacitance model of MOS devices with advanced ultra-thin equivalent oxide thickness ( EOT ) (down to 2.5 nm clearly considered here) were introduced for the near future integrated circuit IC technology nodes. Due to the importance of the interface state density for a low dimension and very low oxide thickness, a high frequency C-V model has been developed to interpret the effect of interface state density traps which communicate with the Al 2 O 3 /Si and their influence on the C-V characteristics. We found that these states are manifested by jumping capacity in the inversion zone, for a density of interface, higher than 1 × 10 11 cm − 2 eV − 1 during a p-doping of 1 × 10 18 cm − 3 . This behavior has been investigated with various doping, temperature, frequency and energy levels on the C-V curves, and compared with the MIS structure that contains a standard SiO 2 insulator. [ABSTRACT FROM AUTHOR]

We report on the stabilization of the ferroelectric phase in Hf0.8Zr0.2O2 with a tungsten capping layer. Ferroelectricity is obtained in both metal-insulator-metal (MIM) and metal-insulatorsemiconductor (MIS) capacitors with highly-doped Si serving as the bottom electrode in the MIS structure. Ferroelectricity is confirmed from both the electrical polarization-voltage (P-V) measurement and X-Ray Diffraction analysis that shows the presence of an orthorhombic phase. Highresolution Transmission Electron Microscopy and Energy Dispersive X-ray spectroscopy show minimal diffusion of W into the underlying Hf0.8Zr0.2O2 after the crystallization anneal. This is in contrast to significant Ti and N diffusion observed in ferroelectric HfxZr1-x-O2 commonly capped with TiN. [ABSTRACT FROM AUTHOR]