Effect of interface traps for ultra-thin high-k gate dielectric based MIS devices on the capacitance-voltage characteristics.

The impact of states at the Al 2 O 3 /Si interface on the capacitance-voltage C-V characteristics of a metal/insulator/semiconductor heterostructure (MIS) capacitor was studied by a numerical simulation, by solving Schrodinger-Poisson equations and taking the electron emission rate from the interface state into account. Efficient computation and accurate physics based capacitance model of MOS devices with advanced ultra-thin equivalent oxide thickness ( EOT ) (down to 2.5 nm clearly considered here) were introduced for the near future integrated circuit IC technology nodes. Due to the importance of the interface state density for a low dimension and very low oxide thickness, a high frequency C-V model has been developed to interpret the effect of interface state density traps which communicate with the Al 2 O 3 /Si and their influence on the C-V characteristics. We found that these states are manifested by jumping capacity in the inversion zone, for a density of interface, higher than 1 × 10 11 cm − 2 eV − 1 during a p-doping of 1 × 10 18 cm − 3 . This behavior has been investigated with various doping, temperature, frequency and energy levels on the C-V curves, and compared with the MIS structure that contains a standard SiO 2 insulator. [ABSTRACT FROM AUTHOR]