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We demonstrated the crystal growth of group-III arsenides (III-As) on GaN via an arsenidation layer and GaN-channel electron mobility transistors (HEMTs) with a regrowth InAs/GaAs source and drain (S/D) region. By annealing under an AsH3 atmosphere, the surface of a GaN (0001) template is arsenided. We grew ⟨ 111 ⟩ oriented InAs and GaAs on arsenided GaN. Silicon-doped n-type InAs with a carrier mobility of over 1500 cm2/V s and a carrier concentration of over 1 × 1019 cm−3 was successfully obtained. The fabrication process and direct-current characteristics of GaN-channel HEMTs with the regrown Si-doped InAs/GaAs S/D region were demonstrated for the first time. A maximum transconductance estimated from transfer characteristics was as high as ∼195 mS/mm for the HEMT with a gate length of 2 μm without passivation, which is comparable to those for the HEMT without any S/D regrowth. The impact of the InAs/GaAs S/D region on the on-resistance of the fabricated HEMTs was estimated to be ∼0.9 Ω mm, which can be reduced by optimizing the device structures and process conditions. These results indicate that the process of GaN arsenidation and III-As regrowth can be used without any device performance degradation. Therefore, further lowering the ohmic contact resistivity and on-resistance of GaN-channel HEMTs is possible by maturing the manufacturing-process technology of III-As-contained GaN-channel HEMTs. [ABSTRACT FROM AUTHOR]

A comprehensive quantitative root cause study of defect evolution leading to memory window closure from a charge balance and charge trapping perspective throughout all phases of a Si channel Hf0.5Zr0.5O2 (HZO) ferroelectric field-effect-transistor (FEFET) is reported. Starting with the first write pulse, an excessive SiO2 interlayer field is revealed that triggers the creation of defect levels Dit in excess of 1015 cm−2 eV−1 at the HZO–SiO2 interface screening ferroelectric (FE) polarization while enabling FE switching. Under subsequent early bipolar fatigue cycling (up to 104 cycles), defect creation commences at the SiO2–Si interface due to the high injected hole fluence (0.39 C/m2) during each stress pulse causing negative bias instability (NBI), which shifts the threshold voltage of the erase state VT,ERS by −0.3 V with accrual of permanently captured charge Nit of up to +5 × 10−3 C/m2 (3 × 1012 cm−2). Subsequently, Nit NBI generation at the SiO2–Si interface accelerates reaching levels of +7 × 10−2 C/m2, locking both FEFET program and erase drain current vs gate–source-voltage (ID–VGS) characteristics in the FEFET on-state inducing memory window closure at 105 cycles while FE switching (switched polarization Psw = 0.34 C/m2) remains essentially intact. These findings guide the down-selection toward suitable semiconductor/FE systems for charge balanced, reliable, and high endurance FEFETs. [ABSTRACT FROM AUTHOR]

This paper presents a metal–insulator–semiconductor high-electron-mobility transistor (MIS-HEMT) device, operating in enhancement mode, with a double-channel triple-barrier (DCTB) Al0.15Ga0.85N/GaN/Al0.07Ga0.93N/GaN/Al0.05Ga0.95N device structure. Initially, we simulate the Al0.15Ga0.85N/GaN single-channel single-barrier (SCSB) MIS-HEMT, featuring a T-gate design that offers a significant gap between the gate and a drain electrode, resulting in a high breakdown voltage (VBD) and low parasitic capacitance, enhancing cut-off frequency (ft) and a maximum frequency of oscillation (fmax). In the current era, high breakdown voltage, high current drive, and high-frequency enhancement-mode-operated devices are needed for power switching circuits and high-frequency power amplifier applications. To meet these requirements, we propose a DCTB MIS-HEMT device structure that adds additional back-barrier layers and channel layers to form a double-hump characteristic due to the interaction between two-dimensional electron gas (2DEG) accumulation layers and the electric field across the device. We optimize the devices with an optimistic doping profile in channel and buffer layers, a field plate, recessed gate structure, and control the barrier layers thickness, ensuring enhancement-mode operation. Numerical simulations of the DCTB device provide high drain current (Ids) of 1.5 A/mm, transconductance (gm) of 0.232 S/mm, threshold voltage (Vt) of 2.8 V, VBD of 633.1 V, ON resistance (RON) of 6.074 Ω mm, ft of 49.8 GHz, and fmax of 107.8 GHz. Due to improvements in these parameters, the DCTB MIS-HEMT outperforms the SCSB MIS-HEMT, making it suitable for high-current drive, high-frequency, and high-speed switching applications. In this work, we also examine the merits of utilizing DCTB MIS-HEMT as the switching element in an ultra-low-loss boost converter circuit. [ABSTRACT FROM AUTHOR]

In this paper, a successful electric field modulation in Lateral Double-diffused Metal Oxide Semiconductor (LDMOS) transistors to enhance the electrical characteristics is presented. A β-Ga2O3 film in the drift region is incorporated. The β-Ga2O3 film leads to a more efficient electric field modulation and enhances the DC and RF capabilities. Also, a Silicon layer is embedded in the buried oxide of the proposed structure to improve self-heating effects. Overall, the proposed β-Ga2O3 film in SOI LDMOS (βF-LDMOS) structure offers improved performances in terms of electric field distribution, maximum available power gain, unilateral power gain, gate-drain capacitance, breakdown voltage, and maximum lattice temperature. This makes it a promising candidate for RF power applications requiring high voltage and high power handling capabilities. [ABSTRACT FROM AUTHOR]

This study investigates symmetrical/asymmetrical vertical electrolyte‐insulated semiconductor Tunnel field effect transistors (TFETs) (SV‐EIS‐TFET/ASV‐EIS‐TFET) for their application as pH biosensors. On the basis of device‐level simulations, the underlying physics of all architectures is explored and the comparative biosensing abilities of pH biosensors are evaluated. A vertical electrolyte Bio‐TFET with overlapping electrodes is presented in this study. The pH response is measured by observing the change in drain current and potential when the pH of the injected solution transitions from a lower to a higher level. As an intrinsic semiconductor material, electrons and holes in the electrolyte represent mobile ions in the solution. The region of the electrolyte has an electron affinity of 1.32 eV, a bandgap of 1.12 eV, and a dielectric constant of 78. Double gate structures raise concerns about correctly aligning the right and left gates because of their sensitivity impact. An analysis of the effect of gate misalignment on biosensor surface potentials, drain currents, and transconductance is presented. Furthermore, pH value ranges of 1–14 are considered for various sensitivity parameters. Simulations are performed using Silvaco TCAD for the SV‐EIS‐TFET and ASV‐EIS‐TFET biosensors. [ABSTRACT FROM AUTHOR]

AgGaTe2 is an attractive material for the light‐absorbing layer in solar cells and has been deposited by close‐spaced sublimation using Ga2Te3 powder source. However, the samples exhibit an excess of Te, as well as undesired Mo–Te compounds, when AgGaTe2 is deposited on Mo/glass substrates. Therefore, the AgGaTe2 light‐absorbing layer is deposited using an Ag2Te and GaTe mixed powder source and examined herein. By replacing the Ga2Te3 source with GaTe, the Te content confirmed by the X‐ray fluorescent has significantly decreased. Cross‐sectional transmission electron microscopy observation indicates that the formation of Mo–Te compounds is suppressed. This is because Ga2Te3 produces additional Te gas in the initial decomposition reaction during deposition, and GaTe does not. In addition, the J–V curves show an improved conversion efficiency for solar cells fabricated using GaTe. [ABSTRACT FROM AUTHOR]

This study explores the impact of integrating a gallium arsenide (GaAs) pocket at the source and drain in a dual‐material gate‐oxide‐stack double‐gate tunnel field‐effect transistor (DMGOSDG‐TFET). The performance of this DMGOSDG‐TFET, employing work‐function engineering and gate‐oxide‐stack techniques, is compared with a GaAs pocket‐doped DMGOSDG‐TFET. Using the Silvaco Technology Computer‐Aided Design tool, the comparison covers DC characteristics, analog/RF behavior, and circuit‐level assessments. The research introduces an optimized heterostructure pocket‐doped DMGOSDG‐TFET to enhance DC characteristics, analog/RF performance, and DC/transient analysis. This novel architecture effectively suppresses ambipolarity, making it more suitable for current conduction. The incorporation of work‐function engineering and a gate‐oxide‐stack approach enhances the device's current driving capability, while the use of a highly doped GaAs pocket at the source and drain virtually eliminates ambipolar current conduction. Simulation results indicate that the proposed heterostructure device exhibits a high ON‐current and switching ratio. For analog/RF applications, the optimized heterostructure device outperforms conventional DMGOSDG‐TFET, offering higher cutoff frequency, transconductance, and other analog/RF parameters. Circuit‐level performance is assessed using HSPICE, with a focus on the implementation of a resistive‐load inverter for both proposed and conventional device topologies through DC and transient evaluations. [ABSTRACT FROM AUTHOR]

Hyperspectral scanning capacitance microscopy (SCM) measures d C / d V − V spectra at every XY location of a semiconductor sample surface area. We report its application to GaN-based high electron mobility transistor (HEMT) structures to map threshold voltage (Vth) at the nanoscale. The consistency between the conventional SCM data and the hyperspectral SCM data set of the same area on the HEMT surface provides evidence for the reliability of hyperspectral SCM. We developed a method to extract a map of Vth distribution across the surface of the HEMT structure at the nanoscale from the hyperspectral SCM data set. The map reveals that most of the fissures (i.e., enlarged pits formed at threading dislocation surface endings) on the nitride sample surface reduce local Vth. Other variations in Vth in regions free of the fissures could be a result of thickness and/or composition inhomogeneities in the Al x Ga 1 − x N barrier layer. Conventional SCM and other techniques cannot provide these detailed insights obtained through hyperspectral SCM. [ABSTRACT FROM AUTHOR]

A novel high-speed and process-compatible carrier-stored trench-gate bipolar transistor (CSTBT) combined with split-gate technology is proposed in this paper. The device features a split polysilicon electrode in the trench, where the left portion is equipotential with the cathode. This design mitigates the impact of the anode on the trench gate, resulting in a reduction in the gate-collector capacitance (CGC) to improve the dynamic characteristics. On the left side of the device cell, the P-layer, the carrier-stored (CS) layer and the P-body are formed from the bottom up by ion implantation and annealing. The P-layer beneath the trench bottom can decrease the electric field at the bottom of the trench, thereby improving breakdown voltage (BV) performance. Simultaneously, the highly doped CS layer strengthens the hole-accumulation effect at the cathode. Moreover, the PNP doping layers on the left form a self-biased pMOS. In a short-circuit state, the self-biased pMOS turns on at a certain collector voltage, causing the potential of the CS-layer to be clamped by the hole channel. Consequently, the short-circuit current no longer increases with the collector voltage. The simulation results reveal significant improvements in comparison with the conventional CSTBT under the same on-state voltage (1.48 V for 100 A/cm2). Specifically, the turn-off time (toff) and turn-off loss (Eoff) are reduced by 38.4% and 41.8%, respectively. The short-circuit current is decreased by 50%, while the short-circuit time of the device is increased by 2.46 times. [ABSTRACT FROM AUTHOR]

This paper proposes and investigates a novel 4H‐SiC trench MOSFET (TMOS) with integrated high‐K deep trench and gate dielectric (INHK‐TMOS). The integrated high‐K (INHK) consists of a high‐K gate dielectric and an extended high‐K deep trench dielectric in the drift region. Firstly, the high‐K gate dielectric together with the metal‐forming high‐K metal gate structure, which increases the gate oxide capacitance (COX), reduces the threshold voltage (VTH) and the specific on‐resistance (Ron,sp). Secondly, the extended high‐K deep trench dielectric not only modulates the electric field in the drift region by introducing a new electric field peak at the bottom of the high‐K deep trench dielectric, thereby enhancing the breakdown voltage (BV), but also improves the doping concentration (ND) of the drift region by the assist depletion effect of the high‐K dielectric, further optimizing the forward conduction characteristics. Simulation results demonstrate that when compared to the conventional TMOS, the INHK‐TMOS using HfO2 exhibits a 52.6% reduction in VTH, a 52.1% reduction in Ron,sp, a 20.3% increasement in BV and a 202.3% improvement in figure of merit. [ABSTRACT FROM AUTHOR]

In this study, we report on the direct-current (DC) and frequency characteristics of split-gate heterostructure field-effect transistors (HFETs) with different split-gate lengths. The split-gate HFET contains two distinct operating parts, the large and the small transconductance parts. The split-gate HFET has a current cutoff frequency ( f T ) of 814 MHz and a maximum oscillation frequency ( f max ) of 18.8 GHz in the large transconductance part. Meanwhile, in the small transconductance part, there is a higher unilateral power gain of f max = 2 7. 7 GHz. Also, the split-gate HFET exhibits a voltage gain greater than 1 (0 dB) at both DC and frequencies. Additionally, compared to the large transconductance part, the small transconductance part of the split-gate HFET presents a 53.5% reduction in DC power consumption and a larger input signal voltage range. Split-gate HFETs can be used as conventional power amplifiers in the large transconductance part and are also suitable as low-power voltage amplifiers in the small transconductance part. [ABSTRACT FROM AUTHOR]

In this work, we report on the high-performance p-GaN/InGaN/AlN multi-heterostructure p-channel metal–semiconductor field effect transistors (MESFETs) with energy-band modulated quantum well-like InGaN channel and low work function metal tungsten (W) as the gate material. A negative threshold voltage (VTH) of −0.35 V is achieved by precisely controlling the self-aligned etching depth at the active region. Benefiting from the enhanced hole confinement, the ION/IOFF ratio and subthreshold swing of the fabricated-channel MESFET are extracted to be 1.2 × 107 and 66 mV/dec, respectively, at room temperature. The idealized Schottky interface with TMAH and post-gate-annealing treatment shows an ultra-low voltage hysteresis of 0.08 V extracted at subthreshold area in the dual-sweep transfer curves. [ABSTRACT FROM AUTHOR]

This work develops a regrown fishbone trench (RFT) structure in selective area growth (SAG) technique to fabricate recessed-gate normally off GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs). The RFT structure effectively modulates the electric field at high drain and gate biases, thus allowing the device to feature improved off-state and gate breakdown performance with a high positive Vth of 2 V. The simulated carrier concentration and electric field distributions reveal the mechanism of electric field weakening by RFT architecture. Meanwhile, the current collapse phenomenon is significantly suppressed, and the gate voltage swing is also enlarged. The maximum gate drive voltage of 9.2 V for 10-year reliability of RFT GaN MIS-HEMT, together with the improved linearity and block voltage, broadens the applications of SAG devices. Furthermore, the RFT structure also provides an etching-free method for fabricating normally off GaN MIS-HEMTs with multi-dimensional gates. [ABSTRACT FROM AUTHOR]

Synaptic transistors (STs) with a gate/electrolyte/channel stack, where mobile ions are electrically driven across the solid electrolyte, have been considered as analog weight elements for neuromorphic computing. The current (ID) between the source and drain in the ST is analogously updated by gate voltage (VG) pulses, enabling high pattern recognition accuracy in neuromorphic systems; however, the governing physical mechanisms of the ST are not fully understood yet. Our previous physics-based simulation study showed that ion movement in the electrolyte, rather than the electrochemical reactions that occur in the channel, plays an important role in switching. In this study, we experimentally explore the properties of the HfOx electrolyte and show that by tuning the density of oxygen vacancies, it can assume the dual role of electrolyte and channel. We demonstrate analog synaptic behavior using a novel ST with a two-layer stack of CuOx/HfOx, where the CuOx is the gate and Cu ion reservoir, and the HfOx is the electrolyte and channel. To improve state retention and linearity, we introduce a Cu ion transport barrier in the form of a dense and stoichiometric Al2O3 layer. The CuOx/Al2O3/HfOx exhibits excellent state retention and improved potentiation and depression response. Energy dispersive spectroscopy mapping following potentiation confirms the role of the Al2O3 layer in confining the Cu ions in the HfOx layer. We also show that a two-step programming scheme can further enhance synaptic response and demonstrate high recognition accuracy on the Fashion-MNIST dataset in simulation. [ABSTRACT FROM AUTHOR]

The effect of pulsed laser radiation on the change in the parameters of semiconductor structures of field-effect transistors with a Schottky gate with an operating frequency range of 1.5–8 GHz and integrated amplifiers with an operating frequency range of 0.4–6 GHz is studied. Laser radiation with 25 ns pulse duration, incident on the transistor crystal, creates a pulsed photo current. It is shown that the amplitude of the pulsed photo current is three times higher than the operating transistor current. The current-voltage characteristics of the field-effect transistor were measured in the mode of pulsed laser radiation. The amplitude dependence of the pulsed photocurrent in semiconductor structures on the power of laser radiation for various wavelengths of 1.06 and 0.53 μm is studied. It is shown that as a result of the action of pulsed laser radiation on semiconductor structures, a short disappearance of the amplification of the high-frequency signal at the amplifier output occurs. [ABSTRACT FROM AUTHOR]

In this work, we have presented an analytical model for a recently proposed symmetrical recessed double gate junctionless field‐effect transistor (R_DGJLFET) operating in subthreshold region. The model has been developed by solving a two‐dimensional Poisson's equation in three continuous rectangular silicon regions, resulting in explicit expressions for surface potential, center potential, and eventually the subthreshold drain current. The model provides deeper physical insights by successfully incorporating the effect of various design parameters such as doping concentration, gate length, gate work function, and effective oxide thickness on the subthreshold drain current. Moreover, the effect of variations in gate length on the subthreshold slope has also been presented. The model results have been validated with the simulation results obtained from the Silvaco Atlas tool and found reasonably close. [ABSTRACT FROM AUTHOR]

An atomic layer etching (ALE) process without purge has been developed for gate recess etching of AlGaN/GaN high electron mobility transistors (HEMTs). The process consists of repeating ALE cycles where Cl2/BCl3 plasma modifies the surface by chemisorption. The modified layer is removed by the subsequential Ar ion removal step. In this manner, AlGaN/GaN HEMTs with three different gate recess etching depths of (7.3 ± 0.5), (13.6 ± 0.5), and (21.0 ± 0.5) nm were fabricated. The determined etch per cycle (EPC) of ∼0.5 nm corresponding to one unit cell in the c-direction of GaN was constant for all recesses, illustrating the precision and controllability of the developed ALE process. The root-mean-square surface roughness was 0.3 nm for every etching depth, which corresponds to the roughness of the unetched reference. The electrical measurements show a linear dependence between threshold voltage (Vth) and etching depth. An enhancement mode (E-mode) HEMT was successfully achieved. A deeper gate recess than 20 nm leads to an increased channel resistance, lower saturation current, and higher gate leakage. Hence, a compromise between the desired Vth shift and device performance has to be reached. The achieved results of electrical and morphological measurements confirm the great potential of recess etching using the ALE technique with precisely controlled EPC for contact and channel engineering of AlGaN/GaN HEMTs. [ABSTRACT FROM AUTHOR]

In this work, a novel enhancement-mode GaN p-MISFET with a buried back gate (BBG) is proposed to improve the gate-to-channel modulation capability of a high drain current. By using the p-GaN/AlN/AlGaN/AlN double heterostructure, the buried 2DEG channel is tailored and connected to the top metal gate, which acts as a local back gate. Benefiting from the dual-gate structure (i.e., top metal gate and 2DEG BBG), the drain current of the p-MISFET is significantly improved from −2.1 (in the conv. device) to −9.1 mA/mm (in the BBG device). Moreover, the dual-gate design also bodes well for the gate to p-channel control; the subthreshold slope (SS) is substantially reduced from 148 to ~60 mV/dec, and such a low SS can be sustained for more than 3 decades. The back gate effect and the inherent hole compensation mechanism of the dual-gate structure are thoroughly studied by TCAD simulation, revealing their profound impact on enhancing the subthreshold and on-state characteristics in the BBG p-MISFET. Furthermore, the decent device performance of the proposed BBG p-MISFET is projected to the complementary logic inverters by mixed-mode simulation, showcasing excellent voltage transfer characteristics (VTCs) and dynamic switching behavior. The proposed BBG p-MISFET is promising for developing GaN-on-Si monolithically integrated complementary logic and power devices for high efficiency and compact GaN power IC. [ABSTRACT FROM AUTHOR]

With the popularization of electronic devices and the demand for portability, low-power consumption has become crucial for integrated circuit chips. Two-dimensional (2D) semiconductors offer significant potential in constructing low-power devices due to their ultrathin thickness, enabling fully depletion operation. However, fabricating these 2D low-power devices, such as negative-capacitance transistors or tunneling transistors, often requires multiple layers of gate dielectrics or channel band engineering, adding complexity to the manufacturing process and posing challenges for their integration with silicon technology. In this work, we have developed low-power MoS2 metal–semiconductor field effect transistors utilizing a standard metal–semiconductor contact, which eliminates the need for gate dielectrics and semiconductor heterojunctions. It demonstrates a sharp subthreshold slope (SS ∼ 64 mV/dec), a minimum operating gate voltage range (−0.5 ∼ 1 V), a minimum current hysteresis (3.69 mV), and a stable threshold voltage close to 0 V (Vth ∼ −0.27 V). Moreover, we implemented an inverter circuit with a high voltage gain of 47. [ABSTRACT FROM AUTHOR]

The kink effect is a phenomenon that typically occurs in InP-based InAlAs/InGaAs high electron mobility transistors (HEMTs) at cryogenic temperatures. It results in higher output conductance (gDS) and non-monotonic behavior. This Letter discusses the origin and suppression of the kink effect in InP HEMTs at cryogenic temperatures, which is linked to the structure of gate recess passivation. At room temperature, two devices with different gate recess passivation structures show similar characteristics. However, a temperature-sensitive kink is observed in the non-passivated gate recess structure, leading to the discontinuous transconductance (gm) and the non-monotonic threshold voltage (Vth) shifts. Based on pulsed and static (non-pulsed) measurement data, surface traps and impact ionization in the high-field region are identified as the origin of the kink effect. Specifically, a positive Vth shift of +160 mV is caused by surface traps when the temperature drops to 150 K. A negative Vth shift of –60 mV is due to the enhanced impact ionization below 150 K. Conversely, the device with a passivated gate recess has a negligible kink effect and effectively improves discontinuous gm and the non-monotonic Vth shifts (+25 mV) when the temperature drops. Therefore, the device with a passivated gate recess is significant for suppressing the kink effect and maintaining the stability of the device in variable temperature environments. [ABSTRACT FROM AUTHOR]

In this article, an analytical method for designing transformer matching network of millimeter‐wave (mm‐wave) low noise amplifier (LNA) is presented. In the circuit design, neutralizing capacitors (NCs) structure is used to mitigate the intrinsic gate‐drain feedback capacitance in the transistor for increasing the reverse isolation and available gain, thus allowing the common source (CS) structure can be regarded as an unilateralized active amplification part. The equivalent circuit of the active amplification part and the matching transformer network is modeled, then the analytical matching equations can be established, and the required matching transformer parameter can be determined quickly. As a proof of concept, a Ka‐band LNA operating at 37–43 GHz is designed and implemented in 65 nm complementary metal oxide semiconductor. The measured results show that the small signal gain of the circuit is 19.2–20.5 dB at 37–43 GHz. The noise figure (NF) in the operating band is 3.2–4.2 dB, and the minimum NF is 3.2 dB at 40.2 GHz. The chip area is only 0.08 mm2 excluding pads. [ABSTRACT FROM AUTHOR]

Recent advances in the fabrication of neuromorphic electronic devices using biomaterials have received increasing attention for their prospect in biologically compatible and "green" electronic devices. Here, we proposed a novel electric-double-layer (EDL) synaptic transistor gated with Li-doped natural gelatin membranes, demonstrating larger capacitance at low frequency and extremely strong electrostatic modulation behavior. Experimental results have shown that a concentration of 2 wt. % Li-doping can obtain better electrical performance of EDL synaptic transistor. Ion/Ioff of 4.86 × 105 and threshold voltage of 0.68 V were obtained. Meanwhile, some important synaptic functions such as excitatory postsynaptic current, paired-pulse facilitation, and high-pass filtering characteristic have been successfully implemented. As a result, it can be inferred that the proposed gelatin-based natural polymer EDL electrolyte has demonstrated potential applications in "green" neuromorphic platforms. [ABSTRACT FROM AUTHOR]

In this study, we propose an optimized AlGaN/GaN high-electron-mobility transistor (HEMT) with a considerably improved breakdown voltage. First, we matched the simulated data obtained from a basic T-gate HEMT with the measured data obtained from the fabricated device to ensure the reliability of the simulation. Thereafter, to improve the breakdown voltage, we suggested applying a gate-head extended structure. The gate-head-top and gate-head-bottom lengths of the basic T-gate HEMT were symmetrically extended by 0.2 μm steps up to 1.0 μm. The breakdown voltage of the 1.0 μm extended structure was 52% higher than that of the basic T-gate HEMT. However, the cutoff frequency ( f T ) and maximum frequency ( f m a x ) degraded. To minimize the degradation of f T and f m a x , we additionally introduced a gate-recessed structure to the 1.0 μm gate-head extended HEMT. The thickness of the 25 nm AlGaN barrier layer was thinned down to 13 nm in 3 nm steps, and the highest f T and f m a x were obtained at a 6 nm recessed structure. The f T and f m a x of the gate-recessed structure improved by 9% and 28%, respectively, with respect to those of the non-gate-recessed structure, and further improvement of the breakdown voltage by 35% was observed. Consequently, considering the trade-off relationship between the DC and RF characteristics, the 1.0 μm gate-head extended HEMT with the 6 nm gate-recessed structure was found to be the optimized AlGaN/GaN HEMT for high-power operations. [ABSTRACT FROM AUTHOR]

A novel hybrid double gate junctionless transistor with gate engineering using a dual gate oxide stack has been proposed to improve short-channel effects and gate controllability for digital applications. The performance analysis and comparison of the proposed device with a DGLK junctionless transistor has been reported, hybrid Junctionless double gate transistor device has provided SS 61.4 mV/decade which is close to the ideal value of 60 mV/decade and 27.91% improvement, DIBL of 7.368 mV/V with 88.487% improvement, off current is 35.6 fA/µm, which is nearly 1.6 x10-6 times less and very high switching ratio of 1.648x 1010 which is 5.455 x106 times higher than junctionless double gate transistor. Also, the effect of variations in gate dielectric, spacer length has been studied. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel type of Gate All Around Nanosheet Field Effect Transistor (GAA NS FET) that incorporates source heterojunctions and strained channels and substrate. We compare its electrical characteristics with those of the Heterojunction Gate All Around Nanosheet Field Effect Transistor (Heterojunction GAA NS FET) and the Conventional Gate All Around Nanosheet Field Effect Transistor (Conventional GAA NS FET). We investigate the impact of electrostatic control on both DC and analog parameters such as gate capacitance (Cgg), transconductance gm, and cut-off frequency (fT) for all three device types. In our Proposed GAA NS FET, we employ Germanium for the source and substrate regions, Silicon/Germanium/Silicon (Si/Ge/Si) for the channel, and Silicon for the drain region. The introduction of strain into the nanosheet and the use of a heterojunction structure significantly enhance device performance. Before utilizing a model to analyze a semiconductor device, it is crucial to accurately determine and elaborate on the model parameters. In this case, we solve the Density Gradient (DG) equation self-consistently to obtain the electrostatic potential for a given electron Fermi-level distribution, use the Shockley-Read-Hall (SRH) equation to estimate carrier generation, account for bandgap narrowing in transport behavior, and consider auger recombination. Our general results indicate a notable improvement in drain current, transconductance, and unity-gain frequency by approximately 42%, 53%, and 31%, respectively. This enhancement results in superior RF performance for the Proposed GAA NS FET compared to both the heterojunction GAA NS FET and the conventional GAA NS FET. [ABSTRACT FROM AUTHOR]

This study aimed to propose a silicon-on-insulator (SOI)-based charge-trapping synaptic transistor with engineered tunnel barriers using high-k dielectrics for artificial synapse electronics capable of operating at high temperatures. The transistor employed sequential electron trapping and de-trapping in the charge storage medium, facilitating gradual modulation of the silicon channel conductance. The engineered tunnel barrier structure (SiO2/Si3N4/SiO2), coupled with the high-k charge-trapping layer of HfO2 and high-k blocking layer of Al2O3, enabled reliable long-term potentiation/depression behaviors within a short gate stimulus time (100 μs), even under elevated temperatures (75 and 125 °C). Conductance variability was determined by the number of gate stimuli reflected in the maximum excitatory postsynaptic current (EPSC) and the residual EPSC ratio. Moreover, we analyzed the Arrhenius relationship between the EPSC as a function of the gate pulse number (N = 1–100) and the measured temperatures (25, 75, and 125 °C), allowing us to deduce the charge trap activation energy. A learning simulation was performed to assess the pattern recognition capabilities of the neuromorphic computing system using the modified National Institute of Standards and Technology datasheets. This study demonstrates high-reliability silicon channel conductance modulation and proposes in-memory computing capabilities for artificial neural networks using SOI-based charge-trapping synaptic transistors. [ABSTRACT FROM AUTHOR]

In this paper, a new efficient technique is used in silicon-on-insulator metal–semiconductor field-effect transistors (SOI MESFETs) to simultaneously increase the breakdown voltage and drain current and also improve the frequency parameters. This proposed structure is presented for SOI MESFET with; he displaced gate contact toward the source region and creating distinct silicon oxide packets with different sizes under both sides of the gate electrode inside the channel. Gate electrode displacement from the middle of the device toward the source rises the transistor breakdown voltage. Increasing the distance between the drain and gate electrodes decrease the accumulation of equipotential lines in the corner of the gate on the drain side, and reduces the field, thereby increasing the breakdown voltage in the suggested device. In addition, moving the gate metal toward the source has negative effects on the frequency performance, so by adding two oxide zones on both sides of the gate region the device parasitic capacitances are suppressed to compensate the frequency performance. Numerical simulations reveal that the breakdown voltage in the basic and suggested structures are about 15 and 30 V, respectively. Also, the drain current of the presented structure shows a significant increase compared to its basic counterpart. Here, the maximum output power density is 0.32 W/mm for the presented device and 0.12 W/mm for the basic structure, indicating 166% enhancement. Also, the RF specifications of the suggested structure, including maximum available power gain, current gain, unilateral power gain, and maximum stable gain, were improved by 21, 66, 50, and 52%, respectively, and cutoff frequency in the basic structure is 19.5, increased to 21.5 GHz by applied adaptations. [ABSTRACT FROM AUTHOR]

In this Letter, we demonstrate the Schottky gated p-AlGaN/u-GaN/AlGaN p-channel field-effect transistors (p-FETs) with an extremely low interface state density of 2.5 × 1011 cm−2 eV−1. Benefiting from the high-quality Schottky interface with suppressed interface states, the excellent stability with negligible hysteresis is proved, even after ten sequential dual I–V sweeps at 150 °C. Meanwhile, the trap density, confirmed by the temperature-dependent conductance method, is still below 1012 cm−2 eV−1 at high temperature. Furthermore, the fabricated p-AlGaN/u-GaN/AlGaN p-FET with a gate to drain distance of 1.8 μm shows a breakdown voltage of −128 V and an effective on-resistance of 7.2 kΩ mm, which allows the further scale down in terms of the source–drain spacing to improve the conduction current for low voltage application. The ultra-stable I–V characteristics of the fabricated Schottky-gated p-AlGaN/u-GaN/AlGaN p-FETs show great potential for next-generation integrated circuit application at high temperatures. [ABSTRACT FROM AUTHOR]

GaN has become a prevailing semiconductor in case of power and RF applications. The higher ranking material parameters of GaN, like wider band‐gap, the higher breakdown electric field as well as higher electron velocity when compared to materials like Si, SiC, GaAs etc; allow GaN FINFET to reveal potential advantages such as high voltage and high frequency applications. In this work, a comprehensive study on RF and linearity analysis on Heterojunction‐free GaN layer FINFET through visual technology computer‐aided design (TCAD) device simulator is been illustrated. The influence of varying the Finwidth's of the device on numerous RF parameters like drain current, transconductance (gm), output conductance (gd), gate capacitances(Cgd and Cgs), cut‐off frequency (fT) are studied. And also, the impact of varying the Finwidth's of the device on the numerous linearity parameters like gm2, gm3, VIP3, IIP3, 1 dB compression point were also studied. It is been observed that the higher Finwidth value is more worthy for radio frequency integrated circuit (RFIC) applications. [ABSTRACT FROM AUTHOR]

In recent trends, digital systems in the light of power dissipation are a crucial issue. In computing, the computational process of reversible logic is bijective and can decrease the rising issue of power dissipation. In reversible circuit design, Peres gate considered as one of the fundamental reversible gate. Therefore, a Peres gate using Add/Drop Multiplexer (ADM) and Reflective Semiconductor Optical Amplifier (RSOA) is proposed in this paper. Frequency encoding scheme and dibit-based logic are incorporated here. In long range transmission, frequency encoding bears huge benefits in respect with the other encoding techniques. This encoding technique may decrease the probability of bit error. Due to the high gain and low noise property of RSOA, the proposed design can perform operations like computation, data processing, etc. at ultra-high speed with low noise. MATLAB Simulink (R2018a) software has been used to verify the operation of the proposed design. [ABSTRACT FROM AUTHOR]

A 3 channel rectangular Gate All Around Nano-Wire Multi Bridge Channel Field Effect Transistor (GAA NWMBCFET) is introduced in this work by integrating multi bridge channel into Gate All Around Nano-wire Field Effect Transistor (GAA NWFET) with increased drain current and enhanced Short Channel Effect (SCE) suppression for a gate length of 35 nm. Gate capacitance increases significantly due to vertically stacked channels enclosed by the gate. To understand the characteristics and behavior of the proposed GAA NWMBCFET, a rigorous analysis was conducted using a reliable physical model: the temperature-dependent carrier transport model (DD). Within this analysis, the Mobility Model (MM) played a crucial role in incorporating the effects of doping concentration and electric field. Additionally, the Bandgap Narrowing Model (BNM) and the Shockley-Read-Hall recombination Model (SRM) were instrumental in addressing carrier lifetime concerns. Utilizing Synopsys Sentaurus Technology Computer Aided Design (TCAD) facilitated the simulation of our proposed model, enabling a thorough examination of its characteristics. The rectangular multi bridge channel device exhibit 2.3 times better drain current than the rectangular nano-wire transistor. In addition, the Ultra Thin Body (UTB) in the device inhibits Sub threshold Swing (SS) and Drain Induced Barrier Lowering (DIBL) which contributes to minimized off current. The current drive has a 28 % increase for LG = 5 nm than GAA NWFET. Furthermore, to ensure a comprehensive understanding of the device behavior, a detailed analysis of trans conductance was performed for a gate length of 35 nm. Additionally, analyses were extended to gate lengths of 5 nm, enabling a thorough evaluation of both GAA NWMBCFET and GAA NWFET. [ABSTRACT FROM AUTHOR]

With the rapid development of semiconductor technology, chip integration is getting beyond imagination. Aging has become one of the main threats to circuit reliability. In order to develop aging degradation prediction, it is critical to evaluate aging to avoid circuit failures. At present, the research on aging prediction is mainly focused at the transistor and gate levels: at transistor level, the precision is high, but the speed is low; whereas, the gate-level accuracy is not high, but the speed is very fast. In this paper, a path-level aging prediction framework based on the novel critical gate is proposed. The 10-year Negative Bias Temperature Instability (NBTI) aging delay of the critical subcircuit extracted by the novel critical gate is obtained, and the aging delay trend is learnt by using a linear regression model. Then the critical path aging delay can be obtained quickly based on the framework developed by machine learning using the linear regression model. The experimental results of ISCAS'85 and ISCAS'89 benchmark circuits based on 45-nm PTM show that the proposed framework is superior to the existing methods. [ABSTRACT FROM AUTHOR]

The current collapse has been one of the most challenging problems in AlGaN/GaN high electron mobility transistors (HEMTs). In recent years, the virtual gate effect has been the most widely accepted cause of the current collapse effect. To effectively improve the current collapse effect and reduce the influence of the virtual gate effect on the device, a point‐contact gate AlGaN/GaN HEMT structure is proposed in this article. Tests show that the device has high transconductance, high cut‐off frequency, and good transfer, output, and breakdown characteristics. The maximum saturation drain current is 18 mA mm−1, the maximum transconductance is 200 mS mm−1, the breakdown voltage is 994 V, the maximum current gain is about 190 dB, and the cut‐off frequency is up to 206 GHz when the gate length and width are 0.1 μm × 0.001 μm. The experimental analysis shows that the point‐contact gate AlGaN/GaN HEMT structure shortens the gate length, thereby improving the virtual gate effect and effectively suppressing the current collapse effect, increasing the breakdown voltage of the device, and further improving the device performance, which lays the foundation for the future research of AlGaN/GaN HEMT. [ABSTRACT FROM AUTHOR]

This paper presents a novel approach to the efficient extraction of parasitic resistances in high electron mobility transistors (HEMTs). The study reveals that the gate resistance value can be accurately determined under specific forward gate bias conditions (Vg = 1.0 V), although the gate resistance value becomes unreliable beyond this threshold (Vg > 1.0 V) due to potential damage to the Schottky contact. Furthermore, by examining the characteristics of the device under a cold-FET bias condition (Vds = 0 V), a linear correlation between the gate and drain current is identified, enabling an estimation of the interdependence between the drain and source resistance using the proposed method. The estimation of parasitic pad capacitance (Cpg and Cpd) from Dambrine's model is refined by incorporating the depletion layer capacitance on the gate side during the pinch-off condition. To validate the accuracy of the extracted parasitic capacitance and resistance values obtained from the new method, small-signal modeling is performed on a diverse range of measured devices. [ABSTRACT FROM AUTHOR]

Photosynthetic reaction center (pRC) purified from Rhodobacter sphaeroides 2.4.1 purple bacteria was deposited on a graphene carrier exfoliated from the liquid phase and layered on the surface of SiO2/Si substrate for optoelectronic application. Light-induced changes in the drain-source current vs. gate voltage are demonstrated. Dried photosynthetic reaction centers/graphene composite on SiO2/Si shows a photochemical/-physical activity, as a result of interaction with the current flow in the graphene carrier matrix. The current changes are sensitive to light, due to the contribution from the charge separation in the pRC, and to the applied gate and drain-source voltages. [ABSTRACT FROM AUTHOR]

In this paper, a P-type GaN buried layer is introduced into the buffer layer of AlGaN/GaN HEMTs, and the effect of the P-type GaN buried layer on the device's temperature characteristics is studied using Silvaco TCAD software. The results show that, compared to the conventional device structure, the introduction of a P-type GaN buried layer greatly weakens the peak of the channel electric field between the gate and drain of the device. This leads to a more uniform electric field distribution, a substantial reduction in the lattice temperature of the device, and a more uniform temperature distribution. Therefore, the phenomenon of negative resistance caused by self-heating effect is significantly mitigated, while the breakdown performance of the device is also notably enhanced. [ABSTRACT FROM AUTHOR]

A novel split-gate SiC MOSFET with an embedded MOS-channel diode for enhanced third-quadrant and switching performances is proposed and studied using TCAD simulations in this paper. During the freewheeling period, the MOS-channel diode with a low potential barrier constrains the reverse current flow through it. Therefore, the suggested device not only has a low diode cut-in voltage but also entirely suppresses the intrinsic body diode, which will cause bipolar deterioration. In order to clarify the barrier-lowering effect of the MOS-channel diode, an analytical model is proposed. The calibrated simulation results demonstrate that the diode cut-in voltage of the proposed device is decreased from the conventional voltage of 2.7 V to 1.2 V. In addition, due to the split-gate structure, the gate-to-drain charge (QGD) of the proposed device is 20 nC/cm2, and the reverse-transfer capacitance (CGD) is 14 pF/cm2, which are lower than the QGD of 230 nC/cm2 and the CGD of 105 pF/cm2 for the conventional one. Therefore, a better high-frequency figure-of-merit and lower switching loss are obtained. [ABSTRACT FROM AUTHOR]

In this study, we present an intrinsic device parameter method based on a single device for disordered polymer field-effect transistors (PFETs). Charges in disordered polymer semiconductors transport through localized states via thermally activated hopping, of which field-effect mobility and contact resistance are gate-bias-dependent. By considering the parameters expressed as gate bias-dependent power laws, dividing drain current with transconductance (Ids/gm method) leads to the current–voltage relation decoupled from the contact effect. Following this derived relationship, the intrinsic field-effect mobility and the contact resistance of the PFETs are extracted and found to be consistent with those using the four-probe method. Thus, we can state that the proposed method offers practical benefits for extracting the intrinsic device parameters of disordered PFETs in terms of using a single transfer characteristic of the devices. [ABSTRACT FROM AUTHOR]

GaN/AlGaN, known as the third-generation semiconductor, is widely used in advanced power and RF devices. A precise and low-damage etch process is essential for the preparation of recessed-gate enhancement-mode GaN high electron mobility transistors. Atomic layer etching (ALE) offers novel opportunities during the ultraprecision manufacturing process by splitting etch process into a surface modification step and a modified layer removal step. In this work, two self-limiting AlGaN ALE systems (O2-BCl3 and chlorinate-argon) are reported in detail. The results of the two systems are analyzed and compared. This research provides a deep insight into the ALE mechanism of AlGaN and a broad cognition for applying ALE to engineering problems. [ABSTRACT FROM AUTHOR]

The authors' present a silicon‐on‐insulator (SOI) laterally diffused metal‐oxide‐semiconductor field‐effect transistor (LDMOSFET) with β‐Ga2O3 , which is a large bandgap semiconductor (β‐LDMOSFET), for increasing breakdown voltage (VBR) and power figure of merit. The fundamental purpose is to use a β‐Ga2O3 semiconductor instead of silicon material due to its large breakdown field. The characteristics of β‐LDMOSFET are analysed to those of standard LDMOSFET, such as VBR, ON‐resistance (RON), power figure of merit (PFOM), and radio frequency (RF) performances. The effects of RF, such as gate‐drain capacitance (CGD), gate‐source capacitance (CGS), transit frequency (fT), and maximum frequency of oscillation (fMAX) have been investigated. The β‐LDMOSFET structure outperforms performance in the VBR by increasing it to 500 versus 84.4 V in standard LDMOSFET design. The suggested β‐LDMOSFET has RON ~ 2.3 mΩ.cm−2 and increased the PFOM (VBR2/RON) to 108.6 MW/cm2. All the simulations are done with TCAD and simulation models are calibrated with the experimental data. [ABSTRACT FROM AUTHOR]

Field-effect transistor (FET)-based sensors allow rapid, label-free electrical detection of chemical and biological species and are easy to use. Dual-gate FET-based biosensors enable sensitive detection with high intensity signal by their distinctive structure based on a combination of solid and liquid gates. However, the underlying mechanism of signal amplification to explain the experimental results has not been well explained with theoretical analysis. In this work, a theoretical approach based on device physics is used to interpret the signal enhancement in dual-gate FET-based biosensors. The analysis is verified with a simulation method for pH sensors based on a well-established commercialized semiconductor 3D technology computer-aided design simulation. The pH sensing parameters are comprehensively investigated as a function of the electrical characteristics of dual-gate FETs: the voltage, current, and normalized current signals are directly correlated with capacitive coupling, transconductance, and subthreshold swing, respectively. Our theoretical analysis provides design guidelines for sensitive dual-gate FET-based biosensors. [ABSTRACT FROM AUTHOR]

This work is a systematic investigation of electronic transport and inelastic effects of two-terminal devices without gates composed of zigzag and armchair phagraphene nanoribbons doped with boron nitride. It is based on a hybrid density functional theory and the nonequilibrium Green's function method implemented in the TRANSIESTA code. The doping in the device with a zigzag conformation had a metal–semiconductor transition, symmetric eigenchannels (ECs), high transmission probability, and an evident field-effect transistor (FET) signature with two operating windows. The armchair configuration had a semiconductor–metal transition, asymmetric features in the ECs that decrease the transmission probability considerably, a switch signature for low bias, and FET behavior for bias V > --> 0.2 V. These results suggest that the impurities improve the electron transport for both edge conformations. On the other hand, inelastic transport made a smaller contribution to the current and conductance compared to elastic transport. Inelastic electron-tunneling spectroscopy showed that electron tunneling in phagraphene devices is mainly driven by elastic effects, indicating that almost all the energy of the system is conveniently used in the electronic transport and is not lost through network vibrations. [ABSTRACT FROM AUTHOR]

Toward interface charge engineering in AlTiO/AlGaN/GaN metal-insulator-semiconductor (MIS) devices, we systematically investigated insulator-semiconductor interface fixed charges depending on the composition of the AlTiO gate insulator obtained by atomic layer deposition. By evaluating the positive interface fixed charge density from the insulator-thickness dependence of the threshold voltages of the MIS devices, we found a trend that the interface fixed charge density decreases with the decrease in the Al composition ratio, i.e., increase in the Ti composition ratio, which leads to shallow threshold voltages. This trend can be attributed to the large bonding energy of O-Ti in comparison with that of O-Al and to consequent possible suppression of interface oxygen donors. For an AlTiO gate insulator with an intermediate composition, the MIS field-effect transistors exhibit favorable device characteristics with high linearity of transconductance. These results indicate a possibility of interface charge engineering using AlTiO, in addition to energy gap engineering and dielectric constant engineering. [ABSTRACT FROM AUTHOR]

We report solution-processed oxide thin-film transistors (TFTs) with an indium oxide (InO) channel and a lanthanum–zirconium oxide (LZO) gate insulator with a transconductance (of the mS order) that was two to three orders of magnitude higher than in common oxide TFTs. Analyses revealed that while the mobility was not high, the induced charge density in the channel was extremely high [typically >1.2 × 1014 cm–2 per volt of VG, corresponding to a high dielectric constant (ɛr) of >5000 for the InO/LZO structure]. In addition, the TFTs exhibited low operating voltages (1–2 V) and low subthreshold swing factors (SS, 70–90 mV decade−1) that were close to the theoretical limit (∼60 mV decade−1 at room temperature) of an ideal transistor. The transconductance decreased with decreasing humidity and was similar to that of a typical oxide TFT in a dry environment. Our data indicated that the high carrier density may arise from the formation of electric double layers in the presence of water molecules. Additionally, the crystallinity of the InO channel layer was dependent on the La/Zr ratio in LZO: the crystallinity significantly improved with an La/Zr ratio of 3/7 (high-transconductance TFTs) compared with a ratio of 7/3 (usual TFTs). [ABSTRACT FROM AUTHOR]