Search

In this paper, we describe a new wafer-yield distribution model, which agrees well with experiment using fabricated products with various process technologies. To investigate physical reasoning of the proposed model, we firstly measure effective defect density of chips regarding to spatial dependency in a wafer. It is clarified that the defect density near wafer edge is a couple of times larger than that at the rest of wafer area. Note that the increase of defect at wafer edge causes a significant yield loss in production process lines. Index Terms--Defect density, distribution model, PDF, spatial statistics, wafer-yield.

For future large-scale integration design technology, the device matrix array (DMA), which precisely evaluates within-die variation in device parameters, has been developed. The DMA consists of a 14-by-14 array of common units. The unit size is 240 by 240 [micro]m, and each unit contains 148 measurement elements (52 transistors, 30 capacitors, 51 resistors, and 15 ring oscillators). The element selection and precise measurement are achieved with low parasitic resistance measurement buses and leakage-controlled switching circuits, which allow the measurement accuracy for a transistor, resistor, or capacitor of 90 pA, 11 m[ohms], and 23 aF, respectively, in the 3[sigma] range. The ability to obtain 29008 samples from a chip enables statistical analysis of the variation in 148 elements of each chip with 240-[micro]m spatial resolution. This high resolution and large sample number allows us to precisely decompose the data into systematic and random variation parts with newly developed fourth-order polynomial fitting. Our methodology has been verified using a test chip fabricated by a 130-nm CMOS process with a 100-nm physical gate length and five Cu interconnect layers. In MOSFETs, the random part was dominant and indicated a certain [sigma] value in every chip. In the case of the interconnect layers, the random and systematic parts of the resistance and the capacitance indicated variance fluctuations. By chip, by item, by size, by structure, random or systematic, the [sigma] values of each variation show inconsistency which we believe is attributable to the Cu process. The correlation coefficients of systematic part between device element and ring oscillator frequency shown very high value (0.87-0.98), and those of a random part were low enough (-0.10-0.22) to prove the accuracy of decomposition. Index Terms--Correlation analysis, device variation, leakage control, parameter measurement, polynomial fitting, statistical analysis, switching matrix, variance characteristic, variance decomposition, within-die variation.

We have developed the world's first large-scale test element group (TEG) with large-scale elements that accurately evaluate SoC (system on chip)-level yield and variation. To enable quick feedback on processing, address decoders on all four sides of the chip and testing programs were also developed. The TEG has a simple structure to examine pure (i.e., not oriented to products) logic-processes, yield and variation for near-minimum DSM (deep sub-micron) design rules. We have successfully measured yield, failure mode and locations both before and after on-chip high-voltage stress. It was also demonstrated that intra-/inter-die variations in various process/device elements could be quickly diagnosed within a week. The new TEG consists of five chips designed using 130-nm CMOS technology with 100-nm physical gate lengths and five copper interconnect layers. The proposed TEG could provide a strategic standard test structure for diagnosis of SoC yield/variation, as well as a technology standard for measuring electrical dimensions and evaluating charge-up damage. Index Terms--Address decoder, charge up, correlation analysis, damage, electrical dimension, large scale, pattern density, periodicity, TEG, test structure, variation, wafer map, yield.

An improved equivalent circuit model of GaAs field effect transistors (FET) is described and discussed.

Effects of statistical process variation on the 0.35-[[micro]meter] CMOS performance have been accurately characterized by using a new calibrated TCAD methodology. To conduct the variation analysis, a series of TCAD simulations was conducted on the basis of DoE (design of experiments) with optimum variable transformations, which resulted in RSF's (response surface functions) for threshold voltage ([V.sub.th]) and saturation drain current ([I.sub.ds]). A new global calibration of the RSF model based on experimental data gives excellent accuracy within 0.02 V error in [V.sub.th] and 3% error in [I.sub.ds]. Using calibrated RSF, statistical process variation effects on the device characteristics have been quantitatively evaluated for each process recipe. It is found that variation of the gate-oxide formation process shows the most significant effect on the NMOS [Delta][I.sub.ds] in the production process. Furthermore we have designed an optimized 0.25-[[micro]meter] CMOS process and device on the basis of the RSF and also predicted the process variation effects on the device performance. It is shown that the [V.sub.th] and [I.sub.ds] variations of the 0.25-[[micro]meter] CMOS exhibit less than 10% [I.sub.ds] variation in the production level process, which is similar to the value of 0.35-[[micro]meter] CMOS experimental data. Additional TCAD simulations for MOS model parameter generation of the 0.25-[[micro]meter] device was also conducted to allow circuit-designers to use predictive worst case circuit design parameters before experimental chip fabrication. Index Terms - Calibration, LSI, RSM, sensitivity analysis, TCAD.

This paper describes the generation of a new universal design chart for submicron multilevel interconnection and its verification using test-structures. This has been developed to give the precise interconnect-capacitance for parallel submicron multilevel interconnections. Parasitic effects of a passivation film ([Si.sub.3][N.sub.4]) on the interconnect capacitance have been also studied. The results of the test-structures designed have shown an excellent agreement with the design-chart with a maximum error of 8%. Furthermore, a simple propagation delay and response voltage model to a step voltage input have been developed incorporating the parallel-interconnect capacitance model. The new model is based on a lossy-transmission line equation and demonstrates an excellent agreement with RC lumped circuit simulations, resulting in a new simple and accurate prediction method for interconnect delay for use in VLSI timing design.

We have proposed a novel discrete exponential distribution function, which describes a defect count distribution on wafers or chips more accurately, especially in near defect-free conditions. The conventional approach based on a gamma probability density function (g-pdf) is known to fail in expressing the defects of defect-free wafers or chips, because it always gives zero as the pdf value. Since the number of defects is countable (discrete distribution should be used) and analyzed in terms of nondefective chip yield, the g-pdf cannot be used because of its inaccuracy in the near defect-free condition. A discrete exponential pdf is introduced corresponding to the defect count distribution. In addition, a convolution formula of the new pdf is derived statistically which can express realistic defect count distribution with multiple defect sources. It is noted that the popular negative binomial yield formula (NBYF) is directly derived with the convoluted discrete exponential distribution, which interprets the cluster factor given in NBYF as the number of different defect sources predicted. It is experimentally proven that defect count distributions are approximated by this new model within an average error of about 0.01 defects per wafer from film deposition process data.

Examines the impact of crosstalk on delay. Measurement of a test chip manufactured with node technology; Requirements for precise and fast gate-level simulation technology; Reduction of the maximum error between the measured and simulated degradation.

A highly accurate one-dimensional table model has been developed for an MOS transistor simulation used in a circuit simulation necessary for the VLSI design. The usefulness of the model for the circuit simulation has been tested. Traditionally, the one-dimensional table model has been used in the area where high precision is not required, such as the timing simulators. It is not sufficient for simulation of a high-precision circuit and the MOS transistor of submicron level. In the new one-dimensional table model, the two-dimensional effect of the drain and gate electric fields is included and only two one-dimensional tables are added. The model can be applied to a high-precision circuit simulation. This model has been applied to three devices with the effective channel length of 0.66 - 2.30 µm fabricated in different processes. It was found that the maximum of the average relative error within the practical voltage range is 3.87% which corresponds to the accuracy four times that in the conventional model. Increase of the error for the variation of the substrate voltage is especially small. It has been demonstrated that the present one-dimensional table model is a transistor model capable of high-precision circuit simulation. [ABSTRACT FROM AUTHOR]