A new characterization of sub-micro(m) parallel multilevel interconnects and experimental verification

This paper describes the generation of a new universal design chart for submicron multilevel interconnection and its verification using test-structures. This has been developed to give the precise interconnect-capacitance for parallel submicron multilevel interconnections. Parasitic effects of a passivation film ([Si.sub.3][N.sub.4]) on the interconnect capacitance have been also studied. The results of the test-structures designed have shown an excellent agreement with the design-chart with a maximum error of 8%. Furthermore, a simple propagation delay and response voltage model to a step voltage input have been developed incorporating the parallel-interconnect capacitance model. The new model is based on a lossy-transmission line equation and demonstrates an excellent agreement with RC lumped circuit simulations, resulting in a new simple and accurate prediction method for interconnect delay for use in VLSI timing design.