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1. Guidelines for intermediate back end of line (BEOL) for 3D sequential integration.

Author: Claire Fenouillet-Béranger, S. Beaurepaire, Fabien Deprat, Alexandre Ayres De Sousa, Laurent Brunet, Perrine Batude, Olivier Rozeau, François Andrieu, Paul Besombes, M.-P. Samson, Bernard Previtali, F. Nemouchi, G. Rodriguez, Philippe Rodriguez, R. Famulok, Nils Rambal, Viorel Balan, Z. Saghi, V. Jousseaume, Charles-Antoine Guérin, F. Ibars, F. Proud, D. Nouguier, David Ney, V. Delaye, H. Dansas, X. Federspiel, and Maud Vinet
Published: 2017
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2. Recent advances in 3D VLSI integration.

Author: Claire Fenouillet-Béranger, Perrine Batude, Laurent Brunet, Vincent Mazzocchi, Cao-Minh Vincent Lu, Fabien Deprat, Jessy Micout, M.-P. Samson, Bernard Previtali, Paul Besombes, Nils Rambal, François Andrieu, Olivier Billoint, Melanie Brocard, Sébastien Thuries, Gerald Cibrario, and Maud Vinet
Published: 2016
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3. Integration of Low-k Low Temperature 400°C SiCO as Offset Spacer in view of 3D Sequential Integration

Author: C. Fenouillet-Beranger, L. Brunet, E. Arnoux, V. Lu, V. Beugin, C. Guerin, S.Del Medico, V. Loup, M.-P. Samson, B. Previtali, C. Tabone, N. Rambal, N. Rochat, D. Benoit, F. Allain, G. Romano, T. Artemisia, M. Casse, X. Garros, H. Dansas, A. Grenier, P. Batude, and M. Vinet
Subjects: Materials science, Offset (computer science), business.industry, Optoelectronics, business
Published: 2018
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4. Performance and Design Considerations for Gate-All-Around Stacked-NanoWires FETs

Author: C. Vizioz, J.M. Hartmann, Maud Vinet, Sotirios Athanasiou, Jean-Charles Barbe, Francois Andrieu, Sebastien Martinie, Thomas Ernst, Olivier Rozeau, C. Comboroure, V. Lapras, Marie-Anne Jaud, François Triozon, Bernard Previtali, Joris Lacord, M.-P. Samson, Sylvain Barraud, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), STMicroelectronics [Crolles] (ST-CROLLES), ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010), and European Project: 688101,H2020,H2020-ICT-2015,SUPERAID7(2016)
Subjects: 010302 applied physics, Flexibility (engineering), Electron mobility, Materials science, Transistor, Nanowire, 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, 021001 nanoscience & nanotechnology, 01 natural sciences, 7. Clean energy, Engineering physics, Capacitance, law.invention, Gallium arsenide, chemistry.chemical_compound, [SPI]Engineering Sciences [physics], chemistry, law, Logic gate, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, 0210 nano-technology, Nanosheet
Abstract: International audience; This paper presents recent progress on Gate-All-Around (GAA) stacked-NanoWire (NW) / NanoSheet (NS) MOSFETs. Key technological challenges will be discussed and recent research results presented. Width-dependent carrier mobility in Si NW/NS and FinFET will be analyzed, and intrinsic performance and design considerations of GAA structures will be discussed and compared to FinFET devices with a focus on electrostatics, parasitic capacitances and different layout options. The results show that more flexibility can be achieved with stacked-NS transistors in order to manage power-performance optimization.
Published: 2017
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5. High performance low temperature FinFET with DSPER, gate last and Self Aligned Contact for 3D sequential mtegration

Author: J. Micout, M. Casse, J.-P. Colinge, L. Desvoivres, Vincent Delaye, C. Fenouillet-Beranger, S. Barraud, X. Garros, Perrine Batude, J.M. Hartmann, R. Bortolin, V. Mazzocchi, Frédéric Mazen, G. Romano, B. Mathieu, N. Rambal, V. Balan, Zineb Saghi, F. Allain, M.-P. Samson, P. Besombes, C. Comboroure, M. Vinet, Quentin Rafhay, Joris Lacord, Claude Tabone, Alain Toffoli, Gerard Ghibaudo, C. Vizioz, Benoit Sklenard, V. Lapras, L. Lachal, Laurent Brunet, Virginie Loup, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), STMicroelectronics [Crolles] (ST-CROLLES), Laboratoire des technologies de la microélectronique (LTM ), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), ANR-10-LABX-0055,MINOS Lab,Minatec Novel Devices Scaling Laboratory(2010), and ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010)
Subjects: Materials science, Fabrication, business.industry, 020208 electrical & electronic engineering, Doping, Recrystallization (metallurgy), 02 engineering and technology, Epitaxy, Logic gate, 0202 electrical engineering, electronic engineering, information engineering, Optoelectronics, 020201 artificial intelligence & image processing, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business
Abstract: session 32: Process and Manufacturing Technology (32.2); International audience; For the first time, a low temperature (LT) FinFET process is demonstrated, using Solid Phase Epitaxy Regrowth (SPER), gate last integration and Self Aligned Contact (SAC). The LT devices exhibit performances close to those of the High Temperature Process Of Reference (HT POR). Several techniques of SPER doping are investigated and an innovative Double SPER (DSPER) process using two amorphization/recrystallization steps, is demonstrated. This DSPER process has the advantage of doping the bulk of the S/D junctions. This work opens the door to the fabrication of high-performance LT FinFETs for 3D sequential integration.
Published: 2017
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6. Guidelines for intermediate back end of line (BEOL) for 3D sequential integration

Author: Vincent Delaye, D. Nouguier, Zineb Saghi, N. Rambal, Claire Fenouillet-Beranger, Olivier Rozeau, V. Balan, Philippe Rodriguez, Francois Andrieu, Maud Vinet, S. Beaurepaire, A. Ayres de Sousa, C. Guerin, P. Besombes, Laurent Brunet, Vincent Jousseaume, H. Dansas, M.-P. Samson, F. Proud, Bernard Previtali, D. Ney, R. Famulok, F. Deprat, F. Ibars, Guillaume Rodriguez, Perrine Batude, Xavier Federspiel, and Fabrice Nemouchi
Subjects: Very-large-scale integration, Engineering, Interconnection, business.industry, 02 engineering and technology, 010402 general chemistry, 021001 nanoscience & nanotechnology, 01 natural sciences, Capacitance, 0104 chemical sciences, Back end of line, Stack (abstract data type), Electronic engineering, Thermal stability, 0210 nano-technology, business
Abstract: For the first time the thermal stability of a new fluorine-free (F-free) W barrier coupled with W interconnections enabling 22% line 1 resistance improvement is evaluated in view of 3D VLSI integration. Integrated with ULK, no resistance nor lateral capacitance degradation is observed up to 550°C 5h while preserving good reliability. For additional thermal stability a TEOS/W stability is demonstrated up to 600°C 2h. Both types of interconnection stacks have been successfully integrated on devices with 28nm design rules and show similar performance for MOSFETs and Ring Oscillators (RO) as compared to the ULK/Cu stack. Finally, iBEOL guidelines are given at the end in view of 3D sequential integration.
Published: 2017
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7. Key process steps for high performance and reliable 3D Sequential Integration

Author: J. Micoud, C.-M. V. Lu, Maud Vinet, Charles Leroux, Xavier Federspiel, R. Gassilloud, Perrine Batude, Laurent Brunet, Vincent Delaye, G. Romano, L. Pasini, Xavier Garros, F. Deprat, Claude Tabone, D. Nouguier, N. Rambal, Bernard Previtali, P. Besombes, D. Ney, D. Barge, Francois Andrieu, A. Toffoli, M.-P. Samson, Thomas Skotnicki, A. Tsiara, and Claire Fenouillet-Beranger
Subjects: 010302 applied physics, chemistry, Computer science, Logic gate, 0103 physical sciences, Process integration, Electronic engineering, Gate stack, chemistry.chemical_element, 010502 geochemistry & geophysics, Tin, 01 natural sciences, 0105 earth and related environmental sciences
Abstract: This work provides breakthroughs in key technological modules for high performance and reliable 3D Sequential Integration with intermediate BEOL (iBEOL) in-between tiers. We demonstrate that (i) a high-quality solid phase epitaxy process is possible at 500°C, (ii) TiN native oxide removal prior to poly deposition leads to an improvement in gate stack reliability below 525°C and (iii) state-of-the-art SiOCH ULK in iBEOL is reliable up to 550°C 5h with W metal lines. A process integration is thus proposed to match the process windows of bottom layers (bottom FET and iBEOL) stability and top devices performance and reliability, opening perspectives for a wide range of applications and technologies using 3D Sequential Integration.
Published: 2017
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8. Hydrogen silsesquioxane tri-dimensional advanced patterning concepts for high density of integration in sub-7 nm nodes

Author: B. Hemard, Sébastien Barnola, L. Gaben, S. Pauliac, Virginie Loup, C. Euvrard, J.-A. Dallery, Y. Exbrayat, M.-P. Samson, Thomas Skotnicki, Christian Arvet, M. Vinet, X. Bossy, C. Vizioz, L. Koscianski, Frederic Boeuf, C. Perrot, R. Dechanoz, J. Bustos, B. Previtali, B. Perrin, V. Balan, Francis Balestra, James C. Sturm, S. Barraud, Stephane Monfray, Pascal Besson, STMicroelectronics [Crolles] (ST-CROLLES), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), and Vistec Electron Beam GmbH
Subjects: Extreme ultraviolet lithography, 3D lithography, Nanowire, Nanotechnology, Hardware_PERFORMANCEANDRELIABILITY, 01 natural sciences, stacked nanowire FETs, law.invention, SNWFET, chemistry.chemical_compound, Etching (microfabrication), law, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, HSQ, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Lithography, Hydrogen silsesquioxane, 010302 applied physics, business.industry, Transistor, CMOS, chemistry, Logic gate, FinFET, Optoelectronics, business
Abstract: Best paper award; session 9: Novel Materials and Technologies; International audience; Recent developments in CMOS devices such as FinFET, FDSOI or stacked nanowire FETs (SNWFETs) have led the industry to consider increasingly complex integration processes while aiming at smaller and smaller devices. This paper proposes new concepts of device integration based on the use of hydrogen silsesquioxane (HSQ). Recently employed to replace polysilicon sacrificial gate in gate last processes, its use could also be extended for building the whole transistor level including device lateral insulation, multi-workfonction layouts, self-aligned contacts and possibly the first layer of metal interconnects. If several EUV masks could be employed for such a use, HSQ patterning once enhanced by multi-electron beam lithography, could allow to perform all these features within a single exposure step without involving any conventional etching or stripping steps.
Published: 2017
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9. Dense N over CMOS 6T SRAM cells using 3D Sequential Integration

Author: X. Garros, N. Rambal, C. Fenouillet-Beranger, M. Brocard, L. Pasini, G. Cibrario, Thomas Skotnicki, M.-P. Samson, A. Ayres, Laurent Brunet, M. Vinet, C. Tallaron, C-M. V., O. Billoint, R. Gassilloud, Francois Andrieu, R. Kies, G. Romano, Perrine Batude, Bernard Previtali, A. Toffoli, M. Casse, P. Besombes, C. Leroux, Claude Tabone, V. Lapras, A. Laurent, and D. Barge
Subjects: Footprint (electronics), Reduction (complexity), Materials science, Reliability (semiconductor), CMOS, Hardware_INTEGRATEDCIRCUITS, Electronic engineering, Stacking, Three-dimensional integrated circuit, Hardware_PERFORMANCEANDRELIABILITY, Static random-access memory, NMOS logic
Abstract: Stacking N over CMOS devices using 3D Sequential CoolCube™ Integration has been shown promising for the scaling of 6T SRAMs. By transposing one pass-gate and one pull-down NMOS to the top layer, a cell footprint reduction of 27% could be obtained, leading to a 3D vias density over 108/mm2 achievable. In addition, we presented N-type devices fabricated below 630°C yielding quasi-equivalent performances as high temperature ones while fulfilling the PBTI and hot-carrier effects reliability requirements, comforting the viability of N over CMOS approach.
Published: 2017
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10. Some Remarks about the Testing of Reading in a Foreign Language.

Author: Maas-de Brouwer, T. A. and Sluiter, D. M. M. Samson
Abstract: Describes the way foreign languages have been taught in the Netherlands, the way reading comprehension in a foreign language is tested there, and educational objectives that should be taken into consideration in teaching foreign languages. (GT)
Published: 1978

11. Very Low Temperature (Cyclic) Deposition / Etch of In Situ Boron-Doped SiGe Raised Sources and Drains

Author: B. Sermage, C. Sirisopanaporn, A. André, Marc Veillerot, V. Benevent, M.-P. Samson, Sylvain Barraud, J.M. Hartmann, and Z. Essa
Subjects: In situ, Materials science, Chemical engineering, Boron doping, Deposition (chemistry), Electronic, Optical and Magnetic Materials
Published: 2014
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12. Vertically Stacked-NanoWires MOSFETs in a Replacement Metal Gate Process with Inner Spacer and SiGe Source/Drain

Author: N. Rambal, I. Tinti, Zineb Saghi, V. Balan, O. Faynot, G. Audoit, Nicolas Bernier, F. Allain, Christian Arvet, Claude Tabone, Nicolas Posseme, B. Previtalli, Sylvain Barraud, C. Vizioz, J.M. Hartmann, A. Toffoli, E. Augendre, C. Euvrard, L. Gaben, Yves Morand, Patricia Pimenta-Barros, C. Comboroure, V. Lapras, R. Coquand, V. Maffini-Alvaro, Shay Reboh, David Cooper, Laurent Grenouillet, M.-P. Samson, J. Daranlot, Olivier Rozeau, Maud Vinet, Virginie Loup, Laboratoire de Génie Civil et d'Ingénierie Environnementale (LGCIE), Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), STMicroelectronics [Crolles] (ST-CROLLES), Funding : the NANO 2017 program, and European Project: 688101,H2020,H2020-ICT-2015,SUPERAID7(2016)
Subjects: 010302 applied physics, Fabrication, Materials science, Silicon, business.industry, Transistor, Nanowire, chemistry.chemical_element, 02 engineering and technology, 021001 nanoscience & nanotechnology, 01 natural sciences, Silicon-germanium, law.invention, chemistry.chemical_compound, [SPI]Engineering Sciences [physics], chemistry, law, 0103 physical sciences, Electronic engineering, Optoelectronics, Precession electron diffraction, Field-effect transistor, 0210 nano-technology, business, Metal gate
Abstract: International audience; We report on vertically stacked horizontal Si NanoWires (NW) p-MOSFETs fabricated with a replacement metal gate (RMG) process. For the first time, stacked-NWs transistors are integrated with inner spacers and SiGe source-drain (S/D) stressors. Recessed and epitaxially re-grown SiGe(B) S/D junctions are shown to be efficient to inject strain into Si p-channels. The Precession Electron Diffraction (PED) technique, with a nm-scale precision, is used to quantify the deformation and provide useful information about strain fields at different stages of the fabrication process. Finally, a significant compressive strain and excellent short-channel characteristics are demonstrated in stacked-NWs p-FETs.
Published: 2016
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13. Recent advances in low temperature process in view of 3D VLSI integration

Author: N. Rambal, C. Fenouillet-Beranger, X. Garros, G. Cibrario, M.-P. Samson, B. Mathieu, Fabrice Nemouchi, Perrine Batude, C. Guerin, C. Leroux, Laurent Brunet, C-M. V. Lu, Sebastien Kerdiles, O. Billoint, Daniel Benoit, M. Brocard, J. Micout, R. Gassilloud, M. Vinet, Pascal Besson, Bernard Previtali, Christian Arvet, L. Pasini, Sebastien Thuries, V. Lapras, Francois Andrieu, Virginie Loup, F. Deprat, P. Acosta-Alba, V. Beugin, V. Mazzocchi, P. Besombes, and J.M. Hartmann
Subjects: 010302 applied physics, Very-large-scale integration, Materials science, Fabrication, Annealing (metallurgy), Gate stack, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, Dopant Activation, 021001 nanoscience & nanotechnology, Epitaxy, 01 natural sciences, Engineering physics, chemistry.chemical_compound, chemistry, Logic gate, 0103 physical sciences, Silicide, Hardware_INTEGRATEDCIRCUITS, Electronic engineering, 0210 nano-technology
Abstract: In this paper, the recent advances in low temperature process in view of 3D VLSI integration are reviewed. Thanks to the optimization of each low temperature process modules (dopant activation, gate stack, epitaxy, spacer deposition) and silicide stability improvement, the top layer thermal budget fabrication has been decreased in order to satisfy the requirements for 3D VLSI integration.
Published: 2016
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14. Ns laser annealing for junction activation preserving inter-tier interconnections stability within a 3D sequential integration

Author: Bernard Previtali, Laurent Brunet, B. Mathieu, Perrine Batude, J-P. Nieto, L. Pasini, Pascal Besson, I. Toque-Tresonne, F. Aussenac, Fulvio Mazzamuto, P. Acosta-Alba, Sebastien Kerdiles, Karim Huet, J.M. Hartmann, M.-P. Samson, N. Rambal, F. Ibars, R. Kachtouli, M. Vinet, V. Lapras, C. Fenouillet-Beranger, and A. Roman
Subjects: 010302 applied physics, Materials science, Dopant, Silicon, Annealing (metallurgy), business.industry, Recrystallization (metallurgy), chemistry.chemical_element, 02 engineering and technology, Nanosecond, 021001 nanoscience & nanotechnology, Laser, 01 natural sciences, Semiconductor laser theory, law.invention, chemistry, law, 0103 physical sciences, Electronic engineering, Optoelectronics, Process window, 0210 nano-technology, business
Abstract: In this paper, the energy process window of nanosecond (ns) laser annealing for junctions activation has been determined for several dopants (As, P, BF2). The different recrystallization states observed when tuning laser energy density are explained by numerical simulations. Within these conditions, the laser impact on the thermal stability of ULK/copper inter-tiers interconnections has been evaluated for a 28nm node backend metal 1 design rules technology both from morphological and electrical perspectives. This study highlights the interest of ns laser anneal for CoolCube™ 3D integration.
Published: 2016
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15. Integration of Low Temperature 480℃ SiOCN as Offset Spacer in view of 3D Sequential Integration

Author: A. Michallet, C. Bout, J. Fort, T. Skotnicki, V. Beugin, F. Pierre, D. Benoit, L. Brunet, P. Besson, C. Arvet, M.-P. Samson, C. Tabone, N. Rochat, C.-M. V. Lu, V. Loup, Perrine Batude, C. Fenouillet-Beranger, N. Posseme, Bernard Previtali, A. Roule, and M Vinet
Subjects: Offset (computer science), Materials science, business.industry, Optoelectronics, business
Published: 2016
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16. Influence of Low Thermal Budget Plasma Oxidation and Millisecond Laser Anneal on Gate Stack Reliability in view of 3D Sequential Integration

Author: H. Graoui, C. Guedj, R. Gassilloud, Cédric Leroux, C.-M. V. Lu, S. Sharma, M.-P. Samson, T. Skotnicki, R. Kies, Perrine Batude, N. Rambal, Bernard Previtali, C. Fenouillet-Beranger, L. Brunet, A. Toffoli, Sebastien Kerdiles, Xavier Garros, D. Larmagnac, G. Romano, M. Vinet, and N. Bernier
Subjects: Millisecond, Reliability (semiconductor), Materials science, business.industry, law, Thermal, Gate stack, Optoelectronics, Plasma, business, Laser, law.invention
Published: 2016
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17. HSQ Lithography for Nanowire First Integration: an Interesting Alternative for Gate Last Fabrication of Sub-7nm Stacked Nanowire FETs

Author: Thomas Skotnicki, L. Koscianski, M.-P. Samson, S. Pauliac, M. Vinet, J. Bustos, Stephane Monfray, J.-A. Dallery, Frederic Boeuf, Francis Balestra, X. Bossy, L. Gaben, R. Dechanoz, S. Barraud, B. Hemard, STMicroelectronics [Crolles] (ST-CROLLES), Laboratoire d'Electronique et des Technologies de l'Information (CEA-LETI), Université Grenoble Alpes (UGA)-Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Ducroquet, Frédérique, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])
Subjects: Fabrication, Materials science, business.industry, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Nanowire, Optoelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, Lithography, ComputingMilieux_MISCELLANEOUS
Abstract: International audience
Published: 2016

18. Recent advances in 3D VLSI integration

Author: M. Brocard, Perrine Batude, J. Micout, Sebastien Thuries, P. Besombes, V. Mazzocchi, Laurent Brunet, Francois Andrieu, O. Billoint, C. Fenouillet-Beranger, M.-P. Samson, G. Cibrario, M. Vinet, N. Rambal, F. Deprat, Bernard Previtali, and C-M. V. Lu
Subjects: Very-large-scale integration, CMOS, Computer science, Process requirements, Hardware_INTEGRATEDCIRCUITS, Electronic engineering, Silicon on insulator, Wafer, Hardware_PERFORMANCEANDRELIABILITY, Metal gate, Hardware_LOGICDESIGN
Abstract: This work highlights recent advances in 3D VLSI integration. A review of low temperature process modules development such as junctions, spacers and salicidation is presented. Finally, for the first time, a full CMOS over CMOS 3D VLSI integration on 300mm wafers is demonstrated with a top level compatible with state of the art high performance FDSOI (Fully-Depleted Silicon On Insulator) process requirements such as High-k/metal gate or raised source and drain.
Published: 2016
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19. Stacked Nanowires FETs: Mechanical robustness evaluation for sub-7nm nodes

Author: Francis Balestra, Frederic Boeuf, Arthur Arnaud, L. Gaben, Thomas Skotnicki, C. Vizioz, Stephane Monfray, J.M. Hartmann, Marios Barlas, S. Barraud, Christian Arvet, M.-P. Samson, M. Vinet, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), and STMicroelectronics [Crolles] (ST-CROLLES)
Subjects: 010302 applied physics, Materials science, Silicon, Hybrid silicon laser, business.industry, Nanowire, chemistry.chemical_element, Silicon on insulator, Hardware_PERFORMANCEANDRELIABILITY, 01 natural sciences, Silicon-germanium, chemistry.chemical_compound, chemistry, Buckling, Robustness (computer science), Mechanical stability, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, Electronic engineering, Optoelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business
Abstract: session 8: advanced CMOS and New Devices Concepts; International audience; Stacked Nanowires FETs are proposed to replace FinFET and FDSOI for sub-7nm nodes. While most studies demonstrate the performances gain offered by such structures, mechanical stability of the suspended silicon channels needs to be considered. This paper provides a fully mechanical analytical description of nanowire stacks to explain the occurrence of buckling phenomena of silicon channels.
Published: 2016
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20. Thin-film devices for low power applications

Author: L. Clement, J.-L. Huguenin, Frederic Boeuf, J.M. Hartmann, V Destefanis, Thomas Skotnicki, Stephane Denorme, Stephane Monfray, Y. Campidelli, C. Fenouillet-Beranger, Christian Arvet, G. Bidal, O. Faynot, M.-P. Samson, K. Benotmane, and Nicolas Loubet
Subjects: 010302 applied physics, Engineering, business.industry, ComputingMethodologies_IMAGEPROCESSINGANDCOMPUTERVISION, Electrical engineering, Context (language use), 02 engineering and technology, 021001 nanoscience & nanotechnology, Condensed Matter Physics, 01 natural sciences, Electronic, Optical and Magnetic Materials, Power (physics), ComputingMethodologies_PATTERNRECOGNITION, Depletion region, CMOS, Power consumption, Low-power electronics, 0103 physical sciences, Materials Chemistry, Optoelectronics, Node (circuits), Electrical and Electronic Engineering, Thin film, 0210 nano-technology, business
Abstract: Power consumption and matching are the principal issues at the 32 nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present thin-film technologies (FDSOI, LSOI and bulk+) leading to the integration of single gated thin films devices for 22 nm nodes and below.
Published: 2010
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21. Ω-Gate Nanowire Transistors Realized by Sidewall Image Transfer Patterning: 35nm Channel Pitch and Opportunities for Stacked-Nanowires Architectures

Author: Frederic Boeuf, S. Barraud, F. Balestra, F. Alain, T. Skotnicki, B. Previtali, P. Besson, S. Monfray, J. Pradelles, P. Pimenta-Barros, M Vinet, Yves Morand, M.-P. Samson, L. Gaben, Ducroquet, Frédérique, STMicroelectronics [Crolles] (ST-CROLLES), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])
Subjects: Materials science, Image transfer, business.industry, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Nanowire, Optoelectronics, Nanowire transistors, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, Communication channel
Abstract: SSDM Young Researcher Award; International audience
Published: 2016

22. Opportunities and challenges of nanowire-based CMOS technologies

Author: M.-P. Samson, M. Casse, O. Rozeau, L. Gaben, M. Vinet, J. Laccord, F. Glowacki, N. Bernier, Sebastien Martinie, B. De Salvo, V. Maffini-Alvaro, F. Allain, P. Pimenta-Barros, S. Barraud, Phuong Nguyen, J.M. Hartmann, Marie-Anne Jaud, C. Vizioz, Claude Tabone, and Christian Arvet
Subjects: CMOS, Computer science, Emphasis (telecommunications), MOSFET, Hardware_INTEGRATEDCIRCUITS, Nanowire, Electronic engineering, Silicon on insulator, Hardware_PERFORMANCEANDRELIABILITY, Nanowire transistors, Cmos scaling, Hardware_LOGICDESIGN
Abstract: The Nano Wire (NW) CMOS technology is widely considered as a promising evolutionary solution of current FinFET technology. The main advantage of the nanowire transistors for ultimate CMOS scaling is their optimal electrostatic confinement. In this paper, the major assets of NW field-effect-transistors in leading-edge technology nodes are explained in details. For this purpose, electron (hole) transport properties of Si (SiGe) NWs and the critical contribution of strain are discussed. A particular attention is given to the key technological integration challenges to be addressed, with emphasis on the practical implementation of 3D high-density stacked-NWs architectures.
Published: 2015
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23. W and Copper Interconnection Stability for 3D VLSI CoolCube Integration

Author: A. Roman, A. Seignard, Perrine Batude, C. Ribiere, O. Pollet, V. Benevent, E. Gourvest, M.-P. Samson, N. Rambal, Lucile Arnaud, L. Brunet, Hervé Denis, Y. Loquet, M. Vinet, V. Lapras, L. Emery, V. Lu, S. Maitrejean, Vincent Jousseaume, P. Besson, C.Fenouillet Beranger, G. Druais, C.Euvrard Colnat, Bernard Previtali, F. Deprat, R. Kachtouli, S. Kerdiles, Y.Le Friec, and F. Aussenac
Subjects: Very-large-scale integration, Interconnection, Materials science, chemistry, Stability (learning theory), Electronic engineering, chemistry.chemical_element, Copper
Published: 2015
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24. (Invited) Annealing Techniques for Low Temperature Junctions Design in a 3D VLSI Integration

Author: J.P. Barnes, V. Lapras, P. Acosta Alba, N. Rambal, L. Hortemel, F. Piegas Luce, P. Rivallin, Dominique Lafond, Perrine Batude, Pascal Besson, M.-P. Samson, Sebastien Kerdiles, M. Vinet, B. Mathieu, A. Royer, H. Dansas, R. Kachtouli, M. Casse, Shay Reboh, V. Lu, O. Rozeau, L. Pasini, C.Fenouillet Beranger, Bernard Previtali, Laurent Brunet, F. Aussenac, Benoit Sklenard, and F. Deprat
Subjects: Very-large-scale integration, Materials science, Annealing (metallurgy), Engineering physics
Published: 2015
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25. 3DVLSI with CoolCube process: An alternative path to scaling

Author: Maud Vinet, Thomas Signamarcheix, V. Lu, Julie Widiez, Fabien Clermidy, A. Royer, J. Mazurier, M.-P. Samson, F. Piegas-Luce, Fabrice Nemouchi, L. Pasini, J.M. Hartmann, M. Casse, F. Deprat, Laurent Brunet, N. Rambal, Maurice Rivoire, Perceval Coudrain, M. Bidaud, Ogun Turkyilmaz, Hossam Sarhan, F. Ponthenier, G. Ghibaudo, C. Euvard-Colnat, Perrine Batude, Louis Hutin, Sebastien Kerdiles, Claude Tabone, Emmanuel Josse, L. Benaissa, E. Petitprez, Remi Beneyton, Claire Fenouillet-Beranger, L. Hortemel, G. Cibrario, Pascal Besson, A. Seignard, B. Mathieu, F. Fournel, C. Bout, C. Agraffeil, S. Sollier, Michel Haond, O. Billoint, P. Leduc, O. Rozeau, Benoit Sklenard, Sebastien Thuries, Bernard Previtali, O. Faynot, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), STMicroelectronics [Crolles] (ST-CROLLES), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), STMicroelectronics, ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010), European Project: 619325,EC:FP7:ICT,FP7-ICT-2013-11,COMPOSE3(2013), Laboratoire d'Electronique et des Technologies de l'Information (CEA-LETI), Université Grenoble Alpes (UGA)-Direction de Recherche Technologique (CEA) (DRT (CEA)), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), and ANR-10-EQPX-0030/10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010)
Subjects: 010302 applied physics, Very-large-scale integration, Materials science, business.industry, Transistor, Stacking, Electrical engineering, 02 engineering and technology, Direct bonding, Dopant Activation, 01 natural sciences, 7. Clean energy, 020202 computer hardware & architecture, law.invention, law, 0103 physical sciences, MOSFET, 0202 electrical engineering, electronic engineering, information engineering, Optoelectronics, Process optimization, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, Scaling
Abstract: session 5: 3D Systems and Packaging; International audience; 3D VLSI with a CoolCube™ integration allows vertically stacking several layers of devices with a unique connecting via density above a million/mm 2 . This results in increased density with no extra cost associated to transistor scaling, while benefiting from gains in power and performance thanks to wire-length reduction. CoolCube™ technology leads to high performance top transistors with Thermal Budgets (TB) compatible with bottom MOSFET integrity. Key enablers are the dopant activation by Solid Phase Epitaxy (SPE) or nanosecond laser anneal, low temperature epitaxy, low k spacers and direct bonding. New data on the maximal TB bottom MOSFET can withstand (with high temperatures but short durations) offer new opportunities for top MOSFET process optimization.
Published: 2015
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26. P-type trigate nano wires: Impact of nano wire thickness and Si0.7Ge0.3 source-drain epitaxy

Author: M.-P. Samson, Frederic Boeuf, C. Vizioz, J.M. Hartmann, M. Vinet, F. Allain, L. Gaben, Francis Balestra, S. Barraud, S. Montray, F. Aussenac, and Thomas Skotnicki
Subjects: 010302 applied physics, Electron mobility, Materials science, Silicon, business.industry, Nanowire, chemistry.chemical_element, Nanotechnology, Epitaxy, 01 natural sciences, chemistry, 13. Climate action, 0103 physical sciences, Nano, MOSFET, Optoelectronics, business
Abstract: The impact of nanowire (NW) height and Si 0.7 Ge 0.3 :B source-drain (S/D) on the performance of p-type trigate NW is presented. We show that an increase in Si NW height from 14.5nm to 24nm generates up to +30% enhancement in hole effective mobility for a 13nm NW width. Effectiveness of Sio.7Geo.3:B S/D is then discussed for a wide range of NW width (13nm Nw 0.7 Ge 0.3 :B S/D: +86% I on improvement is observed for H Nw =11nm against only +58% for H Nw =24nm.
Published: 2015
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27. Performance of Localized-SOI MOS Devices on (110) Substrates: Impact of Channel Direction

Author: Frederic Boeuf, Yves Morand, M.-P. Samson, Gerard Ghibaudo, J.-L. Huguenin, V. Delaye, P. Gautier, P. Boulitreau, J.M. Hartmann, P. Brianceau, Stephane Monfray, Christian Arvet, Thomas Skotnicki, and V Destefanis
Subjects: Electron mobility, Materials science, Silicon, Subthreshold conduction, business.industry, Transistor, Silicon on insulator, chemistry.chemical_element, Epitaxy, Electronic, Optical and Magnetic Materials, law.invention, chemistry, law, Logic gate, MOSFET, Optoelectronics, Electrical and Electronic Engineering, business
Abstract: In this letter, we demonstrate the optimization of localized silicon-on-insulator and the functionality of devices on (110) silicon substrates. The influence of several channel directions (i.e., 15 °, 30° , 45°, and 60 ° away from the [001] direction) on both hole mobility and electron mobility has been investigated. Finally, the electrical characteristics of 55-nm-gate-length n-channel and p-channel metal-oxide-semiconductor transistors are presented, showing a good subthreshold behavior and confirming the interest of (110) ultrathin body/box devices for low-power applications.
Published: 2011
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28. New insights on bottom layer thermal stability and laser annealing promises for high performance 3D VLSI

Author: S. Chhun, R. Kachtouli, B. Mathieu, F. Aussenac, X. Garros, M. Casse, M.-P. Samson, A. Laurent, J.P. Barnes, L. Pasini, C. Reita, E. Richard, Claire Fenouillet-Beranger, M. Vinet, E. Petitprez, N. Guillot, Pascal Besson, Bernard Previtali, Fabrice Nemouchi, Perrine Batude, Pierre Perreau, V. Benevent, I. Toque-Tresonne, D. Barge, Laurent Brunet, Karim Huet, Sebastien Kerdiles, G. Druais, F. Deprat, H. Dansas, D. Lafond, V. Lu, and N. Rambal
Subjects: Very-large-scale integration, Materials science, business.industry, Doping, Transistor, Laser, law.invention, chemistry.chemical_compound, chemistry, law, MOSFET, Silicide, Electronic engineering, Optoelectronics, Thermal stability, Metal gate, business
Abstract: For the first time the maximum thermal budget of in-situ doped source/drain State Of The Art (SOTA) FDSOI bottom MOSFET transistors is quantified to ensure transistors stability in Sequential 3D (CoolCube™) integration. We highlight no degradation of Ion/Ioff trade-off up to 550°C. Thanks to both metal gate work-function stability especially on short devices and silicide stability improvement, the top MOSFET temperature could be relaxed up to 500°C. Laser anneal is then considered as a promising candidate for junctions activation. Based on in-depth morphological and electrical characterizations it demonstrates very promising results for high performance Sequential 3D integration.
Published: 2014
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29. High mobility w-gate nanowire P-FET on cSGOI substrates obtained by Ge enrichment technique

Author: M. Casse, P. Nguyen, Carlos Mazure, D. Rouchon, N. Bernier, F. Glowacki, J.M. Hartmann, Francois Andrieu, Claude Tabone, Daniel Delprat, V. Maffini-Alvaro, Bich-Yen Nguyen, C. Vizioz, F. Allain, D. Lafond, M. Koyama, M.-P. Samson, O. Faynot, M. Vinet, and S. Barraud
Subjects: Electron mobility, Materials science, business.industry, Transistor, Nanowire, Gate length, Ion current, Substrate (electronics), Electrostatics, law.invention, law, Electronic engineering, Optoelectronics, business
Abstract: Ω-gate nanowires (NW) P-FETs on compressively-strained-SiGe-on-insulator (cSGOI) substrate obtained by the Ge enrichment technique are presented. Effectiveness of cSGOI channel is demonstrated for ultra-scaled P-FET NW (L G =15nm and W NW =25nm) with an outstanding I ON current (I ON =860µA/µm at I OFF =140nA/µm) and a good electrostatics immunity (DIBL=110mV/V). For the first time, Si 0.8 Ge 0.2 -channel transistors highlight a mobility improvement for narrow NWs down to short gate length compared to Si one (92% for L G =30nm). The hole mobility improvement provided by the strong uniaxial compressive strain coming from cSiGe and cCESL leads to an ION current improvement of 95% at L G =15nm.
Published: 2014
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30. Monolithic 3D integration: A powerful alternative to classical 2D scaling

Author: O. Faynot, Ogun Turkyilmaz, F. Deprat, F. Ponthenier, M.-P. Samson, Hossam Sarhan, G. Cibrario, L. Pasini, V. Lu, Claude Tabone, J-E. Michallet, M. Vinet, Perrine Batude, N. Rambal, Fabien Clermidy, O. Billoint, JM Hartmannn, Claire Fenouillet-Beranger, O. Rozeau, Benoit Sklenard, Laurent Brunet, Sebastien Thuries, and Bernard Previtali
Subjects: Engineering, business.industry, law, Scale (chemistry), MOSFET, Transistor, Hardware_INTEGRATEDCIRCUITS, Electrical engineering, Electronic engineering, business, 3d ic design, Scaling, law.invention
Abstract: Monolithic or sequential 3D Integration is a powerful technological enabler for actual 3D IC design as the stacked layers can be connected at the transistor scale. This paper reviews the opportunities brought by M3DI and highlights the applications benefiting from this small 3D contact pitch. It also presents the technological challenges of this concept and offers a general overview of the potential solutions to obtain a high performance low temperature top transistor while keeping bottom MOSFET integrity.
Published: 2014
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31. Strained Silicon Directly on Insulator N- and P-FET nanowire transistors

Author: V. Maffini-Alvarro, Maud Vinet, Romain Lavieville, S. Barraud, M.-P. Samson, M. Casse, Claude Tabone, and F. Allain
Subjects: Materials science, business.industry, Transistor, Nanowire, Electrical engineering, Silicon on insulator, Strained silicon, Insulator (electricity), Electron, law.invention, law, MOSFET, Optoelectronics, Nanowire transistors, business
Abstract: High-performance strained Silicon-On-Insulator (sSOI) nanowire (NW) transistors with gate length and NW width down to 15 nm are reported. We demonstrate sSOI π-Gate n-FET NWs with I ON current of 1410 μA/μm (when I OFF = 70 nA/μm) at V DD =0.9V and a good electrostatic immunity (DIBL = 140 mV/V, SS SAT = 76 mV/dec). Effectiveness of sSOI substrates for n-FETs is shown with an I ON improvement up to +40% at short gate lengths. More generally, size- and orientation-dependent strain impact on electron and hole transport in long and short channel π-Gate (s)SOI NW transistors is systematically studied.
Published: 2014
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32. High Mobility Ω-Gate Nanowire P-FET on cSGOI Substrates Obtained by Ge Enrichment Technique

Author: P Nguyen, S Barraud, M Koyama, M Cassé, F Andrieu, C Tabone, F Glowacki, J.-M Hartmann, V Maffini-Alvaro, D Rouchon, N Bernier, D Lafond, M.-P Samson, F Allain, C Vizioz, D Delprat, B.-Y Nguyen, C Mazuré, O Faynot, and M Vinet
Published: 2014
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33. Scaling of high-kappa/metal-gate TriGate SOI nanowire transistors down to 10 nm width

Author: Daniela Munteanu, Sébastien Barnola, M. Casse, R. Coquand, Pierre Perreau, Claude Tabone, Thierry Poiroux, Sylvain Barraud, C. Comboroure, M.-P. Samson, E. Ernst, V. Maffini-Alvaro, P. Leroux, C. Vizioz, Frederic Boeuf, Gerard Ghibaudo, Stephane Monfray, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), Laboratoire de Génie Civil et d'Ingénierie Environnementale (LGCIE), Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA), Département d'Astrophysique, de physique des Particules, de physique Nucléaire et de l'Instrumentation Associée (DAPNIA), Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), STMicroelectronics [Crolles] (ST-CROLLES), Centre National de la Recherche Scientifique (CNRS)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Université Grenoble Alpes (UGA), Laboratoire d'Electronique et des Technologies de l'Information (CEA-LETI), Université Grenoble Alpes (UGA)-Direction de Recherche Technologique (CEA) (DRT (CEA)), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)
Subjects: 010302 applied physics, Electron mobility, Materials science, business.industry, Nanowire, Silicon on insulator, Nanotechnology, 02 engineering and technology, 021001 nanoscience & nanotechnology, Condensed Matter Physics, 01 natural sciences, Subthreshold slope, Electronic, Optical and Magnetic Materials, Planar, CMOS, 0103 physical sciences, Materials Chemistry, Optoelectronics, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, business, Metal gate, Scaling, ComputingMilieux_MISCELLANEOUS
Abstract: In this paper, TriGate nanowire (TGNW) FETs with high-κ/metal gate are studied as an alternative way to planar devices for the future CMOS technological nodes (14 nm and beyond). The influence of Si film thickness ( H ) and nanowire width ( W ) on electrical performance of long- and short-channel devices are presented and discussed. We show that the transport properties in our TGNW are fully governed by the additive contributions of the (1 0 0) top surface and (1 1 0) sidewalls. As compared to wide planar devices, the improvement of electrostatic integrity (subthreshold slope and drain-induced-barrier-lowering) of scaled down TGNW FET is clearly demonstrated.
Published: 2013
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34. Low-temperature transport characteristics in SOI and sSOI nanowires down to 8nm width: Evidence of IDS and mobility oscillations

Author: R. Coquand, L. Tosti, M. Casse, B. De Salvo, V. Maffini-Alvaro, S. Barraud, X. Mescot, M. Koyama, Stephane Monfray, M.-P. Samson, Frederic Boeuf, Gerard Ghibaudo, and O. Faynot
Subjects: Quantum capacitance, Electron mobility, Materials science, Condensed matter physics, Quantum dot, Nanowire, Induced high electron mobility transistor, Silicon on insulator, Metal gate, Capacitance
Abstract: This paper describes low-field electron transport in nanowire FETs with high-k/metal gate fabricated on 300 mm SOI and strained-SOI substrates. We studied the temperature and size dependences of gate-channel capacitance (C Gc ) and effective mobility (μEFF) down to 8 nm width. We show that the electron mobility is strongly reduced for sub-10 nm widths. Low-temperature measurements show a quantum oscillatory behavior of mobility revealing the electron confinement in 1D subbands structure of nanowires for temperature below 50K.
Published: 2013
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35. Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width

Author: David Cooper, Stephane Monfray, Frederic Boeuf, Gerard Ghibaudo, M. Casse, M.-P. Samson, Thierry Poiroux, Sylvain Barraud, O. Faynot, V. Maffini-Alvaro, R. Coquand, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), Département d'Astrophysique, de physique des Particules, de physique Nucléaire et de l'Instrumentation Associée (DAPNIA), Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), STMicroelectronics [Crolles] (ST-CROLLES), and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)
Subjects: 010302 applied physics, Electron mobility, Lateral strain, Materials science, business.industry, Nanowire, Silicon on insulator, 02 engineering and technology, 021001 nanoscience & nanotechnology, 01 natural sciences, Electronic, Optical and Magnetic Materials, Nanolithography, Strain engineering, Nanoelectronics, 0103 physical sciences, MOSFET, Electronic engineering, Optoelectronics, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, business, ComputingMilieux_MISCELLANEOUS
Abstract: A detailed study of performance in uniaxially strained Si nanowire (NW) transistors fabricated by lateral strain relaxation of biaxial strained-SOI (sSOI) substrate is presented. Two-dimensional strain imaging demonstrates the lateral strain relaxation resulting from nanoscale patterning. An improvement of electron mobility in sSOI NW scaled down to 10-nm width is successfully demonstrated (+55 % with respect to SOI NW) due to remaining uniaxial tensile strain. This improvement is maintained even by using hydrogen annealing to form an Omega gate. For short gate length, a strain-induced ION gain as high as +40% at LG = 45 nm is achieved for a multiple-NW active pattern.
Published: 2013
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36. Scaling of high-k/metal-gate Trigate SOI nanowire transistors down to 10nm width

Author: C. Vizioz, M.-P. Samson, P. Leroux, Pierre Perreau, R. Coquand, V. Maffini-Alvaro, Sébastien Barnola, Daniela Munteanu, E. Ernst, M. Casse, Frederic Boeuf, Gerard Ghibaudo, S. Barraud, Stephane Monfray, C. Comboroure, Claude Tabone, and Thierry Poiroux
Subjects: Electron mobility, Materials science, CMOS, business.industry, Logic gate, Nanowire, Optoelectronics, Silicon on insulator, Nanotechnology, Field-effect transistor, business, Metal gate, High-κ dielectric
Abstract: In this paper, Tri-Gate Nanowire (TGNW) FETs with high-k/metal gate are studied as an alternative way to planar devices for the future CMOS technological nodes (14nm and beyond). The influence of Si film thickness (H) and nanowire width (W) on electrical performances of long- and short-channel devices are presented and discussed. We show that the transport properties in our TGNW are fully governed by the additive contributions of the (100) top surface and (110) sidewalls. As compared to wide planar devices, the improvement of electrostatic integrity (SS and DIBL) of scaled down TGNW FET is clearly demonstrated.
Published: 2012
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37. A solution for an ideal planar multi-gates process for ultimate CMOS?

Author: Francois Leverd, B. Le-Gratiet, C. Borowiak, Thomas Ernst, Frederic Boeuf, L. Pinzelli, S. Barraud, T. Morel, Stephane Denorme, J.-L. Huguenin, Romain Wacquez, Sébastien Barnola, Pascal Gouraud, J. Bustos, G. Bidal, Stephane Monfray, M.-P. Samson, O. Faynot, Jf. Dalemcourt, K. Benotmane, B. Icard, Christian Arvet, Laurent Pain, Y. Campidelli, Thomas Skotnicki, P. Perreau, M. Martin, Remi Beneyton, and C. De-Buttet
Subjects: Very-large-scale integration, Materials science, Silicon, business.industry, Transistor, Electrical engineering, chemistry.chemical_element, Silicon-germanium, law.invention, chemistry.chemical_compound, Planar, CMOS, chemistry, Direct exposure, law, Logic gate, business
Abstract: We demonstrate for the first time high-performant planar multi-gates devices with Si-conduction channel of 4nm, allowing drive current up to 1350µA/µm @I off =0.4nA/µm (V dd =1.1V, CET=1.9nm). But as future multi-gates transistors need to have reduced capacitances and a simple robust process, we also demonstrate in this paper an ideal planar self-aligned solution, based on the direct exposure of a HSQ layer through a 5nm Si-channel. This opens the way to an easy planar multi-gate process for ultimate CMOS (11nm node & below), fully co-integrable with conventional devices.
Published: 2010
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38. Localized SOI Logic and Bulk I/O devices co-integration for Low Power System-on-Chip Technology

Author: C. Borowiak, Stephane Denorme, M.-P. Samson, L. Clement, Francois Leverd, G. Bidal, Sébastien Barnola, F. Abbate, K. Benotmane, Y. Campidelli, C. Fenouillet-Beranger, Thomas Skotnicki, Frederic Boeuf, Gerard Ghibaudo, Stephane Monfray, Dominique Golanski, P. Perreau, J.-L. Huguenin, Nicolas Loubet, STMicroelectronics [Crolles] (ST-CROLLES), Laboratoire de physiopathologie de la nutrition (LPN), Université Paris Diderot - Paris 7 (UPD7)-Centre National de la Recherche Scientifique (CNRS), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), Domenget, Chahla, and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)
Subjects: Materials science, Silicon, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, chemistry.chemical_element, Silicon on insulator, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, 01 natural sciences, law.invention, Stack (abstract data type), law, Low-power electronics, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, Wafer, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS, 010302 applied physics, business.industry, Transistor, Electrical engineering, 021001 nanoscience & nanotechnology, chemistry, Logic gate, Optoelectronics, 0210 nano-technology, Tin, business
Abstract: The objective of this paper is to present the successful co-integration of Logic Ultra-Thin Body and Box (UTBB) devices and bulk-Si I/O devices on the same chip. The UTBB transistors are integrated locally on a Bulk wafer with the Localized Silicon On Insulator (LSOI) process technology with HfO 2 /TiN gate stack for low power applications. I/O co-integrated Bulk devices have a thicker interfacial SiO 2 under the HfO 2 /TiN stack to be compatible with the I/O higher voltage. Both performances of logic UTBB and I/O bulk devices are presented.
Published: 2010

39. Hybrid Localized SOI/Bulk technology for Low Power System-on-Chip

Author: G. Bidal, Ph. Galy, O. Faynot, L. Clement, Frederic Boeuf, A. Bajolet, Antoine Cros, S. Handler, D. Marin-Cudraz, Christian Arvet, Qing Liu, Francois Leverd, Y. Campidelli, Stephane Denorme, Gerard Ghibaudo, F. Abbate, Sébastien Barnola, Stephane Monfray, J.-L. Huguenin, M.-P. Samson, Claire Fenouillet-Beranger, Nicolas Loubet, T. Benoist, K. Benotmane, Thomas Skotnicki, C. Borowiak, P. Perreau, STMicroelectronics [Crolles] (ST-CROLLES), Laboratoire de physiopathologie de la nutrition (LPN), Université Paris Diderot - Paris 7 (UPD7)-Centre National de la Recherche Scientifique (CNRS), Interactions et dynamique des environnements de surface (IDES), Université Paris-Sud - Paris 11 (UP11)-Institut national des sciences de l'Univers (INSU - CNRS)-Centre National de la Recherche Scientifique (CNRS), Science et Ingénierie des Matériaux et Procédés (SIMaP), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Institut de Chimie du CNRS (INC)-Centre National de la Recherche Scientifique (CNRS), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), and Domenget, Chahla
Subjects: 010302 applied physics, Materials science, Electrostatic discharge, business.industry, Electrical engineering, Silicon on insulator, Hardware_PERFORMANCEANDRELIABILITY, Chip, 01 natural sciences, Silicon-germanium, chemistry.chemical_compound, chemistry, [PHYS.COND.CM-GEN] Physics [physics]/Condensed Matter [cond-mat]/Other [cond-mat.other], Logic gate, Low-power electronics, [PHYS.COND.CM-GEN]Physics [physics]/Condensed Matter [cond-mat]/Other [cond-mat.other], 0103 physical sciences, Optoelectronics, System on a chip, Static random-access memory, business, ComputingMilieux_MISCELLANEOUS
Abstract: This paper highlights the successful co-integration of Localized Silicon-On-Insulator (LSOI) devices and of bulk-Si I/O devices on the same chip. LSOI devices present good logic performances and very low mismatch values down to 1.2mV/µm. In addition, we show the backbiasing impact on LSOI SRAM bit-cells for stability improvement. This work also presents the co-integration of LSOI with bulk devices as a solution for the devices that are not compatible with thin-body technology. In particular, we demonstrate for the first time competitive bulk co-integrated ElectroStatic Discharge (ESD) protections.
Published: 2010

40. Ultra-Thin (4nm) Gate-All-Around CMOS devices with High-k/Metal for Low Power Multimedia Applications

Author: Nicolas Loubet, R. Beneyton, T. Morel, Stephane Denorme, L. Pinzelli, B. Le-Gratiet, Francois Leverd, Stephane Monfray, G. Bidal, J.-L. Huguenin, M.-P. Samson, Sébastien Barnola, Aomar Halimaoui, K. Benotmane, Thomas Skotnicki, Frederic Boeuf, C. De-Butet, Gerard Ghibaudo, Christian Arvet, Y. Campidelli, Pascal Gouraud, P. Perreau, STMicroelectronics [Crolles] (ST-CROLLES), Institut d'Astrophysique de Paris (IAP), Université Pierre et Marie Curie - Paris 6 (UPMC)-Institut national des sciences de l'Univers (INSU - CNRS)-Centre National de la Recherche Scientifique (CNRS), Science et Ingénierie des Matériaux et Procédés (SIMaP), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Institut de Chimie du CNRS (INC)-Centre National de la Recherche Scientifique (CNRS), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), and Centre National de la Recherche Scientifique (CNRS)-Institut national des sciences de l'Univers (INSU - CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)
Subjects: 010302 applied physics, Materials science, business.industry, 02 engineering and technology, 021001 nanoscience & nanotechnology, 01 natural sciences, Power (physics), CMOS, [PHYS.COND.CM-GEN]Physics [physics]/Condensed Matter [cond-mat]/Other [cond-mat.other], 0103 physical sciences, Optoelectronics, 0210 nano-technology, business, ComputingMilieux_MISCELLANEOUS, High-κ dielectric
Abstract: International audience
Published: 2010

41. Planar Bulk+ technology using TiN/Hf-based gate stack for low power applications

Author: Thomas Skotnicki, C. Laviron, Pascal Gouraud, Vincent Cosnier, P. Perreau, Jean-Damien Chapon, Stephane Denorme, Sebastien Haendler, T. Salvetat, J. Bougueon, Frederic Boeuf, C. Leyris, Francois Leverd, Mustapha Rafik, G. Bidal, François Martin, Sébastien Barnola, D. Fleury, M. Sellier, Gerard Ghibaudo, Mickael Gros-Jean, M.-P. Samson, D. Chanemougame, L. Clement, M. Marin, Nicolas Loubet, and Stephane Monfray
Subjects: Materials science, Silicon, business.industry, Transistor, Electrical engineering, chemistry.chemical_element, PMOS logic, Silicon-germanium, law.invention, chemistry.chemical_compound, chemistry, law, MOSFET, Optoelectronics, business, Metal gate, NMOS logic, High-κ dielectric
Abstract: This work highlights the new bulk+ technology using high-K dielectric, single metal gate and fully depleted SON (silicon on nothing) channel for sub-45 nm low cost applications. Thin silicon channel (down to Tsi= 8 nm) and thin BOX (Tbox = 15 to 25 nm) are obtained using the SON process (Jurczak, 1999). Transistor performance (Wdesign/Lgate= 90 nm/40 nm) at Vdd = 1.1 V and Ioff < 2 nA/ mum is as high as 1298 muA/ mum for nMOS and 663 muA/ mum for pMOS. In addition, reliability, noise and 6T-SRAM bit cells down to 0.249 mum2 are characterized. Significant improvements with respect to conventional bulk technology are demonstrated.
Published: 2008
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42. Localized SOI technology: an innovative Low Cost self-aligned process for Ultra Thin Si-film on thin BOX integration for Low Power applications

Author: Thomas Ernst, L. Clement, Simon Deleonibus, J.M. Hartmann, F. Allain, A. Quiroga, E. Rouchouze, M.-P. Samson, L. Vandroux, D. Bensahel, Stephane Monfray, D. Chanemougame, J. P. Colonna, Nicolas Loubet, S. Borel, Bernard Guillaumot, Yves Campidelli, A. Margin, Didier Dutartre, Alain Toffoli, D. Renaud, Christian Arvet, Thomas Skotnicki, and G. Rabille
Subjects: Materials science, CMOS, business.industry, Low-power electronics, Electrical engineering, Silicon on insulator, Optoelectronics, Power semiconductor device, business, Metal gate, NMOS logic, Leakage (electronics), PMOS logic
Abstract: In this paper, we demonstrate the first successful integration of "localized SOI" devices integrated with HfO2/TiN gate stack on dedicated areas of bulk CMOS substrates. We propose a low cost innovative approach based on the SON technology, where the buried sacrificial SiGe layer can be removed directly from the edges of the active area in a self-aligned process, to form an entire fully-depleted structure isolated from the substrate. NMOS devices with gate length down to 32 nm are demonstrated on 6 nm Si-films, allowing the control of Ioff current down to 0.1 nA/mum for 440 muA/mum Ion @Vdd=1.1 V. We also demonstrated the impact of the TiN (as metal gate) thickness and compressive CESL (contact etch stop layer) boosters for ultra-thin film PMOS, allowing +15% and +22% additional improvement in performances, respectively. This localized-SOI approach is dedicated to low power devices where the leakage reduction is crucial. The possibility for power management is also demonstrated thank to the very thin buried dielectric and to the ground-plane implantations, allowing body factor as high as 80 mV/Von short devices.
Published: 2007
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43. A Breakthrough Electronic Lithography Process Through Si Layer for Self Aligning Gates in Planar Double-Gate Transistors for 32nm Node And Below

Author: R Wacquez, A. Pouydebasque, B. Guillaumot, Thomas Ernst, Nicolas Loubet, Philippe Coronel, L. Clement, J. Bustos, M.-P. Samson, Pascal Masson, Vincent Delaye, Thomas Skotnicki, J P Gouy, L Baud, and D. Delille
Subjects: Planar, Materials science, business.industry, law, Node (networking), Transistor, Optoelectronics, Double gate, Nanotechnology, Lithography process, business, Layer (electronics), law.invention
Published: 2007
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44. A Novel Self Aligned Design Adapted Gate All Around (SADAGAA) MOSFET including two stacked Channels: A High Co-Integration Potential

Author: R Wacquez, Antoine Cros, Robin Cerutti, Philippe Coronel, Damien Lenoble, Pascal Masson, F. Judong, Nicolas Loubet, S. Harrison, Thomas Ernst, B. Guillaumot, D. Fleury, D. Delille, Thomas Skotnicki, M.-P. Samson, Francois Leverd, N. Vuillet, J. Bustos, S. Borel, A. Pouydebasque, Département Mécanismes d'Accidents (INRETS/MA), Institut National de Recherche sur les Transports et leur Sécurité (INRETS), STMicroelectronics [Crolles] (ST-CROLLES), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Laboratoire d'Electronique, Antennes et Télécommunications (LEAT), Université Nice Sophia Antipolis (1965 - 2019) (UNS), COMUE Université Côte d'Azur (2015-2019) (COMUE UCA)-COMUE Université Côte d'Azur (2015-2019) (COMUE UCA)-Centre National de la Recherche Scientifique (CNRS), gaffé-clément, sophie, and Université Nice Sophia Antipolis (... - 2019) (UNS)
Subjects: 010302 applied physics, Materials science, business.industry, [SPI.ELEC] Engineering Sciences [physics]/Electromagnetism, Nanotechnology, 02 engineering and technology, 021001 nanoscience & nanotechnology, 01 natural sciences, [SPI.ELEC]Engineering Sciences [physics]/Electromagnetism, 0103 physical sciences, MOSFET, Optoelectronics, 0210 nano-technology, business, ComputingMilieux_MISCELLANEOUS
Abstract: International audience
Published: 2006

45. Metal gate-all-around CMOS integration using poly-gate replacement through contact hole (PRETCH)

Author: Robin Cerutti, D. Delille, Philippe Coronel, J. Bustos, Antoine Cros, M.-P. Samson, Romain Wacquez, Alexandre Talbot, S. Harrison, S. Borel, Thomas Skotnicki, Francois Leverd, F. Balestra, and A. Pouydebasque
Subjects: Materials science, Pass transistor logic, business.industry, Polysilicon depletion effect, Electrical engineering, NAND gate, Hardware_PERFORMANCEANDRELIABILITY, CMOS, Gate oxide, MOSFET, Hardware_INTEGRATEDCIRCUITS, Optoelectronics, business, Metal gate, Gate equivalent, Hardware_LOGICDESIGN
Abstract: In this paper, the authors presented an integration strategy for metal gate GAA transistors made by SON process using poly-gate replacement through contact hole (PRETCH). Double gate (DG) type MOSFETs, including planar DG gate-all-around and fin-FETs are today known as the best candidates for the ultimate sealing of the logic CMOS technologies on silicon. One of the main difficulties in optimizing DG devices is the control of the threshold voltage (V/sub th/) from high performances to low power devices. With polysilicon gates, a higher channel doping has to be used when lowering the silicon thickness (T/sub Si/). This adjustment strategy has its limits and thus, gate workfunction engineering seems necessary for thin DG transistors.
Published: 2005
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46. Highly performant double gate MOSFET realized with SON process

Author: Jean-Luc Autran, Francois Leverd, Robin Cerutti, H. Brut, Yves Morand, S. Jullian, M.-P. Samson, Damien Lenoble, Thomas Skotnicki, Stephane Monfray, Daniela Munteanu, Alexandre Villaret, D. Delille, Didier Dutartre, Pascale Mazoyer, Philippe Coronel, R. Palla, Antoine Cros, Alexandre Talbot, S. Harrison, S. Borel, S. Descombes, J. Bustos, Roland Pantel, Munteanu, Daniela, Institut des Matériaux, de Microélectronique et des Nanosciences de Provence (IM2NP), Université de Toulon (UTLN)-Centre National de la Recherche Scientifique (CNRS)-Aix Marseille Université (AMU), STMicroelectronics [Crolles] (ST-CROLLES), and Aix Marseille Université (AMU)-Université de Toulon (UTLN)-Centre National de la Recherche Scientifique (CNRS)
Subjects: 010302 applied physics, Physics, Silicon, business.industry, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, chemistry.chemical_element, 02 engineering and technology, 021001 nanoscience & nanotechnology, 01 natural sciences, chemistry, Low-power electronics, 0103 physical sciences, MOSFET, Optoelectronics, Double gate, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, business
Abstract: IEEE International Electron Devices Meeting, WASHINGTON, D.C., DEC 08-10, 2003; International audience; Utilizing the SON (Silicon On Nothing) process, highly performant double gate devices have been processed in a planar configuration. Two families of devices were obtained (High Performance and Low Power) with very-high Ion/Ioff trade off. Drive currents of 1954muA/mum (Ioff = 283 nA/mum) and 1333 muA/mum (Ioff = 1 nA/mum) are obtained @1.2V with Tox = 20A and Lgate = 70nm. DIBL is very well controlled, measured below 60mV for gates as short as 40nm. These features place our devices among the most performant ever reported.
Published: 2004
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47. Poly-gate replacement through contact hole (PRETCH): A new method for high-K/metal gate and multi-oxide implementation on chip

Author: D. Barge, A. Beverina, Thomas Skotnicki, Philippe Coronel, J.L. Autran, S. Harrison, Antoine Cros, J. Bienacel, D. Delille, Romain Wacquez, Francois Leverd, M.-P. Samson, Robin Cerutti, J. Bustos, S. Maitrejean, Daniela Munteanu, F. Martin, B. Tavel, Institut des Matériaux, de Microélectronique et des Nanosciences de Provence (IM2NP), Université de Toulon (UTLN)-Centre National de la Recherche Scientifique (CNRS)-Aix Marseille Université (AMU), STMicroelectronics [Crolles] (ST-CROLLES), and Aix Marseille Université (AMU)-Université de Toulon (UTLN)-Centre National de la Recherche Scientifique (CNRS)
Subjects: 010302 applied physics, Engineering, OR gate, business.industry, Gate dielectric, Electrical engineering, NAND gate, Time-dependent gate oxide breakdown, 02 engineering and technology, 021001 nanoscience & nanotechnology, 7. Clean energy, 01 natural sciences, Gate oxide, 0103 physical sciences, Optoelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, business, Metal gate, Gate equivalent, NMOS logic
Abstract: 50th IEEE International Electron Devices Meeting, San Francisco, CA, DEC 13-15, 2004; International audience; We report on a new concept for an easy co-integration, on a same chip, of different MOSFET configurations (GP, LP, HS, buffer transistors) realized after the end of the standard FE process. This Poly-gate Replacement Through Contact Hole PRETCH) concept enables replacement of initial poly-silicon gate and/or gate oxide by any gate stack desired. PRETCH addresses multi-Vt control, multi-oxide realization and metal gate integration challenges. As PRETCH gate replacement takes place after PMD (beginning of BE), it is perfectly suitable for High-K integration, allowing low thermal budget (no source and drain anneal seen by HK) and no particular contamination issues. Large potential of PRETCH integration is confirmed by promising morphological results and by very good electrical characteristics of both nMOS and pMOS TiN 90nm gate length MOSFETs. Integration of TiN gate with three different oxide configurations is demonstrated: initial thermal oxide left, replaced by either Slot Plane Antenna [SPA] oxide or High-K. PRETCH concept has also been validated on 3D architectures such as DG. Finally, functional TiN DG inverters and SRAMs are demonstrated.
Published: 2004
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48. Fabrication, structural and electrical properties of (1 1 0) localized silicon-on-insulator devices

Author: P. Boulitreau, V Destefanis, J.M. Hartmann, P. Gautier, Thomas Skotnicki, Christian Arvet, P. Brianceau, Vincent Delaye, Stephane Monfray, M.-P. Samson, J.-L. Huguenin, and Yves Morand
Subjects: Electron mobility, Fabrication, Analytical chemistry, Silicon on insulator, Nanotechnology, Partial pressure, Condensed Matter Physics, Epitaxy, Electronic, Optical and Magnetic Materials, Etching (microfabrication), Materials Chemistry, Wafer, Growth rate, Electrical and Electronic Engineering
Abstract: The aim being to fabricate (1 1 0) localized silicon-on-insulator (L-SOI) devices, we have first of all completed the Semicond. Sci. Technol. 23 105018 (2008) study of the differences between (1 1 0) and (1 0 0) surfaces in terms of (i) HCl etch kinetics and (ii) SiGe growth kinetics (with a chlorinated chemistry). The core layers of a L-SOI device are indeed obtained thanks to the in situ HCl etching (on patterned wafers) of the Si active areas followed by the selective epitaxial growth of a Si0.7Ge0.3/Si stack. Given that SiGe(1 1 0) layers grown at 650 °C in windows of patterned wafers are rough, we have first of all studied the 600 °C growth kinetics of SiGe(1 1 0). As expected, the SiGe growth rate decreases as the growth temperature decreases from 650 °C down to 600 °C (irrespective of the surface orientation). The SiGe(1 0 0) growth rate increases linearly with the germane mass flow. Meanwhile, the SiGe(1 1 0) growth rate increases in a sub-linear fashion and then saturates at much lower values than on (1 0 0). The Ge concentration x dependence on the F(GeH4)/F(SiH2Cl2) mass flow ratio is parabolic on (1 0 0) and linear on (1 1 0), with lower values on the latter than on the former. We have then used those data to fabricate (1 0 0) and (1 1 0) L-SOI structures. The high HCl partial pressure recessing of the Si(1 1 0) and Si(1 0 0) active areas was performed at 675 °C and 725 °C, respectively. An increase of both the Si(1 1 0) HCl etch rate and the SiGe growth rate (be it at 650 °C on (1 0 0) or at 600 °C on (1 1 0)) was noticed when switching from blanket to patterned wafers (factors of 2.5–3 for HCI and 1.5 for SiGe). Finally, Si(1 1 0) growth times were multiplied by 4/3 compared to the Si(1 0 0) growth time in order to obtain similar thickness Si caps. Subsequent process steps were very similar on (1 0 0) and (1 1 0). Almost the same etch rates were notably obtained for the lateral etching of the (1 1 0) and (1 0 0) SiGe sacrificial layers (thanks to a CF4-based dry plasma), with no anisotropy. Significant hole mobility gains (electron mobility loss) compared to the universal Si(1 0 0)/SiO2 mobility were evidenced in long, narrow (L = 10 µm; W = 0.08 µm) 'bulk-like' epitaxial Si(1 1 0) L-SOI devices (i.e. with SiGe still present under most of the Si channel). The gain (the loss) monotonically increased from 120% (11%) up to 246% (58%) when moving away from the [0 0 1] direction toward the [1 −1 0] direction (not reached, however: at most at 60° to [0 0 1]). Vastly improved hole transport properties (a factor of 2 On current increase) were evidenced in short dimensions L-SOI devices (L = 0.35 µm; W = 0.08 µm) when switching from (1 0 0) surfaces with 1 1 0 conduction channels to (1 1 0) surfaces with a [0 0 1] propagation direction for the holes.
Published: 2010
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49. SON (Silicon-On-Nothing) technological CMOS Platform: Highly performant devices and SRAM cells

Author: Alexandre Talbot, Nathalie Vulliet, Stephane Monfray, Thomas Skotnicki, A. Vandooren, Nicolas Planes, R. Palla, Yves Morand, D. Delille, S. Borel, Francois Leverd, M.-P. Samson, T. Sparks, Didier Dutartre, D. Chanemougame, and S. Descombes
Subjects: Physics, Silicon, business.industry, Electrical engineering, Silicon on insulator, chemistry.chemical_element, PMOS logic, CMOS, chemistry, Static noise margin, Static random-access memory, business, NMOS logic, Electronic circuit
Abstract: In this paper, we demonstrate for the first time full integration of highly performant NMOS and PMOS silicon-on-nothing (SON) devices into circuits. We demonstrated fully functional SRAMs cells with very good yield, showing static noise margin (SNM) of 175mV and write margin (WM, stable "read 0") above 500mV. The optimized SON devices show performance for NMOS and for PMOS that is among the best published data (with drive current up to 1100/350/spl mu/A//spl mu/m for 138/20nA//spl mu/m I/sub off/ for NMOS and PMOS devices respectively @V/sub dd/=1.2V, I/sub ox/=16A). Finally, we present also the implementation of the SON process into a new "localized SOI" architecture on bulk. This new and simplified SON process is also demonstrated by fully operational SRAM cells.

50. 3D Sequential Integration: Application-driven technological achievements and guidelines

Author: C. Comboroure, M. Zussy, L. Pasini, N. Rambal, J.-B. Pin, François Martin, V. Balan, Perrine Batude, C. Vizioz, J.M. Hartmann, Virginie Loup, N. Allouti, Sébastien Barnola, A. Duboust, Frédéric Mazen, O. Faynot, Louis Hutin, Mazzocchi, R. Berthelon, A. Ayres, Gilles Sicard, F. Deprat, Sebastien Hentz, J.-P. Colinge, Francois Andrieu, B. Mathieu, S. Beaurepaire, J. Micout, F. Ponthenier, E. Vianello, F. Fournel, O. Rozeau, E. Avelar Mercado, V. Ripoche, V. Beugin, Cristiano Santos, M.-P. Samson, Pascal Vivet, D. Larmagnac, S. Barraud, C. Euvrard-Colnat, Sebastien Kerdiles, M. Vinet, Benoit Sklenard, P. Acosta Alba, Sebastien Thuries, C. Fenouillet-Beranger, Philippe Rodriguez, X. Garros, Fabrice Nemouchi, R. Gassilloud, O. Billoint, Julien Arcamone, Pascal Besson, Didier Lattard, M. Casse, Laurent Brunet, C.-M. V. Lu, and Bernard Previtali
Subjects: 010302 applied physics, Materials science, Silicon, Interface (computing), Stacking, chemistry.chemical_element, Ranging, 02 engineering and technology, 021001 nanoscience & nanotechnology, 01 natural sciences, 7. Clean energy, Engineering physics, Annealing (glass), chemistry, 0103 physical sciences, Thermal, Hardware_INTEGRATEDCIRCUITS, Field-effect transistor, Thermal stability, 0210 nano-technology
Abstract: 3D Sequential Integration (3DSI) with ultra-small 3D contact pitch (
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