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In this paper, we have studied the stability of polymorphous silicon (pm-Si:H) and μc-Si:F:H bottom gate thin-film transistors (TFTs) by combining degradation and relaxation experiments under various stress conditions. We report on polymorphous silicon (pm-Si:H) TFTs with ΔVTH=1 V after 10 h of stress and μc-Si:F:H TFTs with superior stability, which show a ΔVTH of only 0.05 V under stress conditions similar to those encountered in active-matrix operation regime (VG=12 V and VD=10 V). Relaxation studies show that the quality of the interface between silicon nitride and pm-Si:H (or μc-Si:F:H) controls the stability at short stress times. Interestingly, the deposition conditions of the semiconductor layer seem to modify the quality of the a-SiN:H and thus the stability of the interface.

Bottom-gated n-channel thin-film transistors (TFTs) were fabricated, using as channel material hydrogenated amorphous silicon (a-Si:H)/nanocrystalline silicon (nc-Si:H) bilayers, deposited at 230 °C by plasma-enhanced chemical vapor deposition, and SiN x as gate dielectric. The stability of these devices is investigated under three bias stress conditions: (i) gate bias stress ( V G = 25 V, V D = 0), (ii) on-state bias stress ( V G = 25 V, V D = 20 V) and (iii) off-state bias stress ( V G = −25 V, V D = 20 V). It is found that the TFT degradation mechanisms are strongly dependent on the bias stress conditions, involving generation of deep and tail states in the active area of the channel material, carrier injection (electrons or holes) within the gate insulator and generation of donor trap states at the gate insulator/channel interface. The common features and the differences observed in the degradation behaviour under the different bias stress conditions are discussed.

Bottom gate microcrystalline silicon thin film transistors (μc-Si:H TFT) have been fabricated at three different deposition temperatures (150, 200 and 250 °C) for the μc-Si layer. We found that the linear field effect mobility increases from 0.1 to 0.44 cm 2 /V s by decreasing the temperature from 250 °C to 150 °C, and that the leakage current of TFTs with μc-Si deposited at 150 °C is lower than that of μc-Si:H deposited at 250 °C. Moreover, there is no influence of the deposition temperature on the stability of μc-Si:H TFTs. The improvement of the electrical characteristics at lower deposition temperatures is discussed in terms of a lower concentration of donor active oxygen atoms at lower temperature.

Bottom gate microcrystalline silicon thin film transistors (μc-Si TFT) have been realized with two types of films: μc-Si(1) and μc-Si(2) with crystalline fraction of 80% and close to 100% respectively. On these TFTs we applied two types of passivation (SiN x and resist). μc-Si TFTs with resist as a passivation layer present a low leakage current of about 2.10 − 12 A for V G = − 10 and V D = 0.1V an ON to OFF current ratio of 10 6 , a threshold voltage of 7 V, a linear mobility of 0.1 cm 2 /V s, and a sub-threshold voltage of 0.9 V/dec. Microcrystalline silicon TFTs with SiN x as a passivation present a new phenomenon: a parasitic current for negative gate voltage (− 15 V) causes a bump and changes the shape of the sub-threshold region. This excess current can be explained by and oxygen contamination at the back interface.

Bottom-gated n-channel thin-film transistors (TFTs) were fabricated on amorphous silicon (a-Si)/nanocrystalline silicon (nc-Si) bilayers, deposited at 230 °C by plasma-enhanced chemical vapour deposition. The impact of the channel length on the electrical and low-frequency noise characteristics of the TFTs is investigated. The results show that the 1/ f noise can be interpreted in terms of carrier number fluctuations, except the long channel devices where the 1/ f noise is interpreted in terms of the Hooge’s mobility fluctuations model at low drain currents. The gate insulator trap density has been evaluated, demonstrating that the nc-Si extended underneath the n + drain contact area contributes to the measured noise.

The effect of the channel width dimension on the electrical characteristics of amorphous/nanocrystalline silicon bilayer thin-film transistors (TFTs) is investigated. For comparison, nanocrystalline silicon monolayer TFTs are also studied. The experimental results show that the leakage current is decreased and the back-channel conduction is suppressed in bilayer channel devices. The overall results demonstrate that the performance of bilayer TFTs is enhanced with decreasing the channel width, which is attributed to the corner effect

The static bias-stress-induced degradation of hydrogenated amorphous/nanocrystalline silicon bilayer bottom-gate thin-film transistors is investigated by monitoring the turn-on voltage (V on) and on-state current (I on) in the linear region of operation. Devices of constant channel length 10 mum and channel width varying from 3 to 400 mum are compared. The experimental results demonstrate that the device degradation is channel-width dependent. In wide channel devices, substantial degradation of V on is observed, attributed to electron injection into the gate dielectric, followed by I on reduction due to carrier scattering by the stress-induced gate insulator trapped charge. With shrinking the channel width down to 3 mum, the device stability is substantially improved due to the possible reduction of the electron thermal velocity during stress or due to the gate insulator quality uniformity over small dimensions.

Bottom-gated n-channel thin-film transistors (TFTs) were fabricated using hydrogenated amorphous-silicon (a-Si:H)/ nanocrystalline silicon (nc-Si:H) bilayers as channel materials, which are deposited by plasma-enhanced chemical vapor deposition at low temperatures. The stability of these devices is investigated under static and dynamic bias stress conditions. For comparison, the stability of a-Si:H and nc-Si:H single-layer TFTs is investigated under similar bias stress conditions. The overall results demonstrate that the a-Si:H/nc-Si:H bilayer TFTs are superior compared with their counterparts of a-Si:H and nc-Si:H TFTs regarding device performance and stability.

The drain leakage current in n-channel bottom-gated nanocrystalline silicon (nc-Si) thin-film transistors is investigated systematically by conduction and low-frequency noise measurements. The presented results indicate that the leakage current, controlled by the reverse biased drain junction, is due to Poole-Frenkel emission at low electric fields and band-to-band tunneling at large electric fields. The leakage current is correlated with single-energy traps and deep grain boundary trap levels with a uniform energy distribution in the band gap of the nc-Si. Analysis of the leakage current noise spectra indicates that the grain boundary trap density of 8.5 times 1012 cm -2 in the upper part of the nc-Si film is reduced to 2.1 times 1012 cm-2 in the lower part of the film, which is attributed to a contamination of the nc-Si bulk by oxygen

A simple analytical expression for the above threshold voltage drain current is derived in nanocrystalline silicon thin-film transistors (TFTs), based on an exponential energy distribution of band tail states. When the characteristic temperature distribution of the band tails is equal to 1.5 times the lattice temperature, the derived expression leads to the basic “quadratic” metal-oxide-semiconductor current expression. By including the impact ionization effect and using the same trap distribution parameters, the model describes adequately the output characteristics of TFTs with different channel dimensions, making the proposed model suitable for the design of circuits with nc-Si TFTs.

We report on a guided growth of silicon nanowires (SiNWs) based on an in-plane solid-liquid-solid mechanism, which provides a general strategy to deploy SiNWs precisely into desired circuits. During a reacting-gas-free annealing process, the SiNWs are activated to grow and be guided into predefined patterns by effective controlling the movement of the catalyst drops. We demonstrate three different approaches to achieve a guided growth of SiNWs, which are as follows: (1) by an a-Si: H channel, (2) by a step edge, and (3) by an a-Si : H edge. These results provide a design principle for future SiNWs-based nanodevices. (C) 2009 American Institute of Physics.

Nanocrystalline silicon thin-film transistors present technological interest in that they combine many of the advantages of amorphous with those of polycrystalline Si structures. Progress in practical implementation of this technology is hampered by limited understanding of the conduction mechanisms in these structures and of the underlying relationship between device behavior and process manufacturing parameters. These mechanisms are explored through detailed simulation that includes model calibration and correlation with experimental results, as well as parametric sensitivity evaluation of this class of devices over the entire range of applied voltage. Through fitting of the tests results, a unique set of density of states was identified that characterizes the particular technology used. The leakage current was attributed to the band to band tunneling and thermal generation-recombination mechanisms. For devices with channel length of less than 20μm, the kink effect was observed in the output characteris...

The stability of n-channel bottom-gated thin-film transistors (TFTs), fabricated using as channel material hydrogenated amorphous silicon∕nanocrystalline silicon bilayers, is investigated by applying on the gate pulses in the on-state and off-state regions of operation and dc bias on the drain electrode. Dynamic gate stress, with the source and drain electrodes grounded, were also performed to avoid the effect of dc stress during the dynamic stress. The degradation mechanisms are thoroughly studied for each type of stress conditions, including carrier injection in the SiNx gate insulator and generation of traps at the gate insulator∕channel interface and in the active channel material. The common features and the differences in the TFT degradation behavior under different bias stress conditions are discussed.

The mechanisms of threshold voltage (Vth) drift in nanocrystalline silicon (nc-Si:H) TFTs have been investigated. Using bias-temperature stress measurements, it is found that the dominant mechanism of Vth drift is charge trapping in the SiNx gate insulator. This result is confirmed by a study on ambipolar nc-Si:H:TFTs. Comparing with a-Si:H TFTs, this means that the reduction of the voltage shift in nc-Si:H TFTs is the result of an improvement of the semiconductor material.

An analytical model for the drain current above threshold voltage, based on an exponential energy distribution of band tail states, has been applied to bottom-gated nanocrystalline silicon (nc-Si) thin-film transistors (TFTs). Analysis of the model shows that the slope of the exponential band tails determines the behavior of the device current-voltage characteristics. Comparison with experimental data shows that few fundamental model parameters, related to the material quality and different physical effects, can be used to describe consistently both output and transfer characteristics of nc-Si TFTs over a wide range of channel lengths.

Bottom-gated n-channel thin-film transistors were fabricated on nanocrystalline silicon (nc-Si) layers, deposited at 230°C by plasma-enhanced chemical vapor deposition. The transfer characteristics were measured in devices with different channel dimensions, exhibiting front and back channel conduction. The change of the device parameters with channel dimensions is explained in terms of the trap density in the bulk of the nc-Si layer extracted from space charge limited current measurements in n+‐nc‐Si‐n+ structures and both front∕back interface traps determined from the slopes associated with the front and back channel conduction. The overall results suggest the existence of regions of high trap density at the back interface near the source and drain n+ contacts, whereas the reduction of the back channel conduction with decreasing the channel width can be attributed to the sidewall edge effect. The gate insulator trap concentration of 1.5×1019cm−3eV−1 was deduced from the noise data.