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A compact probe for charged particle imaging, with potential applications in source activity mapping and radio-guided surgery was designed and tested. The development of this technology holds significant implications for medical imaging, offering healthcare professionals accurate and efficient tools for diagnoses and treatments. To fulfill the portability requirements of these applications, the probe was designed for battery operation and wireless communication with a PC. The core sensor is a dual-layer CMOS SPAD detector, fabricated using 150 nm technology, which uses overlapping cells to produce a coincidence signal and reduce the dark count rate (DCR). The sensor is managed and interfaced with a microcontroller, and custom firmware was developed to facilitate communication with the sensor. The performance of the probe was evaluated by characterizing the on-board SPAD detector in terms of the DCR, and the results were consistent with the characterization measurements taken on the same chip samples using a purposely developed benchtop setup.

Dark count rate (DCR) increase in CMOS single-photon avalanche diodes (SPADs) exposed to a nonmonochromatic neutron source is modeled, taking into account the source spectrum and the geometry of the device under test. Experimental results from the characterization of SPADs fabricated in a 150-nm technology and irradiated with 1-MeV neutron equivalent fluences up to $10^{\textsf {11}}$ cm $^{-\textsf {2}}$ are found to be in good agreement with the theoretically calculated distribution of the nonionizing energy deposited in the device substrate.

In this paper we present a position-sensitive detector based on the vertical integration of pairs of aligned pixels operating in Geiger-mode regime and designed for charged particle detection. This novel device exploits the coincidence between two simultaneous avalanche events to discriminate between particle-triggered detections and dark counts. This concept allows to have a reduced material budget and low power consumption in spite of a high granularity and fast timing response. A proof-of-principle prototype was designed and fabricated in a 150 nm CMOS process and vertically integrated through bump bonding. This first demonstrator has been characterized and tested with a high energy particle beams at CERN SPS/PS facilities, in different configurations, featuring a reduction of the dark-count rate (DCR) at room temperature from ∼ 100 kHz/mm 2 to about 24 Hz/mm 2 a particle detection efficiency limited only by the geometric factor. The device radiation tolerance has been investigated, via irradiation of single tiers with 10 keV X-rays up to a dose of 1 Mrad (SiO2) and with neutrons up to a fluence of 1011 cm−2. A second prototype, addressing the goal to improve the present fill-factor, has been designed, manufactured and approaches now the characterization phase. Potential applications of this sensor include high spatial resolution tracking in high-energy experiments, radiation monitoring in space and radiation imaging in nuclear medicine. A small hand-held demonstrator is under construction for radio-guided surgery.

This work is concerned with the design and the characterization of digital-to-analog current converters, developed in a 65 nm CMOS technology, conceived for threshold tuning of front-end channels at the High-Luminosity LHC experiment upgrades. Two DAC designs were integrated in a small prototype chip, that was submitted in August 2018 in the framework of the RD53 developments. One of the DAC designs features a binary weighted architecture implemented with cascoded current mirrors and no dummy transistors, whereas the second one, sharing the same architecture, exploits regular current mirrors with dummy transistors. The prototype has been tested before and after exposure to X-rays up to a TID of 460 Mrad(SiO2). The main performance parameters of the two structures, namely DAC dynamic range, INL and DNL, are compared and discussed in the paper.

Single-photon avalanche diodes (SPADs) fabricated using two different CMOS technologies were exposed to a neutron source up to a maximum fluence of $3\times 10^{11}\,\,1$ -MeV neutron equivalent cm−2. Significant changes in the dark count rate (DCR), with a strong dependence on the fluence and the device active area, were detected after irradiation. A model for the probability of DCR degradation, accounting for the source spectrum and the geometry of the device under test (DUT), was proposed and proved to be in good agreement with experimental data. The model may be helpful in performing worst-case analysis of SPAD-based detection systems under neutron irradiation.

This work is concerned with the characterization of a bandgap reference circuit, fabricated in a commercial 65 nm CMOS technology, designed for applications to HL-LHC experiments. Measurement results show a temperature coefficient of about 16 ppm/\(^\circ \)C over a temperature range of 140 \(^\circ \)C (from \(-40\) to 100 \(^\circ \)C) and a variation of 1.6% for V\(_{DD}\) from 1.08 to 1.32 V. The mean value of the bandgap output is about 400 mV, with a 5% maximum shift when exposed to a Total Ionizing Dose (TID) around 1 Grad (SiO\(_2\)). The power consumption is 165 \(\upmu \)W at room temperature, with a core area of 0.02835 mm\(^2\).

This paper is focused on the study of the noise performance of 65 nm CMOS transistors at extremely high total ionizing dose (TID) levels of the order of several hundreds of Mrad(SiO2). Noise measurements are reported and discussed, analyzing radiation effects on $1/f$ noise and channel thermal noise. In nMOSFETs, up to 10 Mrad(SiO2), the experimental behavior is consistent with a damage mechanism mainly associated with lateral isolation oxides, and can be modeled by parasitic transistors turning on after irradiation and contributing to the total noise of the device. At very high dose, these parasitic transistors tend to be turned off by negative charge accumulating in interface states and compensating radiation-induced positive charge building up inside thick isolation oxides. Effects associated with ionization and hydrogen transport in spacer oxides may become dominant at 600 Mrad(SiO2) and may explain the observed noise behavior at extremely high TID. The results of this analysis provide an understanding of noise degradation effects in analog front-end circuits integrated in readout chips for pixel detectors operating in very harsh radiation environments such as the High-Luminosity Large Hadron Collider.

This paper presents the first experimental demonstration of a pixelated two-layer Geiger-mode avalanche sensor designed for the direct detection of charged particles. In the proposed device, each pixel is formed by two vertically aligned avalanche detectors, exploiting the coincidence between two simultaneous avalanche events to discriminate between the detection of particles and dark counts. A 48 $\times $ 16 pixel array has been designed and fabricated in a 150-nm CMOS process and vertically integrated through bump bonding. The pixel, that includes passive quenching, comparator, and digital electronic circuits for coincidence processing and signal storage, has a size of 50 $\mu \text{m} \,\, \times $ 75 $\mu \text{m}$ and a maximum fill factor of 51.6%. The operation of the particle sensor has been validated with the measurement of dark count rate distribution at different coincidence resolution times. An average dark count rate per pixel as low as 93 mHz, corresponding to 24 Hz/mm2, was obtained at room temperature. A first sensor validation using a 90Sr $\beta $ source is presented.

International audience; Next generation pixel chips at the High-Luminosity (HL) LHC will be exposed to extremely high levels of radiation and particle rates. In the so-called Phase II upgrade, ATLAS and CMS will need a completely new tracker detector, complying with the very demanding operating conditions and the delivered luminosity (up to 5×10 34 cm −2 s −1 in the next decade). This work is concerned with the design of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier featuring a detector leakage compensation circuit, and a compact, single ended comparator that guarantees very good performance in terms of channel-to-channel dispersion of threshold without needing any pixel-level trimming. A flash ADC is exploited for digital conversion immediately after the charge amplifier. A thorough discussion on the design of the charge amplifier and the comparator is provided along with an exhaustive set of simulation results.

N- and P-type transistors from a 14 nm finFET technology have been tested from the standpoint of static current-voltage characteristics, small signal parameters and noise properties in view of analog front-end applications. Device electrical features are found to be compliant with the scaling trend as carried on with planar CMOS technologies. Comparison with standard, less scaled bulk CMOS processes points out that transition from planar, single-gate to vertical, multiple-gate structures does not affect significantly the device analog performance. The paper will focus in particular on the noise properties of the transistors, featuring different gate length and width and operated in the weak to moderate inversion region.

In the framework of the PixFEL project, a readout chip for pixel sensors has been designed and fabricated in a 65 nm CMOS technology. The PixFEL detector is intended for application to coherent X-ray diffraction imaging (CXDI) at the next generation free electron lasers (FELs). This paper will present a characterization of PFM3’s signal chain first stage. Characterization data has been collected from the charge sensitive amplifier (CSA) stage, implementing a dynamic compression of the input signal. Measurements demonstrating the validity of the dynamic compression feature for various gain settings (1 keV, 2keV and 3keV) and temperatures −40 °C to 70 °C are shown.

This work discusses four different algorithms for the minimization of threshold dispersion in multichannel readout circuits for pixel detectors. These algorithms, which are based on different methods (e.g. charge scans, threshold scans, etc) and differs in terms of performance and computation time, have been tested on the asynchronous front-end integrated in the CHIPIX65_FE0, a readout ASIC prototype designed in a 65 nm CMOS technology.

Single-photon avalanche diode (SPAD) arrays fabricated in a 180-nm CMOS technology with a high-voltage option have been exposed to calibrated neutron and X-ray sources to evaluate their radiation tolerance. The technology is being investigated in view of the design of low material budget detectors for charged particle tracking based on the coincidence of the signals coming from two or more overlapping layers of SPAD sensors. Each element in the array is a monolithic detector including the processing electronics together with the diode in the same substrate. Different sensor dimensions and structures have been implemented in the test chip to thoroughly explore the technology features. This paper will present and discuss the results from the characterization, in terms of dark count rate, of SPAD arrays irradiated with X-ray doses reaching 1 Mrad(SiO2) and with neutron fluences up to $10^{11}~1$ -MeV neutron equivalent cm $^{-2}$ .

International audience; An array of Single Photon Avalanche Diodes (SPAD), fabricated in a 180 nm CMOS technology featuring a high voltage (HV) option, has been investigated in terms of radiation tolerance, in view of the design of low material budget dual-tier detectors for charged particle tracking based on the coincidence of signals coming from pairs of vertically aligned pixels. Each pixel in the array includes both the processing electronics and the sensing element in a monolithic structure. The test vehicles were irradiated with 10 keV X-rays up to a dose of 1 Mrad (SiO 2 ) and with neutrons up to a fluence of 10 11 n eq cm −2 . A selection of the characterization results are presented together with the main features of a new large scale SPAD array to be fabricated in a 150 nm CMOS technology and ready for vertical interconnection in a dual layer structure.

International audience; The RD53A large scale pixel demonstrator chip has been developed in 65 nm CMOS technology by the RD53 collaboration, in order to face the unprecedented design requirements of the pixel 2 phase upgrades of the CMS and ATLAS experiments at CERN. This prototype chip is designed to demonstrate that a set of challenging specifications can be met, such as: high granularity (small pixels of 50×50 or 25× 100 µm2) and large pixel chip size (~2x2 cm2), high hit rate (3 GHz/cm2), high readout speed, very high radiation levels (500 Mrad - 1 Grad) and operation with serial powering. Furthermore, coping with the long latency of the trigger signal (~12.5 µs), used to select only events of interest in order to achieve sustainable output data rates, requires increased buffering resources in the limited pixel area. The RD53A chip has been fabricated in an engineer run. It integrates a matrix of 400×192 pixels and features various design variations in the analog and digital pixel matrix for testing purposes. This paper presents an overview of the chip architecture and of the methodologies used for efficient design of large complex mixed signal chips for harsh radiation environments. Experimental results obtained from the characterization of the RD53A chip are reported to demonstrate that design objectives have been achieved. Moreover, design improvements and new features being developed in the RD53B framework for final ATLAS and CMS production chips are discussed

International audience; This work is concerned with the experimental characterization of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier with detector leakage compensation circuit, and a compact, single ended comparator able to correctly process hits belonging to two consecutive bunch crossing periods. A 2-bit Flash ADC is exploited for digital conversion immediately after the preamplifier. A description of the circuits integrated in the front-end processor and the initial characterization results are provided.

This work is concerned with the design and characterization of an SLVS transmitter/receiver pair, to be used for I/O links in High Energy Physics applications. Core transistors with a power supply of 1.2 V have been considered in the design in order to mitigate the TID effects, due to the harsh radiation environment foreseen. The circuits have been implemented in a 65 nm CMOS technology. The prototype chip was designed and fabricated in the framework of the RD53 project and was completely characterized in the first quarter of 2016. The chip has been also irradiated with X-rays in order to evaluate the effect of the ionizing radiation on the signal integrity

This work is concerned with the design of a low-noise Charge Sensitive Amplifier featuring a dynamic signal compression based on the non-linear features of an inversion-mode MOS capacitor. These features make the device suitable for applications where a non-linear characteristic of the front-end is required, such as in imaging instrumentation for free electron laser experiments. The aim of the paper is to discuss a methodology for the proper design of the feedback network enabling the dynamic signal compression. Starting from this compression solution, the design of a low-noise Charge Sensitive Amplifier is also discussed. The study has been carried out by referring to a 65 nm CMOS technology.

The Source Follower (SF) as the first amplification stage of the front-end electronics has proven to be an effective tool for low-noise read-out of silicon radiation sensors. Since the noise properties of a well-designed amplification circuit are mainly determined by its very first stage, constraints on the subsequent electronics are relaxed. Moreover, since the SF is characterized by a low output resistance, once it is completely integrated into the detector substrate, the connections to the out-of-chip part of the circuit are also relaxed. The effectiveness of this solution and the overall performance of the system depend on the sensor properties. In this paper, by presenting analytical calculations and measurements, we identify the sensor types that could profit from the advantages provided by the integrated SF, and the devices where the SF shows some pitfalls. Although the results presented in this paper have been obtained with an integrated JFET technology, the conclusions are valid for whatever technology the SF is made.

This work discusses the main features of a CMOS Deep N-well (DNW) monolithic active pixel sensor (MAPS) fabricated in a vertically integrated technology, where two 130 nm CMOS homogeneous tiers are processed to obtain a 3D integrated circuit (3D-IC). The 3D CMOS MAPS, which was designed in view of vertexing applications to experiments at high luminosity colliders, features a 20 μm pitch for a point resolution of about 5 μm and data sparsification capabilities for high data rate systems. Results from the characterization of different test structures, including single pixels, 3×3 and 8×8 matrices, are presented. In particular, measurements have been performed with an infrared laser source to evaluate the charge collection properties of the proposed vertically integrated sensors.

Clock distribution circuits account for a significant fraction of the power dissipation of the Macro Pixel ASIC (MPA), designed for the pixel layer readout of the so-called Pixel-Strip module in the innermost part of the CMS tracker at the High Luminosity LHC. A test chip including low power clock distribution circuits of the MPA has been designed in a 65 nm CMOS technology and thoroughly tested. This work summarizes the experimental results relevant to the prototype chip, focusing particularly on the power and speed performance and compares such results with those coming from circuit simulations.

In the framework of the PixFEL project, a processing channel for pixel sensor readout has been designed and fabricated in a 65 nm CMOS technology. The detector under development is aimed at applications to coherent X-ray diffraction imaging (CXDI) at the next generation free electron lasers (FELs). Especially in the detector region around the hole for the unscattered photon beam, pixels will be subjected to huge doses of ionizing radiation, in the order of tens of Grad(SiO 2 , during their lifetime. The total ionizing dose (TID) for the frontend electronics, while significantly reduced by the shielding effect of the detector, is still expected to exceed one Grad(SiO 2 . This paper investigates the performance degradation in the PixFEL readout circuit, in particular in the charge sensitive amplifier, after exposure to X-ray doses up to 100 Mrad(SiO 2 .

International audience; RD53A is a large scale 65 nm CMOS pixel demonstrator chip that has been developed by the RD53 collaboration for very high rate (3 GHz/cm$^2$) and very high radiation levels (500 Mrad, possibly 1 Grad) for ATLAS and CMS phase 2 upgrades. It features serial powering operation and design variations in the analog and digital pixel matrix for different testing purposes. The design and verification of RD53A are described together with an outline of the plans to develop final pixel chips for the two experiments.

A charge preamplifier has been developed in a 65-nm CMOS technology for processing the signals from the inner pixel layers of the CMS detector, in view of the experiment upgrade for the High-Luminosity (HL) Large Hadron Collider (LHC). The circuit is part of a readout channel implementing a time-over-threshold method for the analog-to-digital conversion of the input charge signal. Samples of the circuit have been exposed to high doses of ionizing radiation, up to 500 Mrad(SiO2), from a low-energy proton source and from an X-ray tube. The test results show that the performance degradation, in terms of charge sensitivity, signal shape, and noise, is compatible with operation in the harsh environment of the HL-LHC. Measurement data from the characterization of preamplifiers using different kinds of capacitors in the feedback network help to gain some insight into the damage mechanisms in pMOS transistors irradiated with large ionizing doses. The dependence of performance degradation on the kind of radiation source used in the tests is also discussed.

This work discusses the main results relevant to the characterization of an analogfront-end processor designed in view of experiments with unprecedented particle rates and radiation levels at the High-Luminosity LHC (HL-LHC). The frontend channel presented in this paperis part of the CHIPIX65FE0 prototype, a readout ASIC designed in a 65 nm CMOS technology in the frame of the CERN RD53 collaboration. The prototype integrates $\mathrm{a}64 \times64$ pixelmatrix, divided into two $32 \times64$ sub-matrices with $50 \mu \mathrm{m}$ pitch, embodying two analog front-end architectures based on synchronous and asynchronous hit discriminators. The analog chain takes an overall area close to $1000 \mu \mathrm{m^{2}}$, with a per-channel power dissipation around $5 \mu \mathrm{W}$. The paper is focused on the characterization of the array with asynchronous channels, before and after exposure to ionizing doses up to 630 Mrad(SiO 2 of X-rays. The mean value of the equivalent noise charge (ENC), not significantlyaffected by radiation, is close to 90 electrons with no sensor connected to the front-end. Thethreshold dispersion before irradiation is 55 electrons, for a tuned threshold of 600 electrons, with a moderate increase after irradiation. The assessed performance guarantees sub-1000 electrons stable threshold operations, which is a mandatory feature for highly efficient readoutchips for the HL-LHC.

This paper describes a readout ASIC prototype designed by the CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC . A 64×64 matrix of 50×50μm2 pixels is realised. A digital architecture has been developed, with particle efficiency above 99.5% at 3 GHz/cm2 pixel rate, trigger frequency of 1 MHz and 12.5μsec latency. Two analog front end designs, one synchronous and one asynchronous, are implemented. Charge is measured with 5-bit precision, analog dead-time below 1%. The chip integrates for the first time many of the components developed by the collaboration in the past, including the Digital-to-Analog converters, Bandgap reference, Serializer, sLVS drivers, and analog Front Ends. Irradiation tests on these components proved their reliability up to 600 Mrad.

International audience; In this paper, we present a two-layered silicon sensor working in Geiger-mode avalanche regime and designed for charged particle detection. Each position-sensitive element is comprised of two vertically aligned pixels, exploiting the coincidence between two simultaneous avalanche events to discriminate between particle triggers and dark counts. This approach potentially offers several advantages. First, a low material budget can be achieved thanks to the thinning of the detector down to a few tens of microns (e.g. 50 μm) as the avalanche starts in a shallow region just a few microns deep. Operation in a regime of quenched avalanche allows for an excellent timing resolution and provides an internal gain that makes a front-end amplification stage unnecessary, thus dramatically reducing the power consumption. Fine detector segmentation is possible as the (horizontal) inter-pixel cross-talk in the detection plane can be reduced to a comfortable level while the vertical cross-talk is totally eliminated using a metal light-shield layer. The detector is also insensitive to background light. A number of applications could benefit from a detector with these characteristics, including particle tracking and vertex reconstruction in particle physics experiments at accelerators and in space, as well as ionizing radiation imaging in nuclear medicine and life-sciences.

International audience; In this paper, we present the implementation and preliminary evaluation of a new type of silicon sensor for charged particle detection operated in Geiger-mode. The proposed device, formed by two vertically-aligned pixel arrays, exploits the coincidence between two simultaneous avalanche events to discriminate between particle-triggered detections and dark counts. A proof-of-concept two-layer sensor with per-pixel coincidence circuits was designed and fabricated in a 150 nm CMOS process and vertically integrated through bump bonding. The sensor includes a 48×16 pixel array with 50μm×75μm pixels. This work describes the sensor architecture and reports a selection of results from the characterization of the avalanche detectors in the two layers. Detectors with an active area of 43×45μm2 have a median dark count rate of 3 kHz at 3.3 V excess bias and a breakdown voltage non-uniformity lower than 20 mV.

CHIPIX65-FE0 is a readout ASIC in CMOS 65nm designed by the CHIPIX65 project for a pixel detector at the HL-LHC, consisting of a matrix of 64x64 pixels of dimension 50x50 μm2. It is fully functional, can work at low thresholds down to 250e− and satisfies all the specifications. Results confirm low-noise, fast performance of both the synchronous and asynchronous front-end in a complex digital chip. CHIPIX65-FE0 has been irradiated up to 600 Mrad and is only marginally affected on analog performance. Further irradiation to 1 Grad will be performed. Bump bonding to silicon sensors is now on going and detailed measurements will be presented. The HL-LHC accelerator will constitute a new frontier for particle physics after year 2024. One major experimental challenge resides in the inner tracking detectors, measuring particle position: here the dimension of the sensitive area (pixel) has to be scaled down with respect to LHC detectors. This paper describes the results obtained by CHIPIX65-FE0, a readout ASIC in CMOS 65nm designed by the CHIPIX65 project as small-scale demonstrator for a pixel detector at the HL-LHC. It consists of a matrix of 64x64 pixels of dimension 50x50 um2 pixels and contains several pieces that are included in RD53A, a large scale ASIC designed by the RD53 Collaboration: two out of three front-ends (a synchronous and an asynchronous architecture); several building blocks; a (4x4) pixel region digital architecture with central local buffer storage, complying with a 3 GHz/cm2 hit rate and a 1 MHz trigger rate maintaining a very high efficiency (above 99%). The chip is 100% functional, either running in triggered or trigger-less mode. All building-blocks (DAC, ADC, Band Gap, SER, sLVS-TX/RX) and very front ends are working as expected. Analog performance shows a remarkably low ENC of 90e-, a fast-rise time below 25ns and low-power consumption (about 4μA/pixel) in both synchronous and asynchronous front-ends; a very linear behavior of CSA and discriminator. No significant cross talk from digital electronics has been measured, achieving a low threshold of 250e-. Signal digitization is obtained with a 5b-Time over Threshold technique and is shown to be fairly linear, working well either at 80 MHz or with higher frequencies of 300 MHz obtained with a tunable local oscillator. Irradiation results up to 600 Mrad at low temperature (-20°C) show that the chip is still fully functional and analog performance is only marginally degraded. Further irradiation will be performed up to 1 Grad either at low or room temperature, to further understand the level of radiation hardness of CHIPIX65-FE0. We are now in the process of bump bonding CHIPIX65-FE0 to 3D and possibly planar silicon sensors during spring. Detailed results will be presented in the conference paper.

This work presents the first characterization results obtained on a pilot fabrication run of planar sensors, tailored for X-ray imaging applications at FELs, developed in the framework of INFN project PixFEL. Active and slim-edge p-on-n sensors are fabricated on n-type high-resistivity silicon with 450 μm thickness, bonded to a support wafer. Both diodes and pixelated sensors with a pitch of 110 μm are included in the design. Edge structures with different number of guard rings are designed to comply with the large bias voltage required by the application after accumulating an ionizing radiation dose as large as 1GGy. Preliminary results from the electrical characterization of the produced sensors, providing a first assessment of the proposed approach, are discussed. A functional characterization of the sensors with a pulsed infrared laser is also presented, demonstrating the validity of slim-edge configurations.

Monolithic active pixelsensors fabricated in abulk CMOS technology with no epitaxial layer and standard resistivity(10 Ω cm) substrate, featuring a deep N-well as the collecting electrode (DNW MAPS), have been exposed to γ-rays, up to a final dose of 10 Mrad (SiO2), and to neutrons from a nuclear reactor, up to a total 1 MeV neutron equivalent fluence of about 3.7 x 10^13 cm^−2. The irradiation campaign was aimed at studying the effects of radiation on the most significant parameters of the front-end electronics and on the charge collection properties of the sensors. Device characterization has been carried out before and after irradiations. The DNW MAPS irradiated with 60Co γ-rays were also subjected to high temperature annealing (100 C for 168 h). Measurements have been performed through a number of different techniques, including electrical characterization of the front-end electronics and of DNW diodes, laser stimulation of the sensors and tests with 55Fe and 90Sr radioactive sources. This paper reviews the measurement results, their relation with the damage mechanisms underlying performance degradation and provides a new comparison between DNW devices and MAPS fabricated in a CMOS process with high resistivity (1 kΩ cm) epitaxial layer.

This work presents the characterization of Deep N-well (DNW) active pixel sensors fabricated in a vertically integrated technology. The DNW approach takes advantage of the triple well structure to lay out a sensor with relatively large charge collecting area (as compared to standard three transistor MAPS), while the readout is performed by a classical signal processing chain for capacitive detectors. This new 3D design relies upon stacking two homogeneous tiers fabricated in a 130 nm CMOS process where the top tier is thinned down to about 12 μ m to expose through silicon vias (TSV), therefore making connection to the buried circuits possible. This technology has been used to design a fine pitch 3D CMOS sensor with sparsification capabilities, in view of vertexing applications to the International Linear Collider (ILC) experiments. Results from the characterization of different kind of test structures, including single pixels, 3×3 and 8×8 matrices, are presented.

Total ionizing dose effects are studied in 130-nm transistors and pixel sensors in a vertically integrated two-layer CMOS technology, evaluating the possible impact of 3D integration on radiation tolerance and damage mechanisms. Measurements of static characteristics and noise voltage spectra before and after exposure to high total ionizing doses demonstrate that the analog performance of transistors as well as their radiation hardness are not degraded by mechanical and thermal stresses occurring during the fabrication of the 3D chips. The paper also presents irradiation results on 3D CMOS pixel sensors with a sparsified readout architecture. After exposure to ionizing radiation, these devices behave in a very similar way as analogous counterparts in a standard 2D 130-nm process, confirming that performance advantages associated with 3D integration are not impaired by an enhanced radiation sensitivity.

The prototype of a three-dimensional (3D) monolithic active pixel sensor (MAPS) has been characterized. The device, featuring a 20μm pitch, was designed based on the same approach that was adopted in developing the so-called deep N-well (DNW) MAPS in planar CMOS process. The new 3D design relies upon stacking two homogeneous tiers fabricated in a 130 nm CMOS technology. Different kinds of test structures, including single pixels, 3×3 arrays and 8×8 and 16×16 matrices were tested. Functionality of the collecting deep N-well electrode, the analog front-end and the digital readout electronics has been demonstrated. Inter-tier communication was found to work properly in the case of redundant interconnection and could be exploited for the test of the analog pixel section. On the other hand, inter-tier interconnections based on individual bond pads were proven ineffective likely due to wafer misalignment.