333 results on '"Linten, D."'
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2. The impact of self-heating and its implications on hot-carrier degradation – A modeling study
3. Low frequency noise analysis on Si/SiGe superlattice I/O n-channel FinFETs
4. Comphy — A compact-physics framework for unified modeling of BTI
5. A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability
6. Quantitative retention model for filamentary oxide-based resistive RAM
7. Impact of the Device Geometric Parameters on Hot-Carrier Degradation in FinFETs
8. Analysis of the Features of Hot-Carrier Degradation in FinFETs
9. The defect-centric perspective of device and circuit reliability—From gate oxide defects to circuits
10. Reliability challenges in Forksheet Devices: (Invited Paper)
11. Causes and consequences of the stochastic aspect of filamentary RRAM
12. Total-Ionizing-Dose Effects in IGZO Thin-Film Transistors with SiO2 Oxygen-Penetration Layers
13. Positive bias temperature instability of HfO2-based gate stacks at reduced thermal budget for future CMOS technologies.
14. Total-Ionizing-Dose Effects in IGZO Thin-Film Transistors With SiO₂ Oxygen-Penetration Layers
15. Bias Temperature Instability (BTI) in high-mobility channel devices with high-k dielectric stacks: SiGe, Ge, and InGaAs
16. Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO
17. Evaluating Forksheet FET Reliability Concerns by Experimental Comparison with Co-integrated Nanosheets
18. Low-temperature atomic and molecular hydrogen anneals for enhanced chemical $\mathbf{SiO}_{2}$ IL quality in low thermal budget RMG stacks
19. A plug-and-play wideband RF circuit ESD protection methodology: T-diodes
20. Novel low thermal budget gate stack solutions for BTI reliability in future Logic Device technologies : Invited paper
21. Impact of Charge Trapping and Depolarization on Data Retention Using Simultaneous P–V and I–V in HfO₂-Based Ferroelectric FET
22. Investigation of Imprint in FE-HfO2 and Its Recovery
23. An Ultra Low Voltage, Low Power, Fully Integrated VCO for GPS in 90 nm RF-CMOS
24. On the impact of buffer and GaN-channel thickness on current dispersion for GaN-on-Si RF/mmWave devices
25. A BSIM-Based Predictive Hot-Carrier Aging Compact Model
26. Reliability and Variability-Aware DTCO Flow: Demonstration of Projections to N3 FinFET and Nanosheet Technologies
27. Implementation of plug-and-play ESD protection in 5.5 GHz 90 nm RF CMOS LNAs—Concepts, constraints and solutions
28. Low-frequency noise assessment of ferro-electric field-effect transistors with Si-doped HfO2 gate dielectric
29. Atomic Hydrogen Exposure to Enable High-Quality Low-Temperature SiO2 with Excellent pMOS NBTI Reliability Compatible with 3D Sequential Tier Stacking
30. Defect profiling in FEFET Si:HfO2 layers
31. Investigation of Imprint in FE-HfO₂ and Its Recovery
32. Trap identification on n-channel GAA NW FETs
33. Physical Modeling the Impact of Self-Heating on Hot-Carrier Degradation in pNWFETs
34. Overview of Bias Temperature Instability in Scaled DRAM Logic for Memory Transistors
35. Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability
36. Quantum Mechanical Charge Trap Modeling to Explain BTI at Cryogenic Temperatures
37. Fast & Accurate Methodology for Aging Incorporation in Circuits using Adaptive Waveform Splitting (AWS)
38. Exploring the DC reliability metrics for scaled GaN-on-Si devices targeted for RF/5G applications
39. Reliability and Variability of Advanced CMOS Devices at Cryogenic Temperatures
40. On the impact of mechanical stress on gate oxide trapping
41. Gate Bias and Length Dependences of Total-Ionizing-Dose Effects in InGaAs FinFETs on Bulk Si
42. A Sensitivity Map-Based Approach to Profile Defects in MIM Capacitors From I-V, C-V, and G-V Measurements
43. Understanding and Physical Modeling Superior Hot-Carrier Reliability of Ge pNWFETs
44. Impact of Charge trapping on Imprint and its Recovery in HfO2 based FeFET
45. Reliability Engineering Enabling Continued Logic for Memory Device Scaling
46. Application of Single Pulse Dynamics to Model Program and Erase Cycling-Induced Defects in the Tunnel Oxide of Charge-Trapping Devices
47. Impact of Fin Height on Bias Temperature Instability of Memory Periphery FinFETs
48. Simulation Study: the Effect of Random Dopants and Random Traps on Hot-Carrier Degradation in nFinFETs
49. Physics-based Modeling of Hot-Carrier Degradation in Ge NWFETs
50. On the Impact of the Gate Work-Function Metal on the Charge Trapping Component of NBTI and PBTI
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