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This paper presents a double-sided liquid cooling scheme for power MOSFETs using Embedded Power packaging technology. A liquid module test bed has been built to create various convection conditions and is used with 600-V high-current MOSFET-based Embedded Power samples to test the effectiveness and feasibility of the proposed scheme. Compared with single-sided liquid cooling, an improvement of 45% to 60% in thermal resistance is experimentally shown, for Embedded Power with double-sided liquid cooling for a device loss between 5 and 300 W and 0.25 to 4.5 GPM water flow rate. The trend and concept is also validated with physics-based lumped parameter thermal models. Index Terms--Double-sided cooling, forced liquid convection, power density, semiconductor packaging.

Technology for a 3-D high temperature integrated power electronics module for applications involving high density, and high temperature (e.g., those over 200 [degrees]C) is described. The high temperature embedded chip module (ECM) technology is proposed to realize a lower stress distribution in a mechanically balanced structure with double-sided metallization layers and material coefficient of thermal expansion match in the structure. This technology for packaging the active component is also proposed for universal use with a flip-over structure and pressure connections. The fabrication process of this high temperature ECM is presented. The forward and reverse characteristics of the high temperature ECM have been measured up to 279 [degrees]C. Thermally induced mechanical stress is reduced to an acceptable level by applying a symmetrical structure with buffering layers. Index Terms--Coefficient of thermal expansion (CTE), embedded chip module (ECM).

In integrated power modules, mechanical properties of interfaces between deposited copper traces and substrates are important for reliable operation. This paper investigates the values of thermomechanical stresses by IDEAS simulation and describes an experimental method to calculate intrinsic residual stresses using the Stoney equation based on the bending curvature of the sample. Index Terms--Intrinsic residual stress, planar metallization, thermomechanical stress.

A Si CoolMOS field effect transistor and SiC diode assembly with gate driver in boost configuration (ratings at 600 V/12 A), for power factor correction application, has been fabricated in a version of an integrated power electronic module. It uses the so-called embedded power technology, to form a three-dimensional multiple chip/component interconnection with the embedded chips in a co-planar ceramic substrate with thin-film metallization bond/interconnection added on top. In this paper, the switching parameters of this module and their effects on the performance of a converter have been analyzed and experimentally characterized. The procedures adopted for the defined fabrication process of planar metallization interconnects are presented. In addition to the improvement of structural electrical properties, compared to a conventional discrete version, the characteristics of the planar process integration have also been demonstrated. Index Terms--Power electronics module integration, power semiconductor switching, structural electromagnetic parameters.

Assemblies of power semiconductor switches and their associated drive circuits are at present available in modules. Upward into the multi-kilowatt range, mixed mode module construction is used. This incorporates monolithic, hybrid, surface mount, and wirebond technology. However, a close examination of the applications in motor drives and power supplies indicates that there has been no dramatic volume reduction of the subsystem. The power semiconductor modules have shrunk the power switching part of the converter, but the bulk of the subsystem volume still comprises the associated control, sensing, electromagnetic power passives (inductors, transformers, capacitors) and interconnects. This paper addresses the improvement of power processing technology through advanced integration of power electronics. The goal of a subsystem in a module necessitates this advanced integration, incorporating active switching stages, electromagnetic interference (EMI) filters, and electromagnetic power passives into modules by integration technology. The central philosophy of the technology development research in the National Science Foundation Engineering Research Center for Power Electronic Systems is to advance the state of the art by providing the concept of integrated power electronics modules (IPEMs) for all these functions. The technology underpinning such an IPEM approach is discussed. Index Terms--Electromagnetic interference (EMI) filters, integrated power electronics modules (IPEMs).

A metal-oxide-semiconductor field-effect transistor (MOSFET) (rating at 500 V/24 A) half-bridge power switching subassembly with gate drivers has been fabricated, employing a planar integration technology, in which an integrated power chips stage is built by embedding chips in a coplanar ceramic substrate with a metallization thin-film interconnection built up onto it. This deposited metallization not only bonds the power chips, but also provides the second-level interconnect wiring. The associated components are mounted on top of the integrated power stage. This packaging scheme results in a three-dimensional (3-D) multiple chips/components assembly with the capability of functional integration. In this paper, the electrical and thermal parameters of this packaged module have been experimentally and theoretically characterized. The procedures adopted for the defined fabrication processes are presented. In addition to the characteristics of the planar integration process, the improved electrical and thermal performance has been demonstrated. Index Terms--Multichip 3-D integration, planar process technology, power electronics integrated packaging, power electronics modules.