Back to Search
Start Over
Reducing Parasitic Electrical Parameters with a Planar Interconnection Packaging Structure.
- Source :
- 2012 7th International Conference on Integrated Power Electronics Systems (CIPS); 1/ 1/2012, p1-6, 6p
- Publication Year :
- 2012
-
Abstract
- A novel packaging structure for medium power modules featuring power semiconductor switches sandwiched between two symmetric substrates that fulfill electrical conduction and insulation functions is presented. The power switches in a popular phase leg electrical topology are orientated in a face up/face down configuration. Large bonding areas between dies and substrates combined with a compact busbar interface allow this packaging technology to offer dramatic improvements in electrical conversion efficiency and electromagnetic interference containment. [ABSTRACT FROM PUBLISHER]
Details
- Language :
- English
- ISBNs :
- 9783800734146
- Database :
- Complementary Index
- Journal :
- 2012 7th International Conference on Integrated Power Electronics Systems (CIPS)
- Publication Type :
- Conference
- Accession number :
- 86516059