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This article presents a fully integrated Cryo-CMOS system on chip (SoC) for quantum computing. The proposed SoC integrates a radio frequency (RF) pulse modulator for qubit state manipulation, a multi-tone signal generator and a coherent receiver for qubit state readout, and 22 DACs for high-speed voltage pulsing of qubit gates. By adopting frequency division multiplexing and direct digital synthesis (DDS), the RF pulse modulator can control up to 16 qubits over a single RF line, and the readout receiver can detect the state of up to six qubits simultaneously. The proposed SoC also integrates a microcontroller for low latency on-chip signal processing and increased flexibility in implementing quantum instruction sets. A detailed analysis of qubit-state readout fidelity and the impact of finite DAC resolution on two-qubit gate fidelity is also included in this article, together with an electrical specification summary. The SoC is implemented in Intel’s 22 nm FFL fin field-effect transistor (FinFET) process, and it is characterized both at room and 4 K temperatures. The performance of each specific block is measured, with the readout characterized in a loop-back configuration. Generation of the control signals required for a full Rabi oscillation experiment is also demonstrated. This article also describes the cryogenic thermalization techniques used to integrate the SoC in the dilution refrigerator and shows temperature measurements during operation.

Quantum computing promises exponential speed-up in solving certain complex problems that would be intractable by classical computers. However, thousands or millions of qubits might be required to solve useful problems. High-precision and low-noise electrical signals are required to manipulate and read the state of a qubit and to control qubit-to-qubit interactions. Current systems use room temperature electronics with many coax cables routed to the qubit chip inside a dilution refrigerator. This approach does not scale to large number of qubits, due to form factor, cost, power consumption and thermal load to the fridge. To address this challenge, a cryogenic qubit controller has been proposed [1]. The first integrated implementation of a cryogenic pulse modulator has been presented in [2], demonstrating the capability of manipulating (drive) the state of superconducting qubits. The work in [3] extends the capability of the controller with 3 main features: frequency-multiplexing to reduce the number of RF cables per qubit, an arbitrary I/Q pulse generation for improved control fidelity and a digitally-intensive architecture with integrated instruction set to enable integration in existing quantum control stacks. This work further advances the prior art by integrating the capability of reading the qubit state and generating the voltage pulses required for drive, readout, 2-qubit operations and qubit characterization. The SoC can drive up to 16 spin qubits by frequency multiplexing over a single RF line, read the state of up to 6 qubits simultaneously and control up to 22 gate potentials. The SoC also integrates a $\mu$-controller for increased flexibility in implementing the control instruction set. The proposed cryogenic controller can replace all the high-speed control electronics used in conventional solutions today, paving the way towards scalable quantum computers.

Perhaps the greatest challenge facing quantum computing hardware development is the lack of a high throughput electrical characterization infrastructure at the cryogenic temperatures required for qubit measurements. In this article, we discuss our efforts to develop such a line to guide 300mm spin qubit process development. This includes (i) working with our supply chain to create the required cryogenic high volume testing ecosystem, (ii) driving full wafer cryogenic testing for both transistor and quantum dot statistics, and (iii) utilizing this line to develop a quantum dot process resulting in key electrical data comparable to that from leading devices in literature, but with unprecedented yield and reproducibility.

We investigate the structural and quantum transport properties of isotopically enriched Si28/SiO228 stacks deposited on 300-mm Si wafers in an industrial CMOS fab. Highly uniform films are obtained with an isotopic purity greater than 99.92%. Hall-bar transistors with an oxide stack comprising 10 nm of Si28O2 and 17 nm of Al2O3 (equivalent oxide thickness of 17 nm) are fabricated in an academic cleanroom. A critical density for conduction of 1.75×1011cm-2 and a peak mobility of 9800cm2/Vs are measured at a temperature of 1.7 K. The Si28/SiO228 interface is characterized by a roughness of Δ=0.4nm and a correlation length of Λ=3.4nm. An upper bound for valley splitting energy of 480μeV is estimated at an effective electric field of 9.5 MV/m. These results support the use of wafer-scale Si28/SiO228 as a promising material platform to manufacture industrial spin qubits.

Quantum computing's value proposition of an exponential speedup in computing power for certain applications has propelled a vast array of research across the globe. While several different physical implementations of device level qubits are being investigated, semiconductor spin qubits have many similarities to scaled transistors. In this article, we discuss the device/integration of full 300mm based spin qubit devices. This includes the development of (i) a 28 Si epitaxial module ecosystem for growing isotopically pure substrates with among the best Hall mobility at these oxide thicknesses, (ii) a custom 300mm qubit testchip and integration/device line, and (iii) a novel dual nested gate integration process for creating quantum dots.