Search

The strain impact on integrated circuit performance is investigated by applying a novel indentation technique. The approach aims to investigate stress caused by CPI, particularly highly localized stress/strain with respect to the actual device geometry. Non-destructive elastic indentation is used to induce homogenous stress fields in the vicinity of the test structure by applying a contact with a spherical tip. Strain-sensitive ring oscillator structures manufactured in the 22 nm FDSOI CMOS technology node are designed to monitor the device and simultaneously the NMOS and PMOS strain behavior separately. Complementary FE-simulations provide a deeper insight into the obtained experimental results by transferring them from contact force into the stress/strain space and validating the indentation approach. Relevant layout and indentation dependent parameters are investigated and evaluated. The simulation of the strain induced mobility shift and the comparison with the established correlation verifies the accuracy of the approach. The results provide an insight into package-related stress and resulting transistor degradation, aiming at establishing a versatile tool to estimate the effect of specific real-usage conditions.

The field of consumer and automotive electronics is becoming increasingly important for applications of mmWave technology. Innovative approaches and materials for electronics packaging are currently being developed. The focus on improving the performance and the reliability induces an increased demand for in-depth analysis and testing. In this study, the thermo-mechanical behaviour of mmWave modules mounted onto a standard or a hybrid substrate is investigated. A board level reliability study is performed according to the automotive standard AEC-Q100 grade 1 specification. Findings after temperature cycling test at −55°C to + 150°C will be presented. Commercially available FR4 substrate materials with high- and suitable low transmission loss characteristics are selected to meet both automotive and high frequency requirements. The mmWave module is made of one low loss material. The impact of two substrate configurations on the board level reliability of the mmWave module is investigated. Considering the different material properties and the large package dimension, temperature changes will cause severe stress to the board level solder interconnects (alloy SAC305, diameter). The performance of the mmWave test vehicle in terms of the solder joint damage behaviour under temperature cycling testing will be analysed in this study. Both specimen configurations successfully passed electrical tests after up to 1,000 cycles temperature cycling. Cross sections and electrical analysis show a better performance of the hybrid configuration at high cycle counts.

Packages based on the Antenna-in-Package approach and designed for mmWave applications are large in area size, e.g. due to size of patch antennas and their pitch in an array. High frequency-able package materials that have comparably high Young’s modulus and low coefficient of thermal expansion are needed to match the electrical performance. Both geometry and materials influence the warpage behavior of the package during fabrication as well as under use case conditions. In this work, a comparative study on warpage throughout the fabrication process is carried out and focuses on two different FR4-materials being used. In addition, warpage effects on occurring solder joint shapes and package robustness during temperature cycling test done at -55 °C to +150 °C for up to 750 cycles are assessed at board level. To reveal package and solder joint robustness cross sectioning was done.

The stress related shifts of transistors are measured by precise stress application with a newly designed in-situ four-point bending (4PB) system. A test board including a flip chip packaged test vehicle is loaded with uniaxial stress. The test vehicle contains dedicated ring oscillator circuits fabricated in the 22 nm FDSOI technology node, used to evaluate the effects of thermo-mechanical stress on the characteristics of CMOS devices. Finite element simulation provides insight into the originated stress values in the board, package, and active devices during mechanical loading. Considering the bending caused stress in the devices and the specific layout of the circuits, the directional frequency shifts of the circuits under stress are derived. These shifts are compared with a previous indentation study, which has been developed to induce very localized loads. The comparison aims for verification of the indentation approach to study directional stress related effects as well as very localized effects in chip stacks.

The stress-related change in the characteristics of transistors manufactured in the 22 nm fully depleted silicon on insulator (FDSOI) CMOS technology node is studied with advanced experimental indentation setups. Precisely, NAND and NOR ring oscillator circuits are used to monitor the strain-caused mobility deviations in the silicon transistor channels. Piezoresistive coefficients for strained silicon are calculated from the experimental indentations data using spherical and cylindrical tip geometries. In contrast to spherical tips, the cylindrical indentation tips enable to induce the stress more selectively into a desired direction. To set up the experimental details appropriately, finite element (FE) simulations have been used. Additionally, FE method (FEM) studies are conducted to compute the quantitative strain values in the silicon transistor channels as a function of contact load as well as chip and tip geometries. Using the signal deviations of the RO circuits subjected to strain from spherical and cylindrical indentation, a set of equations using the linearized piezoresistive model are created to determine the directional piezoresistive coefficients.

Suitable stretchable electronics is the key to promote future human-machine collaboration to facilitate processes in daily life. Sensors and actuators on humans will enable a close and yet unhesitating interaction with robots by translating data between biological and technical systems. This paper describes our first approach for chip integration and stretchable interconnect manufacturing in order to achieve reliable stretchable interconnects. Therefore inkjet printed silver horseshoe-interconnects with a radius of 500µm on spin coated polyurethane substrate are tested on a self-developed stretch test setup. More than 400 stretch and release cycles on 10% and 20% stretching were achieved. Furthermore, a polymer chip-embedding process by polymer casting is shown to apply fan-out redistribution layer directly on thin chip carrier. Those carriers can be integrated in stretchable foils in order to achieve miniaturized and low-profile assemblies for human-machine interfaces.

Autonomous driving and car to car or car to infrastructure communication applications are pursuing and demand for a detailed understanding of the reliability of electronics. This work focuses on reliability analysis of flip-chip chip scale packages (FCCSP) for such as automotive electronics applications. Reliability investigation is accomplished by means of temperature cycling on board level (TCoB) since it is strongly recommended to apply such tests during the package development phase. Tests have been done on FCCSP components. The board level interconnects are solder joints with a BGA pitch of 0.4 mm. The packages have been assembled to custom test boards using SnAgCu solder alloy. Temperature cycling was done at -40/125 °C according to the AEC-Q100 standard. Test board development was done to enable harsh test conditions and to cover advanced use requirements, e.g. by selecting a high-T g material. The entire test setup enables in-situ monitoring of resistance and leakage currents. The tested packages have been manufactured using a flip-chip CSP assembly technology and Cu-pillar first level interconnects. As electronics qualification procedures require passing at least 500 TC cycles but the AEC even ask to pass 1,000 cycles, the aim of this study was to investigate the health of the first and second level interconnects of the FCCSP package after an intermediate cycle count of 750. The stress which the second level interconnects are exposed to was accelerated. Therefore, the board design considered SMD defined pads with a rather small pad diameter. In addition, consecutive electrical read-outs were used to prove if an offline monitoring of selected I/Os can be used to track the overall specimen health throughout the experiment. Analyses of the samples are in progress including extensive cross sectioning. Though no damages were seen at the BEoL structures nor first level interconnects, severe damage of the second level interconnects is proven and certainly caused by the specific board pad design. In addition, board design features such as trace routing seem to have an influence on the second level solder joint reliability as well. However, based on the accomplished number of TCoB cycles and analysis results a high package level robustness of the FCCSP can be concluded and proposals for the board design can be derived.

The focus of this study is a grain structure analysis of hybrid Cu/SiO 2 wafer-to-wafer bonding interconnects after reliability testing. Hybrid bonding also known as direct bond interconnect is a very promising technology for fine pitch bonding without solder capped microbumps. The elimination of solder enables smaller bonding pitches and smaller interconnect sizes. The main challenge of the hybrid bonding technology is the preparation of a clean Cu/SiO 2 surface with a required Cu dishing. The development of the Cu grain structure after hybrid bonding and after reliability testing was investigated in detail in this study. The wafer-to-wafer stack with Cu interconnects (diameter 4 μm and pitch 18 μm) enclosed by SiO 2 was prepared. This wafer stack was diced into small pieces after successful bonding for further reliability testing. Two types of tests were carried out according to JEDEC standards: temperature shock test at −40°C / +125°C with up to 1000 cycles and isothermal storage at 150°C, 300°C, and 400°C. The resulting microstructure was characterized by scanning electron microscopy (SEM) and electron backscatter diffraction (EBSD). The results show that Cu/Cu interconnects have a {111} texture parallel to the bonding interface that barely changes with reliability testing. EBSD indicates the intergrowth between the Cu grains after the isothermal storage. Significant grain coarsening was found for the isothermal storage at 400 °C in comparison to the state after bonding. The details of the bonding interface (defects and grain boundaries) are presented as well and discussed with regard to recent publications.

The impact of strain, induced by nanoindentation, on integrated circuit performance is measured. Localized strain caused by chip- package interaction alters the charge carrier mobility in the transistor channel due to the piezoresistive effect. Instrumented indentation enables to induce controlled localized loads with high lateral precision, and it is used to apply consecutive loading conditions to a single test device. Newly designed ring oscillator test structures manufactured in 22 nm FDSOI technology are used as a sensor to monitor the strain effect on transistor performance. Novel tip geometries provide insight into the direction dependent strain impact. Strain/stress fields at transistor level are determined by complementary FEM simulation. Board bending experiments with uniaxial stress/strain conditions are performed to verify the approach. The established correlation of mechanical load and device performance is used to provide an estimate for the effect of package related stress on transistor performance.

Chip-package interaction-caused mobility degradation in CMOS transistors is a critical degradation mechanism for microelectronic devices. An approach based on nondestructive indentation is applied to induce highly localized stress fields. Strain-sensitive ring oscillator circuits are integrated to monitor parametric deviations during mechanical loading. In this study, the indentation technique is used to investigate the impact of the chip layout and geometry of a flip chip-packaged test chip. Complementary FE simulation provides a better understanding of the relevant stress-strain fields and enables a comparison of the parametric circuit deviations within a dedicated stress tensor. The results demonstrate the capability to study the stress-strain distribution in microelectronic devices during external loading with indentation and to determine its impact on transistor degradation.

In this study, a universal modular test setup for a variety of high density package concepts with ball pitches smaller than 0.4 mm is presented. It enables bias loading and online monitoring of multiple test specimens during accelerated environment stress testing according to AEC grade 1 conditions. Humidity is a critical factor when reducing ball pitch and introducing innovative casting compounds (e. g. epoxy resins) for electronic packaging. Therefore, its influence has to be investigated and a reliable test setup is required. The focus of this study is on the overall performance of the test setup under test conditions for storage at temperature and humidity. Experiments during board development were performed, including tests on material behaviour and surface effects due to narrow spacing between neighbouring traces, pads, or grid dimensions. The functionality of the developed test setup is demonstrated by electrical measurements at specimen level and setup system level before, during, and after temperature humidity storage. Potential failure modes at die, package, and board level can be investigated with the presented test setup.

With decreasing solder volumes and joint sizes, new aspects in electronics packaging occur. Previous publications report porous structures in Cu/Sn microbump interconnects after flux-assisted bonding and storage. The origin and mechanisms of pore formation are still discussed among researchers. In this study, the influence of no-clean flux during isothermal storage is investigated on soldered Cu/SnAg3.5 microbumps with intermetallic compounds. Soldering was carried out on single dies in air atmosphere without cleaning agent at 240 °C for 15 min. Subsequent isothermal storage was performed in air and N2 atmosphere at 240 °C for 1 min, 10 min and 20 min. The microbumps were exposed to flux and flux fumes during isothermal storage. Reference samples were stored separately without any flux contact. The results show pores in samples with flux contact of any kind. Inert atmosphere seems to diminish pore formation. The study reveals different residue appearances on and around the microbumps according to different storage conditions. Reasons for pore formation are also discussed in this study.

Solid-liquid interdiffusion (SLID) interconnectsbased on Cu and Sn-solder are excellent candidates forstacking of Si chips in 3D integration. If the high-temperaturestable intermetallic compound (IMC) Cu3Sn is desired, themanufacturing of the interconnect can be very time consuming(long annealing time for growth of Cu3Sn). In this paper wepropose a method for the accelerated formation of Cu-Cu3Sn-Cu interconnects by selective dissolution of Sn from Cu6Sn5. This leads to a porous network of Cu3Sn. The influence oftemperature, flux and atmosphere onto the pore formation willbe addressed in detail.