Search

In CMOS chips, the wider layout rules were traditionally applied to overcome latch-up issues. However, the chip area with wider layout rules was often enlarged, and in turn the chip cost was also increased. To effectively improve latch-up immunity without enlarging the chip area, circuit methods were therefore invented. An overview on circuit methodology used to prevent latch-up issues in CMOS integrated circuits (ICs) is presented in this article. The circuit solutions, including reducing the I/O pad trigger current, sensing the trigger current to control the power supply, and restarting the power supply through an MOS switch to shut off the latch-up current, are overviewed.

As the high-voltage (HV) and low-voltage (LV) circuits are integrated together in a common silicon substrate, the parasitic latch-up path between neighboring HV and LV circuits with limited spacing in layout would be triggered into latch-up state to cause unrecoverable failure in the chip. In this work, the isolation ring of HV n-well (HVNW) / N-buried layer (NBL) with Schottky-embedded junction to overcome the lateral HV-to-LV latch-up path was proposed and verified in a $0.18{\mu }\text{m}$ HV bipolar-CMOS-DMOS (BCD) technology. From the experiment results of the proposed Schottky-embedded isolation ring, the holding voltage (Vh) in the lateral HV-to-LV parasitic latch-up path can be increased to be greater than the voltage difference between the different power supplies of the neighboring HV and LV circuits. Furthermore, the layout spacing between the neighboring HV and LV circuits can be significantly reduced to save chip area. The proposed Schottky-embedded isolation ring is a cost-effective solution to provide good latch-up immunity among the HV-to-LV circuit blocks with a short layout distance.

High-power electromagnetic pulses can transmit a large induced electromotive force or energy through metal interconnection lines, causing interference or damage to integrated circuits. CMOS circuits are the basic components of sensors, so sensors that work in an electromagnetic environment may malfunction. It is of great importance to study the antielectromagnetic damage technology of CMOS inverters. On the basis of the simulation using Sentaurus, an electrothermal coupling model of a 55 nm CMOS inverter is established. The simulation results show that the latch-up effect is the main mechanism of CMOS failure. In view of the failure process under different high-power microwave (HPM) pulse parameters, we propose a CMOS inverter reinforcement technology. Research shows that the source injection current of the reinforced structure is more than ten times less than that of the traditional structure under electromagnetic interference, which effectively suppresses the occurrence of latch-up. [ABSTRACT FROM AUTHOR]

A high-speed wireline interfaces, e.g. LVDS (Low Voltage Differential Signaling), are widely used in the aerospace field for powerful computing in artificial satellites and aircraft [19]. This paper describes Bit Error Rate (BER) prediction methodology for wireline data transmission under irradiation environment at the design stage of data transmitter, which is useful in proactively determining if the design circuit meets the BER criteria of the target system. Using a custom-designed LVDS transmitter (TX) to enhance latch-up immunity [42], the relationship between transistor size and BER has been analyzed with focusing on Single Event Effect (SEE) as a cause of the bit error. The measurement was executed under 84Kr17+ exposure of 322.0 MeV at various flux condition from 1 × 103 to 5 × 105 count/cm2/sec using cyclotron facility. For the analysis of the bit error, circuit simulation by SPICE was utilized with expressing the irradiation environment by a current source model. The current source model represents a single event strike into the circuit at drain and substrate junctions in bulk MOSFETs. For the construction of the current source model, a charge collection was simulated at the single particle strike with the creation of 3D Technology CAD (TCAD) models for the MOS devices of bulk transistor process technology. The simulation result of the charge correction was converted to a simple time-domain equation, and the single-event current source model was produced using the equation. The single-event current source was applied to SPICE simulation at bias current related circuits in the LVDS transmitter, then simulation results are carefully verified whether the output data is disturbed enough to cause bit errors on wireline data transmission. By the simulation, sensitive MOSFETs have been specified and a sum of the gate area for these MOSFETs has 29% better correlation than the normal evaluation index (sum of the drain area) by comparison to the actual BER measurement. Through the precise revelation of the sensitive area by SPICE simulation using the current model, it became possible to estimate BER under irradiation environment at the pre-fabrication design stage. [ABSTRACT FROM AUTHOR]

IDeF-X HD is a 32-channel analog front-end with self-triggering capability optimized for the readout of 1 6 × 1 6 pixels CdTe or CdZnTe pixelated detectors to build a low power micro-gamma camera. IDeF-X HD has been designed in the standard AMS CMOS 0.35 μ m process technology. Its power consumption is 800 μ W per channel. The energy range of the ASIC can be extended to 1.1 MeV thanks to the in-channel adjustable gain stage. When no detector is connected to the chip and without input current, a 33 electrons rms ENC level is achieved after shaping with 10.7 μ s peaking time. Spectroscopy measurements have been performed with CdTe Schottky detectors. We measured an energy resolution of 4.2 keV FWHM at 667 keV ( 1 3 7 Cs) on a single-pixel configuration. Meanwhile, we also measured 562 eV and 666 eV FWHM at 14 keV and 60 keV, respectively ( 2 4 1 Am) with a 256 small pixel array and a low detection threshold of 1.2 keV. Since IDeF-X HD is intended for space-borne applications in astrophysics, we evaluated its radiation tolerance and its sensitivity to single event effects. We demonstrated that the ASIC remained fully functional without significant degradation of its performances after 200 krad and that no single event latch-up was detected putting the linear energy transfer threshold above 110 MeV/(mg/cm2). Good noise performance and radiation tolerance make the chip well suited for X-rays energy discrimination and high energy resolution. The chip is space qualified and flies on board of the solar orbiter ESA mission launched in 2020. [ABSTRACT FROM AUTHOR]

Abstract A novel CMOS-process-compatible high-holding voltage silicon-controlled rectifier (HHV-SCR) for electrostatic discharge (ESD) protection is proposed and demonstrated by simulation and transmission line pulse (TLP) testing. The newly introduced hole (or electron) recombination region H-RR (or E-RR) not only recombines the minority carrier in parasitic PNP (or NPN) transistor base by N+ (or P+) layer, but provides the additional recombination to eliminate the surface avalanche carriers by newly added P+ (or N+) layer in H-RR (or E-RR), which brings about a further improvement of holding voltage (V h). Compared with the measured V h of 1.8 V of low-voltage triggered silicon-controlled rectifier (LVTSCR), the V h of HHV-SCR can be increased to 8.1 V while maintaining a sufficiently high failure current (I t2 > 2.6 A). An improvement of over four times in the figure of merit (FOM) is achieved.

The silicon-controlled rectifier (SCR) has been reported to protect CMOS integrated circuits (ICs), due to high ESD robustness within a small silicon area. However, the holding voltage (Vh) of the SCR device was too low to suffer the latch-up issue. Thus, the Vh value of the SCR device must be improved to be greater than the circuit operating voltage for safe applications. In this work, the Schottky-embedded modified lateral SCR (SMLSCR) with high holding voltage for ESD protection was proposed and verified in a 0.18-μm 1.8-V/3.3-V CMOS process. By using the Schottky barrier junction, the Vh value of the SCR device can be improved by the reverse-bias Schottky barrier diode (SBD) that is embedded into the SCR device structure. Among those experimental results on the SMLSCR devices with split layout parameters in the silicon test chip, the SMLSCR device without P+ guard ring has the best second breakdown current (It2) of 3.1 A and a high Vh value of 9.7 V. [ABSTRACT FROM AUTHOR]

A power-efficient, voltage gain enhancement technique for op-amps has been described. The proposed technique is robust against Process, Voltage and Temperature (PVT) variations. It exploits a positive feedback-based gain enhancement technique without any latch-up issue, as opposed to the previously proposed conductance cancellation techniques. In the proposed technique, four additional transconductance-stages (gm stages) are used to boost the gain of the main gm stage. The additional gm stages do not significantly increase the power dissipation. A prototype was designed in 65 nm CMOS technology. It results in 81 dB voltage gain, which is 21 dB higher than the existing gain-boosting technique. The proposed op-amp works with as low a power supply as 0.8 V, without compromising the performance, whereas the traditional gain-enhancement techniques start losing gain below a 1.1 V supply. The circuit draws a total static current of 295 μ A and occupies 5000 μ m2 of silicon area. [ABSTRACT FROM AUTHOR]

This article discusses the robustness of field-plate-assisted reduced surface field effect (RESURF) DMOS designs to time-dependent latch-up within a single dielectrically isolated device. This work individually characterizes the dopant defined parasitic bipolar parallel to all MOS and uniquely describes the existence of another parasitic bipolar of opposite polarity through the generation of a backgate current as a result of weak impact ionization. These two NPN and PNP bipolar devices in a single DMOS device complete the latch-up mechanism once the product of their gains is greater than one. The characterized time-dependent nature of the increasing backgate current is accounted for by oxide charge trapping in the extended drain region, where measurements of this mechanism over a broad range of application and manufacturing variables enable a mathematical model for the time to failure to be described. Finally, the advantage of analyzing DMOS latch-up robustness in the context of individual parasitic NPN and PNP bipolar devices is shown by its ability to isolate out the separate variables feeding into each bipolar to implement robust solutions. [ABSTRACT FROM AUTHOR]

Described the generation theory of negative voltage and negative current in Latch-up test and the theory of chain reaction caused by inner parasitic bipolar transistor. Then analyzed the influence of negative current in chip level with examples of analog voltage buffer and LDO. Finally, proposed a series of action list of how to protect negative current in chip level.

This paper explains the hidden positive feedback in a two-stage fully differential amplifier through external feedback resistors and possible DC latch-up during the amplifier start-up. The biasing current selection among the cascade branches has been explained intuitively, with reference to previous literature. To avoid the latch-up problem, irrespective of the transistor bias currents, a novel hysteresis-based start-up circuit is proposed. An 87 dB, 250 MHz unity gain bandwidth amplifier has been developed in 65 nm CMOS Technology and post-layout simulations demonstrate no start-up failures out of 1000 Monte-Carlo (6-Sigma) simulations. The circuit draws 126 μ A from a 1.2 V supply and occupies the 2184 μ m2 area. [ABSTRACT FROM AUTHOR]

We investigate the difference in the probability of latch-up occurrence in complementary metal–oxide–silicon (CMOS) circuits exposed to neutron radiation and total ionizing dose (TID), which are subsequently exposed to pulsed gamma rays. First, we irradiate three types of CMOS circuits in a reactor for neutron exposure and in a Co-60 unit for TID exposure respectively, which are then placed in a pulsed gamma-ray environment. The latch-up induced by pulsed gamma-ray irradiation is studied. Our experimental results indicate that the manifestation of the latch-up phenomenon is different among the devices after neutron irradiation and TID exposure, thereby indicating that the influences of neutron and TID exposures on the latch-up sensitivity are different. To understand how the latch-up sensitivity changes, we study a dynamic model for latch-up occurrence and analyse the influences of neutron and TID exposure using the model. Our results indicate that neutron injection reduces the susceptibility of latch-up occurrence, whereas TID exposure increases the latch-up occurrence susceptibility. Therefore, in the case of CMOS circuits exposed to pulsed gamma-ray irradiation, the latch-up threshold decreases with TID accumulation, but increases with neutron fluence augmentation. Interestingly, the latch-up threshold drops when the neutron fluence is sufficiently large, mainly because concomitant gamma rays in the reactor environment play an important role in affecting the threshold. [ABSTRACT FROM AUTHOR]

On-chip decoupling capacitors often formed by varactor or nMOS have been widely used to shunt the power-line noise in integrated-circuit products. Because the N+ cathode of these capacitors is connected to ground, an unexpected latch-up path between I/O pMOS and n-type decoupling capacitors may be accidentally triggered on. In this paper, the non-typical latch-up path between I/O pMOS and n-type decoupling capacitors was investigated in 0.18- ${\mu }\text{m}$ 1.8/3.3-V CMOS technology. The measurement results from the silicon chip with split test structures have verified that the n-type decoupling capacitor near the I/O pMOS can cause a high risk of latch-up. Therefore, the layout rules between the decoupling capacitor and I/O devices should be carefully defined to prevent the occurrence of such an unexpected latch-up path. [ABSTRACT FROM AUTHOR]

A new optimization design of an active guard ring has been proposed to improve latch-up immunity of CMOS integrated circuits and been successfully verified in a 0.18- $\mu \text{m}$ 1.8-/3.3-V CMOS technology. Codesigned with the on-chip electrostatic discharge (ESD) protection devices (gate-ground nMOS and gate-VDD pMOS) equipped at the input–output (I/O) pad, the overshooting/undershooting trigger current during latch-up test can be conducted away through the turned-on channels of the ESD protection MOSFET’s to the power rails (${V}_{\textsf {DD}}$ or ${V}_{\textsf {SS}}$). Therefore, the trigger current injecting from the I/O devices (that directly connected to the I/O pad) through the substrate to initiate the latch-up occurrence at the internal circuit blocks can be significantly reduced. Thus, the latch-up immunity of the whole chip can be effectively improved under the same placement distance between the I/O cells and the internal circuit blocks. The new proposed design is a cost-efficient solution to improve latch-up immunity and also to mention good ESD robustness of the I/O cells. [ABSTRACT FROM AUTHOR]

A novel snapback-free silicon-controlled rectifier (SFSCR) with P-type Zener implantation (ZP) is developed in a 0.5- $\mu \text{m}$ bipolar CMOS DMOS technology for latch-up immune high-voltage (HV) electrostatic discharge (ESD) protection. The inherent snapback of SCR is successfully suppressed by the novel ZP technique. But, it also brings about a serious degradation in failure current (${I}_{\textsf {t2}}$) when compared with the regular low holding voltage (${V}_{h}$) device. In order to mitigate such degradation, a novel layout terminal is proposed. According to the transmission-line pulse test results, ${I}_{\textsf {t2}}$ of the SFSCR with new layout is increased by 58.5%, while the ON-state resistance (${R}_{ \mathrm{\scriptscriptstyle ON}}$) is reduced by 48.7% under the same layout area. By comprehensive comparison, the SFSCR is proved to be a potential HV ESD solution. [ABSTRACT FROM AUTHOR]

For some applications, the CMOS ICs need to be supplied with positive and negative voltage sources for the desired circuit operations. To supply the negative voltage source for circuit operations in the silicon chip with the common p-type substrate grounded, the isolation rings configured with n-well (NW) and deep n-well (DNW) layers must be used to isolate the circuits of nMOS devices operating with negative voltage from the common P-substrate. Such NW/DNW isolation rings in the circuit layouts are often connected to ground (GND =0V) for the circuit operations with negative voltage source. But, a parasitic p-n-p-n path from I/O pMOS to this grounded NW/DNW isolation ring may cause the circuits at high risk to latch-up. In this letter, a novel method to improve latch-up immunity against such parasitic p-n-p-n path by using a Schottky junction is reported. [ABSTRACT FROM AUTHOR]

The influences of three typical latch-up immunity structures, including high concentrated P++ doping layer, N+/P+ segmented emitter and P-sink well, upon electro-static discharge (ESD) robustness of the silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) devices are compared. The high concentrated P++ doping layer makes the SOI-LIGBT have the weakest ESD robustness, because the slow turn-on speed of parasitic n-p-n transistor brings long-time high power state and heat accumulation. The N+/P+ segmented emitter causes the SOI-LIGBT to own the medium ESD robustness and the SOI-LIGBT fails at the emitter side due to the crowded current made by the small N+ emitter region. For the P-sink well, it makes SOI-LIGBT exhibit the strongest ESD robustness, because the current can flow along the P-sink into the emitter vertically, which is helpful for reducing surface current density. Considering the comprehensive performances, the P-sink well is suggested as the latch-up immunity structure, which guarantees high latch-up immunity ability and strong ESD robustness simultaneously. [ABSTRACT FROM AUTHOR]

In this paper, A newly Silicon Controlled Rectifier (SCR)-based Electric Static Discharge (ESD) protection circuit is proposed. The proposed circuit has the latch-up immunity in normal operating conditions with the high holding voltage by inserting the floating regions. To verify the electrical characteristics, a Technology Computer Aided Design (TCAD) simulation is performed by setting each of variables: D1, D2, D3, and D4. The results of the simulation show that the proposed protection circuit has the holding voltage 5 V higher than the conventional circuits and has the same level of robustness properties as the existing SCR. In addition, the proposed circuit is fabricated through a 0.18 μm Bipolar-CMOS-DMOS process. The electrical characteristics are confirmed by measuring Transmission Line Pulse, and the robustness properties are measured through Human Body Model (HBM) and Machine Model (MM). The holding voltage is about 20 V, which has the increases above 18 V or more compared to the conventional SCR. Therefore, the proposed circuit is proved to have the better ESD protection performance than HBM 8 kV and MM 800 V higher than HBM 2 kV and MM 200 V, the commercial standard. [ABSTRACT FROM AUTHOR]

This paper proposes an advanced high holding voltage silicon controlled rectifier (AHHVSCR) with a new structure with an insertion of PMOS (P-type metal-oxide-semiconductor). To verify the characteristics of the proposed ESD protection circuit and analyze its operating characteristics, a comparative analysis of electrical characteristics with HHVSCR (High Holding Voltage SCR), was conducted by using TCAD simulation. HBM(Human Body Model) maximum temperature test results confirmed that the proposed ESD protection circuit has a maximum temperature value of 355K, which is about 20K lower temperature characteristic than that of HHVSCR (373K), indicating more improved robustness. In addition, the proposed ESD protection circuit was designed by applying N-STACK technology, and its applicability by voltage was verified through simulations. The proposed ESD protection circuit was designed and fabricated using 0.18um BCD process, and the validity of its electrical characteristics was confirmed using TLP (Transmission Line Pulse) system. The proposed ESD protection circuit has improved latch-up immunity with holding voltage of 18.42V, which is 7.7V higher than HHVSCR in a single structure, and it can be applied by voltage with increased holding voltage characteristics of 2-STACK 45.81V and 3-STACK 76.51V according to the application of N-STACK technology. [ABSTRACT FROM AUTHOR]

In this paper, a numerical description of the ruggedness of punch-through (PT) IGBTs under the unclamped inductive switching (UIS) has been proposed using two-dimensional (2D) simulations with the calibration to experimental results. The UIS capability is an important design factor of device structures for the purpose of screening defects produced during the wafer process. The local hot spot due to the current filament three-dimensionally (3D) distributed over the chip area requires 3D simulations to reproduce the current density of the filament and its behavior leading to the device destruction; however, it is difficult to simulate such a large area with an appropriate mesh size and a boundary condition. To provide a possible solution of this technical issue, 2D simulations using large scale multi-cell structures with the increased current density has been proposed to reproduce experimental results without resorting to 3D simulations. With this approach, not only destructive phenomena including the UIS ruggedness and the latch-up failure mode have been reproduced, but also the device internal state leading to the destruction has been revealed. The spatial distribution of the electric potential and the lateral electric field during the UIS condition is shown to be a key role determining the current filament width and the UIS ruggedness. Besides, the high frequency oscillation of the collector voltage during the UIS observed by experiments has been analyzed and has found to be related with the hopping motion of the current filament from a cell to its neighboring cell of the device. [ABSTRACT FROM AUTHOR]

The insulated-gate bipolar transistor (IGBT) has a parasitic thyristor. Latch-up can occur when the current density exceeds a particular current density. Conventional methods employed to increase the latching current density will lead to some other performance degradations. To overcome these problems and further increase the latching current density of IGBT, a novel IGBT with a floating N-doped buried layer in P-base is proposed. By implanting a floating N-doped buried layer in the P-base, the hole current flowing underneath the N+ emitter can be reduced significantly. Thus, the current density that is needed to trigger the latch-up of the parasitic thyristor increases. Numerical simulation results show that the proposed IGBT can increase the latching current density by more than 100% without compromising the output and switching characteristics when compared with the conventional IGBT. [ABSTRACT FROM PUBLISHER]

We investigate a novel lateral diffused metal-oxide semiconductor (LDMOS) device embedded in silicon controlled rectifier (SCR) and resistance-capacitance circuit (LDMOS-SCR-RC). The internal RC-coupling effect helps to increase the holding current ( I h ), resulting in the enhanced latch-up immunity of electrostatic discharge (ESD) protection device in high voltage integrated circuits (HV ICs). Transmission line pulse testing results show that the proposed LDMOS-SCR-RC has the largest I h and smallest trigger voltage ( V t 1 ), comparing to the conventional LDMOS-SCR and LDMOS-SCR embedded a resistance. When key parameters such as the gate-length and resistance are optimized, the I h increases further from 1.1 A to 1.5 A, while the V t 1 changes insignificantly. The detailed internal mechanism of LDMOS-SCR-RC with regard to key parameters is analyzed numerically by the SENTAURUS simulation. Results confirm that the increased I h is mainly due to the enhanced RC-coupling effect. Finally, DC measurements conducted with a semiconductor curve tracer also confirm that the LDMOS-SCR-RC with small device area is effective for avoiding latch-up risks. The optimized LDMOS-SCR-RC provides a useful latch-up immune ESD protection solution for HV ICs input/output ports. [ABSTRACT FROM AUTHOR]

This paper proposes a new concept of Schottky contact insulated-gate bipolar transistor (SC-IGBT), which uses a top surface Schottky contact to the p-base as a hole barrier to enhance the conductivity modulation effect. TCAD simulation shows that the SC-IGBT offers a saturation voltage decrease of 19% or turn-OFF loss reduction of 46% when compared with a conventional field-stop IGBT. Furthermore, it potentially offers an alternative method of fabricating injection enhancement IGBTs, which is simpler than the existing buried n-type layer or narrow mesa trench structures. [ABSTRACT FROM AUTHOR]

Memory is the essential part of System on Chip applications. The analysis of memories is not an easy task to calculate any parameter in a single step. Tools are operated on a standard basis. It neglects all the issues of the device either it may be a MOSFET or a BJT or any emerging device. All tools provide standardized devices but they do not include following issues like sub threshold leakage, punch through, body effect and latch up in inverters. In any circuit when we scale down the technology then, all effects are taken into account. The parasitic diodes are inherent between the n-well and p-substrate or p-well and n-substrate all to be the latch up occurrence in this System on Chip. Latch up failure mainly occurs and find out only on output pin of the IC. In memories, latch up effects gives effective degradation in data mostly in hold mode. In this paper, we calculated the reduced effect of single event latch-up using FinFET based 7T SRAM Cell and this result is diminished as compare to conventional based 7T SRAM Cell. [ABSTRACT FROM AUTHOR]

Unexpected device interactions between ESD diodes and NMOS clamps in isolated P-well (triple well) have been observed. This can lead to an SCR-like $I$– $V$ behavior in TLP measurements and poses a latch-up risk. The cause of this interaction is being analyzed using equivalent circuits with parasitic devices and by TCAD simulations. [ABSTRACT FROM PUBLISHER]

In general, the antielectrostatic discharge (ESD) ability of a high voltage (HV) MOSFET device will be very low if it is not optimized through the addition of reliability engineering. Accordingly, in this paper, some embedded superjunction (SJ) device under tests (DUTs) of 45-V HV n-channel lateral-diffused MOS (nLDMOS) are developed, which offer a low on-resistance as compared with the traditional nLDMOS due to the redistribution of electric field or/and higher doping density in the drain side. In order to evaluate how various physical parameters affect the anti- ESD capability, these DUTs will change the widths and shapes of the P/N pillars. From the testing results, it can be found that the It2 values of SJ-nLDMOS DUTs will be higher than that of a traditional nLDMOS, while the equivalent immunity level is even greater than HBM 10 kV. In this paper, the It2 values of developed SJ-nLDMOS DUTs were increased at least by 109%, 31%, and 159% over that of the traditional nLDMOS for the Types 1-3 embedded SJ, respectively. Moreover, in some geometry architectures of an SJ-LDMOS, the holding voltage can be greater than the traditional nLDMOS. Therefore, by considering the relationships between these three kinds of SJ-nLDMOS DUTs and the It2 values, it can be determined that the SJ structure is good for ESD/latch-up immunities especially for the ESD reliability. [ABSTRACT FROM AUTHOR]

An analytical model of transient latch-up in CMOS transmission gate induced by laser is established. The time-dependent current characteristics of the parasitic silicon controlled rectifier (SCR) under different injected photocurrent are illustrated. The model analyzes the trigger conditions for latch-up and describes the dynamic process varying with time. The photocurrent threshold causing latch-up under different pulse widths and repetition frequencies is obtained, which agrees well with the experimental results reported in the literature. [ABSTRACT FROM AUTHOR]

Smart power technologies are required to withstand high-electrostatic-discharge (ESD) robustness under both powered and unpowered conditions, particularly for automotive and aeronautic applications among many others. They are concurrently confronted to the challenges of high-temperature operation in order to reduce heat-sink-related costs. In this context, very compact high-robustness ESD protections with low sensitivity to temperature are required. To fulfill this need, we studied a new ESD protection structure that combines in the same component MOS, IGBT, and thyristor effects. This is achieved by inserting in the same LDMOS device \P^+ diffusions in the drain. We studied the impact of \N^+/\P^+ ratios on RON and holding current at high temperatures. Structure optimization has been realized with 3-D TCAD simulation and experimentally validated. The proposed structures provide high ESD robustness with small footprint and reduced temperature sensitivity compared with classical solutions. Original design solutions to improve their immunity to latchup are also presented. [ABSTRACT FROM PUBLISHER]

This paper evaluates the technique used to improve the latching characteristics of the 200 V n-type superjunction (SJ) lateral insulated-gate bipolar transistor (LIGBT) on a partial silicon-on-insulator. SJ IGBT devices are more prone to latch-up than standard IGBTs due to the presence of a strong pnp transistor with the p layer serving as an effective collector of holes. The initial SJ LIGBT design latches at about 23 V with a gate voltage of 5 V with a forward voltage drop (VON) of 2 V at 300 A/cm^2. The latch-up current density is 1100 A/cm^2. The latest SJ LIGBT design shows an increase in latch-up voltage close to 100 V without a significant penalty in VON. The latest design shows a latch-up current density of 1195 A/cm^2. The enhanced robustness against static latch-up leads to a better forward bias safe operating area. [ABSTRACT FROM PUBLISHER]

The latch-up immunity of the high voltage power clamps used in high voltage ESD protection devices is very becoming important in high-voltage applications. In this paper, a stacking structure with a high holding voltage and a high failure current is proposed and successfully verified in 0.1 8um CMOS and 0.35um BCD technology to achieve the desired holding voltage and the acceptable failure current. The experimental results show that the holding voltage of the stacking structure can be larger than the operation voltage of high-voltage applications. Changes in the characteristics of the stacking structure under high temperature conditions (300K-500K) are also investigated. [ABSTRACT FROM AUTHOR]

The pulse width control circuit of DC-DC converters utilizing an inrush current controller was designed to ensure proper pumping action and avoid latch-up during power-up. The converters with controllable latch-up protection technique were excellently operated at temperatures above 90°C and heavy load capacitances of Mobile LCD panels. [ABSTRACT FROM AUTHOR]

Abstract: Formation of lateral thin-film 700-V insulated-gate bipolar transistors (IGBTs) on Si-semiconductor-on-insulator (Si-SOI) substrates by using retrograde p-well double implantation scheme has been proposed. With a low thermal budget for p-well formation, retrograde high-energy boron implantation is employed to cause a high dopant concentration in the bulk region, and additional low-energy boron implantation is carried out for alleviating the surface punch-through of MOSFET (metal-oxide-semiconductor-field-effect-transistor) structure. As compared to the conventional p-well formation process, the retrograde double implantation scheme can lead to better latchup immunity, due to a considerably higher dopant concentration and thus lower well resistance in the p-well bulk region. In addition, owing to a lower surface dopant concentration, the retrograde double implantation scheme can lead to better on-state characteristics than the conventional process, while achieving comparable blocking voltage. [Copyright &y& Elsevier]

Abstract: The proposed device has a high holding voltage and a high triggering current characteristic. These characteristics enable latch-up immune normal operation as well as superior full chip electro-static-discharge (ESD) protection. The device has a small area in requirement robustness in comparison to gate-grounded NMOS (ggNMOS). The proposed ESD protection device is designed in 0.25μm CMOS technology. In the experimental result, the proposed ESD clamp has a double trigger characteristic, a high holding voltage of 3.8V and a high trigger current of greater than 120mA. The robustness has measured to HBM 8kV (HBM: human body model) and MM 400V (MM: machine model). The proposed device has a high-level It2 of 52mA/μm approximately. [Copyright &y& Elsevier]

Abstract: Latch-up effects in two stage cascaded CMOS digital inverters due to high power pulsed electromagnetic interference, are reported. Latch-up was observed to occur at and above 25.5dBm of pulsed interference at frequencies of 1.23GHz and 4GHz. When a latch-up event occurred, the devices failed to respond to the input logic signal even after the pulsed interference was removed. Devices required to be reset to return to normal operation. Latch-up for pulsed interference at the higher frequency of 4GHz occurred at higher power levels, indicating a suppression of the interference effects at higher frequencies due to the by-pass path effects provided by the intrinsic device capacitances. High power interference induced excess carriers and the corresponding body currents that activated the parasitic bipolar transistor action were found to play a key role in triggering the latch-ups, and are proposed here as the main mechanism for the upsets. The parasitic resistances R1 and R2 for the cascaded inverters were calculated to be 4.3 and 2.8kΩ, respectively, and the corresponding excess body currents triggering the latch-ups were 0.163 and 0.25mA, respectively. [Copyright &y& Elsevier]

To accurately evaluate the immunity of CMOS ICs against transient-induced latch-up (TLU) under the system-level electrostatic discharge (ESD) test for electromagnetic compatibility (EMC) regulation, an efficient component-level TLU measurement setup with bipolar (underdamped sinusoidal) trigger is developed in this paper. A current-blocking diode and a current-limiting resistance, which are generally suggested to be used in the TLU measurement setup with bipolar trigger, are investigated for their impacts to both the bipolar trigger waveforms and the TLU immunity of the device under test (DUT). All the experimental results have been successfully verified with device simulation. Finally, a TLU measurement setup without a current-blocking diode but with a small current-limiting resistance, which can accurately evaluate the TLU immunity of CMOS ICs with neither overestimation nor electrical-over-stress damage to the DUT during the TLU test, is suggested. The suggested measurement setup has been verified with silicon-controlled-rectifier test structures and real circuitry (ring oscillator) fabricated in 0.25-mum CMOS technology [ABSTRACT FROM PUBLISHER]

Abstract: This paper investigates the performance of single and multiple junction isolation structures for smart power IC’s with regards to transient carrier injection. Both, single and multiple isolation structures are produced using a standard CMOS process all using the same surface area. The devices are based on different active junction isolation principles and it is shown that combinations of these devices can significantly improve the blocking characteristics of the isolation without an increase in surface area. It is shown that the transient current rejection of the devices is markedly different from their dc blocking characteristics. Considerations for the design of efficient isolation structures are discussed. [Copyright &y& Elsevier]

Abstract: In this paper, a new lateral insulated gate bipolar transistor (LIGBT) structure is proposed to suppress substrate currents in a junction isolated technology by using two buried layers on top of each other. This structure not only allows to reduce the substrate to anode current ratio to less than 10−7, it also yields a device with a large safe operating area and a fast turn-off. Because of the two buried layers, the proposed LIGBT can be used as a floating (above substrate potential) device. Furthermore, the LIGBT is introduced in an existing 80 V smart power technology without the costly need of defining new layers. It has also been shown that the proposed LIGBT can compete with vertical DMOS (VDMOS) devices when used as a large driver. Together with an equivalent circuit, two dimensional simulation has been used to explain the observed device’s substrate current behaviour. [Copyright &y& Elsevier]

This paper describes the design and implementation of fully integrated rectifiers in BiCMOS and standard CMOS technologies for rectifying an externally generated RF carrier signal in inductively powered wireless devices, such as biomedical implants, radio-frequency identification (RFID) tags, and smartcards to generate an on-chip dc supply. Various full-wave rectifier topologies and low-power circuit design techniques are employed to decrease substrate leakage current and parasitic components, reduce the possibility of latch-up, and improve power transmission efficiency and high-frequency performance of the rectifier block. These circuits are used in wireless neural stimulating microsystems, fabricated in two processes: the University of Michigan's 3-µm 1M/2P N-epi BiCMOS, and the AMI 1.5-µm 2M/2P N-well standard CMOS. The rectifier areas are 0.12-0.48 mm² in the above processes and they are capable of delivering > 25 mW from a receiver coil to the implant circuitry. The performance of these integrated rectifiers has been tested and compared, using carrier signals in 0.1-10-MHz range. [ABSTRACT FROM AUTHOR]

In this work, we explore the worst case bias response of fully depleted transistors. Floating body and external body ties transistors fabricated on different SOI substrates are characterized using X-rays. The Influence of gate length is presented. The coupling effect between front and back gate as well as latch triggered by floating body effect are evaluated as a function of dose level. [ABSTRACT FROM AUTHOR]

The paper reports on a set of measurements which were carried out to test the influence of single event upset (SEU) effects on the performance of the VA1TA chip, the front end read-out electronics unit of the upgraded silicon vertex detector for the Belle spectrometer. In addition, the functionality of the SEU correction circuits in the chip were examined. [Copyright &y& Elsevier]

A new Lateral Trench Electrode Insulated Gate Bipolar Transistor (LTEIGBT) with a p+ diverter was proposed and fabricated to improve the electrical characteristics of the conventional LTIGBT. The p+ diverter was placed between anode and cathode electrodes. Because the p+ diverter region of the proposed device was enclosed trench oxide layer, the electric field centered trench-oxide layer, and punch through breakdown of LTEIGBT with p+ diverter was occurred at the high breakdown voltage. Therefore, the p+ diverter of the proposed LTIGBT didn't relate to breakdown voltage in a different way the conventional LTIGBT. As a results of device simulation, the electrical characteristics of the proposed LTEIGBT including latching current density, breakdown voltage and switching speed was superior to conventional devices. After simulation was finished, we fabricated and analyzed the proposed LTEIGBT with a p+ diverter. The maximum current of the proposed device and conventional device were 90 mA and 70 mA, respectively. Therefore, The proposed LTEIGBT with a p+ diverter is effective device for smart power IC. [ABSTRACT FROM AUTHOR]

A new Lateral Trench Electrode Insulated Gate Bipolar Transistor (LTEIGBT) is proposed and fabricated to improve the characteristics of device. The entire electrode of LTEIGBT is placed to trench type electrode. The LTEIGBT is designed so that the width of device is 19µ. The Latch-up current densities of LIGBT, LTIGBT and LTEIGBT are 120A/cm², 540A/cm² and 1230A/cm², respectively. The maximum currents of the proposed LTEIGBT and the conventional LIGBT are 80mA and 70mA, respectively, at the same breakdown voltage of 150V. The forward blocking voltage of the LTEIGBT is 130V. At the same size, those of conventional LIGBT and LTIGBT are 60V and 100V, respectively. [ABSTRACT FROM AUTHOR]