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With the advent of the 5G era, power devices and telecom equipment require small form factor and excellent thermal performance. Flip-chip Land Grid Array (FC-LGA) is rapidly becoming the package choice for those devices, because of its low RDS (ON) and high frequency operation. However, it also brings great challenges to reliability design. Large number of flip chip solder joints between die and substrate lead to a more rigid package body, which will accumulate strong thermomechanical stress under alternating temperature and so inevitably trigger package reliability issues. Excessive warpage and body crack will occur if without appropriate package design consideration. In this study, the thermo-mechanical behaviors of FC-LGA were investigated by finite element simulation under different TCC conditions. Due to the complexity of the LGA substrate, the simulation with detail substrate model in use will incur expensive computation. This work proposed a simplification method considering a substrate of complicated structure as an equivalent anisotropic volume. With simulation models simplified, DoE study was performed to investigate the influence of packaging materials and geometry on the thermo-mechanical reliability of FC-LGA packages in high efficiency. A higher die-to-EMC thickness ratio will result in a more severe package convex warpage, while using a thinner die and a thicker EMC layer can prevent package body from cracking during heating or cooling processes. Besides packaging geometry, the influence of substrate layouts and EMC mechanical properties were also studied to find the optimal packaging design to mitigate the risks of excessive package warpage and body crack.

Purpose This paper aims to investigate and compare the reliability performance of land grid array (LGA) and ball grid array (BGA) solders, as well as the SAC105 and 63Sn37Pb solder alloys, in vibration loading conditions. Design/methodology/approach Reliability tests were conducted using a sine dwell with resonance tracking vibration experiment. Finite element simulations were performed to help in understanding the observed failure trends. Findings Reliability results showed that the tin-lead solders out-perform lead-free solders in vibrations loading. Additionally, the LGA solder type could provide a better vibration reliability performance than BGA solders. Failure analysis results showed that in LGAs, the crack is initiated at the printed circuit board side and at the component side in BGAs. In both types, the crack is propagated throughout in the intermetallic compound layer. Originality/value In literature, there is a lack of published data in the comparison between LGA and BGA reliability performance in vibration loadings. This paper provides useful insights in the vibration reliability behavior of the two common solder joint types.

There has been a great interest in the use of low temperature soldering (LTS) for surface mount technology (SMT) in the past five years. Low temperature solder (LTS) technology improves the package warpage by reducing thermo-mechanical stress during SMT reflow. Several other benefits with LTS include environmental benefits, decreased carbon emissions, and lower electricity consumption. In this study, LTS technology has been evaluated on several electronic components such as, Integrated circuit (IC), memory, ASIC, and passives. Using several LTS formulations, Solder Joint Reliability (SJR) properties were characterized EOL as well as after reliability testing at components suppliers. Several different package types (i.e. QFN, LGA, CSP, WLCSP etc.), and surface finishes were used in this study. For some of the IC components, different types of packages were evaluated: land grid array (LGA) and quad flat no leads (QFN). Different paste formulations having (35–58 wt.% Bi content) were used in these evaluations and SAC305 was the POR/control leg used. Temperature cycle and other reliability data showed promising results with comparable data for both LTS and SAC legs. The goal in this paper is to document some of the challenges in components supply chain enabling and key learnings on the factors that modulate LTS solder joint reliability for various components during SMT process.

In current industrial electronics manufacturing, miniaturized devices and a variety of different device package shapes on one printed circuit board (PCB) are a particular challenge. In this paper, the highly miniaturized 01005 and Land Grid Array (LGA) devices are investigated in a mix on a PCB. Both parts have their own challenges in the manufacturing process, which were examined as a combination in this paper. The aim was to find an optimal production process design in order to produce high quality solder joints for all components. Another special feature is that the manufacturing process was investigated on a specially designed demonstrator under practical conditions on a surface-mounting technology (SMT) production line of the company Cicor RHe Microsystems GmbH. From the theoretical influencing factors, the influencing factors with the greatest significance within a practical manufacturing process were specifically selected. Using the demonstrator PCB and an experimental matrix, the most stable process parameters for the 01005 components and LGAs were found. The results show that solder paste with a larger grain size type 4 is suitable for LGAs. In contrast, for 01005 components, grain size type 5 is the optimum choice in the stencil printing process. For the component mix, a compromise has to be found in the process design to handle the miniaturized 01005 package and the LGAs. This compromise has been successfully demonstrated in this paper. This provides a stable manufacturing process for assemblies with 01005 components and LGAs.

The current state of quantum device maturity proposes the use of removable, reusable interconnection means between such device and their classical microelectronic measurement system. One such means is a land grid array (LGA) socket, used pervasively in microelectronics but relatively untested at cryogenic temperatures necessary for most quantum technologies. This article investigates two distinct commercially available LGA socket technologies with respect to contact resistance performance under cryogenic temperature measurement conditions. Test methodologies were successfully developed for both sockets, demonstrating predictable and repeatable contact resistance values during multiple excursions down to 1.5 K and a single excursion to 10 mK. The experimental data show that contact resistance of individual interconnection sites decreased from 30 to 40 $\text{m}\Omega $ at room temperature to 14-17 $\text{m}\Omega $ at 1.5 K and to 6–8 $\text{m}\Omega $ at 10 mK, thus supporting their reliable use in cryogenic measurement applications. Theoretical calculations based on the construction of the microspring socket validated that measured values behaved in a manner that was consistent with temperature-dependent changes in resistivity of the metals comprising the socket interconnection. Spring deflection allowances compensated for any temperature-driven movement of components within the assembly, thus enabling predictable resistance behavior. Regarding the elastomer socket, the high coefficient of thermal expansion (CTE) of the elastomer bulk material induced large variations in socket compression across the temperature range investigated. Sufficient compression to provide consistent contact resistance values at cryogenic temperatures imposed the need for very high compression at room temperature, which may place into question the longer term integrity of this solution. Nevertheless, a preliminary investigation (five cryogenic cycles and subsequent construction analysis) did not reveal any degradation in either socket type.

A comprehensive signal integrity model to hardware correlation study on an improved, 44 Gb/s capable, hybrid land grid array (HLGA) socket connector design is presented. The connector only design SI performance is shown through 3D electromagnetic (EM) modelling. Details of the test vehicle designed to carry out the connector hardware evaluation are shown. Simulation modelling and experimental results of the test vehicle inclusive of the connector are presented and compared. The systematic testing ensures that the new component performs up to its required specifications which ensures successful operation at the system level.

VTT's well-proven $3\ \mu \mathrm{m}$ SOI (Silicon Over Insulator) photonic integration platform is particularly suitable for passive optical functionalities such as Multiplexers, De-Multiplexers, Power Splitters, Delay Lines, Mach-Zehnder Interferometers (MZI), also for active operations such as phase tuning through Thermo-optic Switches and optical power monitoring or high-speed detection with integrated Ge Photo-Detectors (Ge-PD) etc. In combination with integrated up-reflecting mirrors and solder coated cavities it's enabling heterogeneous integration of III-V active devices; both Wafer Level Packaging (WLP) and E/O Wafer Level Tests can be fully exploited, scaling up in volume manufacturing while dramatically reducing assembly costs. Here heterogeneous integration of 40 Vertical Cavity Surface Emitting Lasers (VCSELs) and a SOI 40:1 multiplexer Photonic Integrated Circuit (PIC) is exploited with flip-chip techniques, coupling VCSEL emitting spots on top of respective up-reflective mirrors. VCSELs can be directly modulated up to 50 Gb/s reaching a 2 T/ls full transmission capacity. Additional 40 linear VCSEL drivers are flip-chip bonded onto a suitable Land Grid Array (LGA) interposer designed to provide interconnection and thermal decoupling capabilities to the Si-PIC, realizing a very compact, thermally efficient packaging solution. The exit waveguide from the PIC is also terminated with an up-reflective mirror and furthermore coupled with a 90 deg. tilting fiber optic pigtail designed to minimize the form-factor impact, improving mechanical reliability of the overall transmitter module.

This paper presents a feasible and efficient implementation of a miniaturized X-band transceiver front-end in a cost-effective system-in-package (SiP) technology. Integrating multiple radio-frequency (RF) GaAs / GaN dies with land grid array (LGA) packages is one of the most commonly used solutions in wireless application. Meanwhile, incorporating the RF power devices with quad flat no-lead (QFN) package is a promising substitute due to good thermal conductivity, which utilizes a large die pad in the center which directly transfers the heat from the GaAs / GaN dies from the package to the outside. In this work, an integrated X-band transceiver is designed and implemented with the LGA and QFN technology, respectively. Subsequently, an overall system-level performance investigation and comparison has been analyzed and illustrated. Moreover, the detailed thermal-electrical / thermal-mechanical analysis and comparison are presented in this paper. According to the simulation results, the proposed SiP layout achieves good power performance and reliability with acceptable costs. Finally, the 8-12GHz transceiver is respectively implemented in a QFN and LGA technology, achieving a similar performance and specification. The total package size of the X-band transceiver is slightly different, which is 9*12 mm2 (QFN) and 11*14 mm2 (LGA).

Ball Grid Array (BGA) package designs are increasingly used in surface mount applications while Land Grid Array (LGA) designs are predominantly used in socketing. The need to converge to a single package design has been driving the need to enable socketable BGAs. BGA spheres with a noble metal surface provide a stable mechanical contact interface with the socket paddles. These noble contact interfaces, however, have to remain intact through the socketing life of the product, considering accelerated testing temperatures of 100-120 °C. Under such conditions, it has been reported that the solder from the ball-attach joints undergoes solid-state wicking along the surface of the ball, leading to complete Au dissolution and potential undesirable intermetallic formation with the socket paddles, along with a drop in ball shear strength due to depletion of the solder from the joints. This paper discusses the use of polymer collars to address this challenge and improve the thermal aging reliability of packages with surface-modified BGA interconnections. The polymer collars were spin-coated on the package, which was aged alongside a reference package with no collars, at accelerated test temperatures of 100 °C and 120 °C, respectively. XPS studies showed that after 650 h of aging, no Au signal but a strong Sn signal was observed in the package without collars, which confirmed complete solder wicking to the top of the ball, while the Au signal remained for the package with the collars, confirming that polymer collars are effective in inhibiting solid-state solder wicking from the ball-attach joints. The joints with polymer collars also showed mechanical stability throughout thermal aging with a 3X improvement in joint shear strength.

Flip Chip Land Grid Array (FcLGA) packages are widely used in Mobile product applications due to their thin form factor and performance. Assembly process qualification requires careful selection of materials and optimization of reflow processes to make consistent and reliable product. The fcLGA typically uses an organic substrate on which the die is reflowed instead of the copper lead frame used in QFN packages. This requires assessment of CTE mismatch and controlled reflow processes to prevent bump separation [1]. The paper reviews the selection of substrate, optimization of assembly process and reliability testing conducted for package qualification

Advanced RF packages are demonstrate with active (low-noise amplifier, RF switch) and passive integration in ultra-thin 3D glass packages with miniaturization and enhanced performance. The novelty of this RF packages is three-fold: 1) Ultra-thin 100 μm glass, 2) Double-side thinfilm RF circuits interconnected with Through-Package Vias (TPVs), and 3) Direct assembly of the glass-core package to the board with Land Grid Array (LGA) connections. An innovative double-via process, starting from prefabricated vias in bare glass, polymer filling and via drilling, is utilized for a robust and high-yield substrate fabrication process. Scalable and low-cost panel laminate processes are utilized to form the RF circuits on the build-up layers. The performance benefits are demonstrated through interconnect loss, impedance match, electrical gain and noise figure measurements. Compared to existing RF substrates, the glass substrates show 2.5X miniaturization in substrate thickness with extensibility to thinner substrates.

Land grid array (LGA) sockets are commonly used for industry standard and custom microprocessors to meet the increased performance challenges for a variety of server applications. Along with the need for increased high speed signaling capabilities comes the challenge to support lower voltages and higher currents. Typical testing that is conducted by the LGA socket suppliers does not provide an accurate assessment of the maximum current capabilities in a real product application due to the test card design and construction limitations. Typical test card designs use daisy chain connections to wire multiple LGA socket contacts in series. The daisy chain wiring in the test card adds to the resistive heating and results in an inaccurate maximum current rating. Also, the test cards typically do not have a cross section construction that is representative of a real product application with multiple ground planes that provide improved thermal dissipation of the heat generated by the LGA socket interface. Hardware testing was conducted to better understand the performance limitations for a new product application. The test card was designed to use multiple voltage and ground planes in the circuit card cross section to provide a low impedance path for current flow and a low voltage drop through the LGA socket interface. In addition to the test card construction, the test hardware included a special test module with a shorted chip to provide a more accurate power distribution path through the socket and processor package. The test variables included different plating metallurgy options for the LGA socket and the processor module along with different configurations for the voltage supply and ground return contacts. Electrical and thermal modeling techniques were used to simulate the test hardware configuration with good correlation between the hardware and modeling results. Based on the positive correlation results, additional modeling was conducted to simulate the worst case power mapping conditions for the processor chip along with a more accurate power distribution. The additional modeling results provided further insights into the maximum current capabilities for the LGA socket based on the temperature increase from the resistive heating in the socket contacts.

Purpose Solder paste printing is the most common method for attaching surface mount devices to printed circuit boards (PCB), and it has been reported that a majority of all assembly defects occur during the stencil printing process. It is also recognized that the solder paste printing process is wholly responsible for the solder joint formation of leadless package technologies such as land grid array (LGA) and quad-flat no-lead (QFN) components and therefore is a determining factor in the long-term reliability of said devices. The aim of this experiment is to determine the acceptable lower limit for solder paste volume deposit tolerances during stencil printing process to ensure both good assembly yield and reliability expectations. Design/methodology/approach Stencils with modified aperture dimensions at particular locations for LGA and QFN package footprints were designed to vary the solder paste volume deposited during the stencil printing process. Solder paste volumes were measured using solder paste inspection system. Low volume solder paste deposits were generated using the modified stencil designs to evaluate assemble yield. Accelerated thermal cycling (ATC) was used to determine the reliability of the solder joints. Failure analysis was used to determine if the failure was attributed to the low paste volume locations. Findings Solder joints formed with nominal paste volume survived longer in ATC compared to intentionally low volume joints. Transfer efficiency numbers for both good assembly yield and good reliability are reported for LGA and QFN devices. A lower volume limit is reported for leadless devices that should not significantly affect yield and reliability in thermal cycling. Originality/value Very little literature is available on solder paste volume tolerance limits in terms of assembly yield and reliability. Manufacturers often use ±50 or ±30 per cent of stencil aperture volume with no evidence of its effectiveness in determining yield and reliability of the solder joints.

Charge Device Model (CDM) events contribute to most of the Electrostatic Discharge (ESD) failures of semiconductor devices in the field. One of the major components of a CDM tester is a grounded pogo pin/probe which is used to create a discharge path for the charged device. There are many device packages in the market, however, this paper will focus on the most common flip chip packages types in the industry - Ball Grid Array (BGA), Pin Grid Array (PGA) and Land Grid Array (LGA). Three pogo probe types will be used and are described in detail in the paper. This study recommends the best fit pogo probe tip type for each package type based on the magnitude and standard deviation of the discharge current. The results and statistical methods can be useful for all Reliability engineers in helping them to choose the most appropriate pogo probe type for the various packages. Choosing the right pin can increase the robustness and quality of CDM testing.

Sensor developments involving semiconductors techniques are even more becoming a typical vehicle for high-level of integration and in many cases are constituting a solid base for a dedicated category of Micro Electro Mechanical Systems (MEMS).In the present paper the package structure along with the System in Package (SIP) assembly details for an optical MEMS sensor are shown. An infrared sensitive structure is involved, based on semiconductor technology. The contribution of the package presence around the sensor chip and the physical interactions with sensor constitutes one of the key aspects for the overall system performance and these physical aspects are focused in the present paper. The package structure is a cavity Land Grid Array (LGA). Structural and physical characteristics of the involved materials points to match the optical signal handling as well as the electrical signal processing as output of the integrated Application-Specific Integrated Circuit (ASIC) controller.A dedicated organic substrate design, a molded-cavity structure and a Si-based IR filtering window constitutes the main features of the sensor system, in terms of concept and design boundary. Measured sensor performance and opto-electrical characterizations are finally reported, including IR opto-geometrical considerations as FFOV (Full Field Of View) results for two different package versions.

Technology development for Internet of Things applications is growing astronomically, increasing the demand for smaller, faster, and lower power solutions to run and power a vast array of connected machines and objects. The LS1012A is the smallest 64-bit processor on the market today, with a novel 211 LGA package that creates a mechanically robust and space efficient component. However, excellent board level reliability is required in order to meet the various IoT application needs. This study evaluates the board level reliability of the 211 LGA by performing single chamber thermomechanical cycling, monotonic bend testing, and JEDEC drop testing. The objective of this study is to fully optimize the board level performance of the 211 LGA without dramatically altering the package design. Two significant board level changes were applied to achieve significant board level performance, exceeding all projected application uses.

This paper examines methods to electromagnetically model a hybrid land grid array (HLGA) connector and its associated printed circuit board (PCB) via individually with the goal of achieving the best correlation between their cascade and when modelled together as a single structure. The transition between the connector and the PCB via is of utmost importance as this is the location where the segmentation takes place. In this activity, the segmentation takes place on or close by the solder ball transitioning a signal between the two components. The solder ball location and any associated pads and/or dog-bone traces are becoming more worthy of attention as signal rise times decrease and data rates increase. Different excitation port setup techniques are considered at the transition. The signal integrity (SI) metrics of the cascaded models generated from each method tested are compared against a reference merged model. Due to differences observed between the cascaded and the merged models for one of the conventional modelling methods, a modelling correction method is investigated to achieve a closer match between cascaded and merged models.

Navigating the trade-offs between performance, size, cost and reliability can be a challenge when considering integrated circuit (IC) packaging and the end-application. The integration of micro-electromechanical systems (MEMS), either monolithic or heterogeneous, introduces yet another level of complexity that has only recently been a major focus of multi-device packaging [1]. Wafer-level fan-out (WLFO) technology can enable improvements in several areas, primarily the reduction in size of parasitic interconnects and, proportionally, a drastic decrease in overall form-factor as compared to more ubiquitous chip-scale packaging solutions. Widespread adoption of WLFO packaging [2] has driven implementation costs to a level competitive with traditional fan-in wafer-level packaging. This study quantifies the benefits of WLFO versus flip-chip land grid array (FCLGA) packaging for a radio frequency (RF) MEMS digital tunable capacitor array integrated with 180nm CMOS technology. RF performance hinges critically upon the ability of the package to transfer signals with minimal impedance, necessitating shortened redistribution layer (RDL) paths and reduced, or removed, solder interconnects. Flip-chip packaging requires a multi-layered substrate and an intermediate solder interconnect while chip-first WLFO packaging makes use of direct Cu RDL bond to die pads and a single-level of routing to the ball grid array. Die size in both cases is 1.8x2.2x0.3mm, which enables a direct comparison of form-factor between the two package types. Manufacturability is addressed in this study; a primary challenge of monolithically integrated MEMS/CMOS is the ability to survive typical IC packaging processes wherein thermal, mechanical and electrical overstress may occur. Daisy chain packaged parts were subjected to board-level mechanical shock. Functional packaged parts were subjected to component-level reliability stresses. RF characterization of functional packaged parts was conducted on printed circuit boards (PCB); the primary figure of merit being self-resonance frequency (SRF) as a result of overall parasitic losses.

A high power density inverter is one of the most important design requirements for a compact and energy-efficient integrated motor drive (IMD) design. Agallium nitride (GaN) high electron mobility transistor (HEMT) has a lateral device structure with land grid array (LGA) or ball grid array (BGA) package for minimum parasitic inductance and resistance, which is also advantageous in a thermal management. This paper presents a new thermal management methodology for a high power density IMD using GaN HEMTs. An optimized printed circuit board (PCB) design is investigated for an effective bottom-side cooling method without any heatsink. The parasitic components are also analytically estimated to prove the validity of the proposed circuit design.

Biometric features, such as fingerprint, facial recognition, etc, are convenient personal identification methods in mobile electronics. Fingerprint recognition is one of mature technologies and is embedded in an increasing number of mobile devices. For fingerprint sensor packaging, wire bonding and over-molding Land Grid Array (LGA) is one of major package types. Inside the wire bond LGA package, the dielectric constant (Dk) of over-molding compounds is one dominant factor for the sensitivity of capacitive fingerprint sensors. Normal molding compounds contain epoxy base polymers and silica base fillers. Their Dk value is relative low (3~5 at 1 MHz). Those compounds are suitable for the general encapsulation purpose. But they have shielding effects on the sensing signal transmission in capacitive fingerprint sensor packages. This shielding effect needs to be reduced as much as possible, especially when thick glass is used on fingerprint module for the mechanical protection. Therefore, high Dk (7~40 at 1 MHz) molding compounds were developed for the sensor performance enhancement. High Dk property of molding compound can be achieved by using new type polymers and metal oxide fillers. With new type polymers and fillers, the major challenges of high Dk molding compounds come from the warpage and stress during the package assembly process. In order to diminish the warpage and stress, lots of experiments were conducted which including molding compound composition adjustment, post-mold cure process optimization and so on. In this paper, several types of high dielectric constant molding compounds were evaluated and compared. Stress simulations were performed to determine the package construction. Screen and corner DoEs of molding process parameters were conducted to come out the process window. Functional test and reliability test have been preformed as well. Two types of high Dk molding compounds have proven to be feasible and reliable materials for enhancing the performance of fingerprint sensors.

Gallium nitride (GaN) high electron mobility transistor (HEMT) has a lateral device structure with a land grid array (LGA) or ball grid array (BGA) device package, which is beneficial in minimizing parasitic parameters as well as the overall device size. These types of packages in conjunction with the lateral device structure possess better thermal performance as compared to the conventional silicon MOSFETs. When a printed circuit board layout is properly designed, the copper traces and pours in the vicinity of the switching devices can serve as effective heat dissipation channels. In this paper, an integrated planar inductor is designed and analyzed to achieve both zero-voltage switching and high thermal performance in a high frequency synchronous buck converter. The conduction losses in the planar inductor can be significantly reduced using multilayer PCB and heavy copper trace.

Area Array microelectronic package with small pitch and large I/O counts is now widely used in the ceramic packaging of microelectronics Integrated Circuit (IC). This kind of Land Grid Array (LGA) device cannot be directly soldered on Printed Circuit Board (PCB). In order to mount them on PCB the LGA device back end is mostly terminated with solder columns (CGA device) or with solder balls (BGA device). For space application CGA and BGA ceramic devices are prone to early failure due to harsh environment. Indeed vibration and shock during launch as well as thermal cycling in orbit induces a high level of stress in the solder joints between board and device. Such high level of stress can ultimately cause the failure of one of the solder joints causing permanent functional electrical failure. As the trend for next generation of ceramic IC device is to increase their sizes and their density of I/O, susceptibility to mechanical and thermal loading grows even more. This statement is in contradiction with the high level of reliability required for space application. To overcome this situation CNES has taken the lead with space users and space connector manufacturers to develop for space application a reliable solderless solution that will enable to easily mount on board the actual and the next generation of ceramic IC package. This solderless solution consists in using a thin connector interposer between the ceramic LGA device and the board. A clamping system is used to hold and keep aligned on the board the stacking composed of the ceramic device and the interposer connector. This solderless solution has been evaluated according to the European space standard and has demonstrated a high robustness to harsh environment making this solution compliant for space application.

This paper presents an improved hybrid land grid array socket connector design enabling high speed bus signaling data rates up to 50Gb/s. Observed limitations in an existing connector such as impedance mismatches and crosstalk are treated and improved. The improved connector structural differences from the existing connector are presented and motivated. Electromagnetic modelling for the improved and existing connectors has been carried out to validate the design concept and compare signal integrity properties.

LGA(Land Grid Array), also referred as pad array package, similar to BGA, but has no solder ball at the bottom of the body. Standards in the field of domestic military, such as QJ3011 and Q/QJA20080-2012, just claim that there should be appropriate distance between the device body and the Printed Circuit Board(PCB) to release heat mismatch, and have no specific instructive soldering process methods and parameters in detail. In this paper, we set LTM8033V device with LGA package from LINEAR company as an example to provide a practical process for its assembly. Specifically, we raise the LGA device to some appropriate height by planting solder ball on the bottom pad of LGA device. The experience of our experiment shows that, special pretreatment must be performed before ball planting. Then, the whole process involves: Cleaning, Pre-dry, Planting balls, Reflow and Inspect. In addition, we analyze the stress and strain changes of the solder joints under thermal cycling condition, and predict the life of solder joints by Finite Element Simulation method. The result shows that it is workable by planting balls onto the bottom pad of LGA device to match the industry standard and achieve high reliability solder joint.

This paper presents the reliability of a plastic land grid array (LGA) with 1156 pads, 1.0-mm pitch, and the reliability of a flip-chip ball grid array (FCBGA) with 1924 balls, 1-mm pitch, assembled with tin-lead solder onto printed circuit boards (PCBs). Surface finishes for PCBs were electroless nickel electroless palladium immersion gold (ENEPIG) and tin-lead hot air solder level (HASL). The LGA assemblies were first subjected to 200 thermal cycles (−55°C to 125°C) and then to 324 hours of aging at +125°C. The FCBGA assemblies were subjected to 200 thermal shock cycles (TS) in the range of −65°C to +150°C. Test results presented include daisy-chain resistances, SEM/X-section images, and dye and pry destructive failure analyses for HASL and ENEPIG surface finishes.

In this article we present the conception, technological fabrication and electrical characterization of 3D hybrid pixel detector modules based on read out chips (ROCs) with through silicon vias (TSVs) which are flip chip bonded onto silicon photon sensors for X-ray detection. The TSVs in the ROCs enable a vertical routing of their peripheral IOs to the back side where they are spread to a land grind array (LGA) with 800 µm pitch. Thus, the back side of the ROCs can be used for next level interconnection to LTCC system boards which allows a pure vertical system architecture. With this routing concept, area-consuming wire bond connections from the peripheral IOs of the ROCs to the system board can be avoided which is the base for edgeless detector configurations with a tiled assembly of ROCs without imaging dead zones. To enable the envisioned vertical system concept, the ROCs were post-processed with 100 µm deep copper filled TSVs, front and back side redistribution, micro solder bumps for connection to the detector and land grid array (LGA) for connection to the system board. The UFXC32k (Ultra Fast X-ray Chip with 32k channels) served as ROC device featuring an array of 32768 pixel IOs using a pitch of 75 mm, 87 peripheral chip IOs and a total size of 2 cm2. The sensor tiles were post-processed with copper pads to enable a side by side flip chip assembly of two ROCs onto each sensor. The LGAs on the back side of the ROCs were used to mount the sub-modules to the LTCC system boards, which were pre-assembled with SMDs and corresponding solder ball arrays. The fabricated 3D hybrid pixel modules show a good electrical performance and passed real X-ray imaging experiments. A high interconnect yield was achieved with only maximum 17 dead pixels out of 65536 total pixels per detector. These investigations took place in a joint project between Fraunhofer IZM in Berlin and AGH University of Science and Technology in Krakow.

As the demand for higher resolution electronic device grows, manufacturers are seeking ways to put as much as possible pixels with using less and less space. Compare with land grid array (LGA) type packaging, WLCSP technology provide a way to shrink the package size. ShellCase WLCSP is one of the types with good reliability and small packaging size used in image sensor. But the double side glass structure might have reliability problem while building with large die size. Means the number of pixel will be constrained by chip size. A new optical packaging patent for CMOS image sensors is discussed in this paper. This package is a chip on glass fan-out structure. Compare with ShellCase Wafer Level Chip Scale Packaging (WLCSP) the glass on print circuit board (PCB) side is removed. Therefore, larger die size can be used in this packaging. In this paper, the thermal cycling test (TCT) reliability for fan-out packaging is discussed through finite element method (FEM).

Recent high-end server design trends have continued to challenge electronic packaging engineers to design and integrate larger form factor land grid array (LGA) attached modules within their assemblies. These trends have included the application of larger, denser, organic packaged modules whose electrical performance and postencapsulation physical characteristics have been enabled by both the continued development of hybrid LGA connectors as well as new module actuation hardware designs. In this paper, we'll discuss these recent trends, including the specific technical attributes and challenges that need to be addressed to ensure a repeatable and reliable assembly design is developed. Initially, overviews of the latest connector and module design trends, including styles and physical sizes and their implications to the module's bottom surface metallurgy (BSM) flatness requirements, etc. are provided. Pursuant to this, recent system integration trending is reviewed; including both the module quantity per system assembly as well as module to module physical placements and how each of these impact printed wiring board (PWB) design (i.e., layer count, LGA site flatness, etc.) as well as the PWB assembly's solder processing characteristics (i.e., LGA pre- and post-solder attach contact co-planarity, etc.). Completing the application portion, is a description of some recent LGA actuation hardware and module external cooling apparatus designs (e.g., air-cooled heats sinks and water-cooling cold-plates and thermal interface materials (TIMs), etc.). The remaining portion of the paper is dedicated to the description of the mechanical analysis efforts completed to provide a fundamental understanding of the design's “as-assembled” attributes and a review of the associated evaluation completed to verify the integrated assembly's reliability characteristics. From the analysis methodology perspective, both the means of including each of the integrated assembly's key attributes (e.g., module mechanical construction and as encapsulated flatness, LGA contact compliance and stiffness as well as soldered contact coplanarity, TIM stiffness, actuation hardware, heat sink and cold-plate mechanical construction, etc.) and the resulting estimation of the predicted module internal TIM and hybrid-LGA's Pb-free soldered interface strains, actuation hardware stresses and LGA contact load variation are provided. Completing the discussion is a review of the variety of testing executed to validate the design's intended reliability. Included in this is a description of the test vehicle's design, the environmental stress testing conducted (i.e., mechanical pre-conditioning, accelerated thermal cycling (ATC), mixed flowing gas (MFG) and heat aging (HA), etc.) and the resulting data.

A laser ultrasound and interferometer inspection system has been successfully applied to detect solder bump defects, including missing, misaligned, open, and cracked solder bumps in flip chips, land grid array packages and chip capacitors. This system uses a pulsed Nd:YAG laser to induce ultrasound in the chip packages in the thermoelastic regime; it then measures the transient out-of-plane displacement response on the package surface using a laser interferometer. The amplitudes of the out-of-plane displacement responses are usually in the order of nanometer. The quality of solder bumps is evaluated by analyzing the transient responses. In this paper, this system is used to evaluate the quality of lead-free solder bumps in ball grid array (BGA) packages; specifically, BGA packages with poor wetted solder bumps are used as test vehicles. Poor wetting not only decreases the mechanical strength of interconnection at the interface between the solder bumps and substrate, but also deteriorates electrical and thermal performance because of the unreliable connections between the package and the printed circuit board (PCB). Causes of poor wetting vary from the solder materials themselves to the manufacturing process. Here, poor wetting of solder bumps were intentionally created by using an improper reflow profile. The transient out-of-plane displacement signal responses from these packages are compared to a hybrid reference signal generated by signal responses from defect-free samples. Packages with poor wetted solder bumps are distinguished from the normal packages by using the correlation coefficient signal analysis method. Then, laser ultrasound inspection results are also compared with results from continuity test, X-ray inspection and scanning acoustic microscope (SAM). Finally, the cross-section images are further used to confirm the existence of the poor wetting in samples with unusual correlation coefficient. It can be concluded that this laser-ultrasound system is capable of identifying the presence of poor wetting in BGA packages.

As high performance computing (HPC) system performance requirements increase, it is necessary to investigate new methods for integrating system components. Of interest is the applicability of 3D packaging approaches to HPC systems. Using thermal test chips, we designed and assembled a 3D processor-memory module with an integrated power delivery network to investigate interconnect density, integration, testability, and rework issues with 3D integrated packaging in an HPC environment. The design was based on interconnection and power delivery requirements for a processor-memory module capable of supporting 64 full-duplex 30G SerDes, routing for 800 processor-to-memory pins, an integrated multi-tiered power delivery network, and a thermal management solution capable of dissipating a nominal processor heat flux of 100 W/cm2. The technologies selected—semi-rigid flex, power connectors, land grid array (LGA) attach with an anisotropic film, and cold plate-based cooling—are all commercially available technologies, which we adapted for this HPC module. As more advanced 3D packaging and integrated circuits become available, these assemblies and components can be incorporated into our approach to increase integration and performance. This design approach also accommodates substitution of thermal test chips in place of functional components, allowing validation of thermal management solutions ahead of the final module design. We will present the electrical-to-mechanical design strategy used to build this module and results of the thermal and electrical analyses, and point to several areas where further development work would be beneficial in the areas of interconnect, power delivery, and mechanical design.

More and more Land Grid Array (LGA) components are being used in electronic devices such as smartphones, tablets and computers. In order to enhance LGA mechanical strength and reliability, capillary flow underfill is used to improve reliability. However, due to the small gap, it is difficult for capillary underfill to flow into the LGA at SMT level. Due to cost considerations, there are usually no pre-heating underfill or cleaning flux residue processes at the SMT assembly line. YINCAE solder joint encapsulant SMT 256 has been successfully used with solder paste for LGA assembly. Solder joint encapsulant is used in in-line LGA soldering process with enhanced reliability. It eliminates the underfilling process and provides excellent reworkability. The shear strength of solder joint is stronger than that of underfilled components. The thermal cycling performance using solder joint encapsulant is much better than that using underfill. Bottom IC of POP has been studied for further understanding of LGA assembly process parameters. All details such as assembly process, drop test and thermal cycling test will be discussed in the full paper.

Package surface coating technology has been around for years. It can be used to protect assembly product from the interference of electromagnetic wave. The industry generally uses PVD sputter method to complete the package surface coating process. So far, the surface coating for land grid array (LGA) has been mass produce by many different suppliers. But, ball grid array (BGA) product with PVD sputter process still faces a lot of issue with process control. The main bottleneck for BGA surface coating with sputter process is the high temperature (>250oC) generated by ion collision during PVD process and back side deposition (BSD) defect. When the temperature is greater than the melting point of solder balls (217oC), the solder ball will melt and lead function fail. But PVD sputter require high vacuum environment to keep processing stable. Back side deposition is another main problem for package surface coating, because BSD will cause pin short to happen. Therefore, a method of lowering the temperature during PVD sputter process and avoiding BSD is the key point for BGA surface coating technology. For the temperature issue, the most viable way to transfer heat in high vacuum deposition chamber is by contact. But it is hard to find a suitable material which can endure high temperature (>250oC) without gas releasing during process and not affect the product. So far, several different kind of silicone type material such as PI base silicone tape or silicone glue and silicone film have been tested to produce BGA product with surface coating layer. As result shows, silicone can help transfer heat from BGA into metal carrier to lower the temperature. To achieve lowering of temperature, alumina is chosen as the main metal to produce the carrier due to its high heat capacity. Silicone can also protect the substrate from back side deposition by sealing the PKG edge of backside with the silicone material. To sum up, we can lower the process temperature from 280°C to less than 160°C by using silicone to transfer heat from the package to metal carrier.

Electrical contacts provide means for a separable connection between two current carrying conductors. Sockets containing these contacts could be exposed to mechanical vibration due to shipping, which can result in micromotion between mating surfaces. Repeated micromotion/fretting could lead to wearout of the protective gold layer and expose the base metal that can oxidize. Traditional laboratory based fretting experiments may not reflect the field reliability risks. In this study, a predictive capability is developed to investigate contact fretting in a socket due to random vibration using a finite element approach. Considering the degrees of freedom involved in the analysis and the resolution needed, a multiscale modeling approach utilizing global models with substructures to track high risk areas and local models to monitor fretting wear on the highest risk contact is employed. This approach allowed the study of micromotion at the contact interface, capturing stick-slip phenomenon, which can influence fretting wear. Predictions are validated through extensive experimentation, which includes matching of fretting risk areas, matching dynamic responses, and matching of fretting wipe lengths and location through image processing techniques.

Recent industry trends to continue enabling increased server system performance and packaging density has driven the need to implement larger form factor hybrid land grid array (LGA) attached organic modules. In addition, given the need to package multiple modules on a single printed circuit board (PCB) assembly, PCB cross-sections and their corresponding physical properties (e.g., flatness, etc.) as well as module bottom surface metallurgy (BSM) co-planarity require a more detailed understanding of impacts to the compliant as well as the soldered connector interfaces. Lastly, the migration to lead (Pb)-free solders has further complicated the issue given both the change in material properties as well as processing temperatures. In this paper we will discuss the mechanical stress analysis and evaluation tests assessment of a recently developed 50 mm square organic processor module, hybrid LGA attached to a multiple site PCB. The analysis presented will highlight the methodology to identify both connector soldered stress and predicted contact load variation across the module's mated interface. Key parameters discuss will include the PCB flatness, Organic substrate BSM co-planarity (both predicted and measured) and the Hybrid LGA as-soldered contact co-planarity. Corroborating predicted analytical results, we will discuss various evaluation tests performed to validate the design's integrity. Key tests include, pressure sensitive film (PSF) studies and environment stress exposures, including thermal shock, mechanical shock and vibration and seismic exposure. Post test electrical integrity and test sample construction analysis, including 3D x-ray and mechanical cross-section, will also be described. The analysis process and testing described will provide a method to evaluate more challenging hybrid LGA applications as both module sizes and/or number applied per PCB assembly increase and Pb-free assembly is introduced in future applications.

High strain-rate drop impact tests were performed for land grid array (LGA) packages with (electroless nickel immersion gold) ENIG metallization and lead-free solder interconnects. Sn-4Ag-0.5Cu (in wt%, SAC405), Sn-3.5Ag (in wt%), and Sn-0.7Cu (in wt%) were used for pretinning the LGA pads. SAC 405 alloy was used for the LGA-to-board mounting. Drop test results showed two distinct trends. Samples pretinned with Sn-4Ag-0.5Cu and Sn-3.5Ag showed poor drop performance while those pretinned with Sn-0.7Cu (in wt%) or without pretinning showed excellent drop performance. The dierence in behavior is related to the initial intermetallic morphology and structure. The needle shape Ni3Sn4-based intermetallics were observed for the first two cases. This led to poor adhesion between solder and NiP metallization. The samples with Sn-0.7Cu pretinning and no pretinning showed a continuous intermetallic morphology. In this case, sucient Cu improved the solder wetting and formed a continuous intermetallic morphology, leading to better drop performance. A sucient amount of Cu makes the better wetting, forming (Cu,Ni)

PurposeThe purpose of this paper is to describe the effect of indium alloying on the thermal fatigue endurance of Sn3.8Ag0.7Cu solder in low‐temperature co‐fired ceramic (LTCC) modules with land grid array (LGA) joints and the feasibility of using a recalibrated Engelmaier model to predict the lifetime of LGA joints as determined with a test assembly.Design/methodology/approachTest assemblies were fabricated and exposed to a temperature cycling test over a temperature range of −40‐125°C. Organic printed wiring board (PWB) material with a low coefficient of thermal expansion was used to reduce the global thermal mismatch of the assembly. The characteristic lifetime, θ, of the test assemblies was determined using direct current resistance measurements. The metallurgy and failure mechanisms of the interconnections were verified using scanning acoustic microscopy, an optical microscope with polarized light, and scanning electron microscopy/energy dispersive spectrometry (SEM/EDS) investigations. Lifetime predictions of the test assemblies were calculated using the recalibrated Engelmaier model.FindingsThis work showed that indium alloying increased the characteristic lifetime of LGA joints by 15 percent compared with Sn3.8Ag0.7Cu joints. SEM/EDS analysis showed that alloying changed the composition, size, and distribution of intermetallic compounds within the solder matrix. It was also observed that a solid‐state phase transformation (Cu,Ni)6Sn5(→ (Ni,Cu)3Sn4 occurred at the Ni/(Cu,Ni)6Sn5 interface. Moreover, the results pointed out that individual recalibration curves for ceramic package/PWB assemblies with high (≥ 10 ppm/°C) and low (≈ 3‐4 ppm/°C) global thermal mismatches and different package thicknesses should be determined before the lifetime of LGA‐type assemblies can be predicted accurately using the recalibrated Engelmaier model.Originality/valueThe results proved that indium alloying of LGA joints can be done using In‐containing solder on pre‐tinned pads of an LTCC module, despite the different liquidus temperatures of the In‐containing and Sn3.8Ag0.7Cu solders. The characteristic metallurgical features and enhanced thermal fatigue endurance of the In‐alloyed SnAgCu joints were also determined. Finally, this work demonstrated the problems that exist in predicting the lifetime of ceramic packages with LGA joints using analytical modeling, and proposals for developing the recalibrated Engelmaier model to achieve more accurate results with different ceramic packages/PWB assemblies are given.

Purpose The purpose of this paper is to investigate the feasibility of using land grid array (LGA) solder joints as a second-level interconnection option in low-temperature co-fired ceramic (LTCC)/printed wiring board (PWB) assemblies for telecommunication applications. The characteristic behaviour of two commercial lead-free solder materials (Sn4Ag0.5Cu and Sn3Ag0.5Cu0.5In0.05Ni) in reflow processes and thermal cycling tests are also evaluated. Design/methodology/approach The effect of the reflow temperature profile on voiding in two lead-free solders in LTCC/PWB assemblies was investigated using X-ray and scanning electron microscopy (SEM) investigations. The test assemblies were fabricated and exposed to a temperature cycling test (TCT) in a 0-100°C or −40 to 125°C temperature range. Organic PWB material with a low coefficient of thermal expansion (CTE) was primarily used. In addition, to compare LGA assemblies with low and high global thermal mismatches, an LTCC module/FR-4 assembly was also fabricated and exposed to a TCT in a 0-100°C temperature range. The characteristic lifetime of the test assemblies was determined using DC resistance measurements. The failure mechanisms of the interconnections were verified using scanning acoustic microscopy, SEM and finite element (FE)-SEM investigations. Findings This work showed that the solderability of AgPt-metallized LTCC modules was poor, resulting in excessive voiding. This problem was avoided by using pre-tinned modules. In the test assemblies, the Sn4Ag0.5Cu joints had a lower void content and a higher characteristic lifetime compared with the Sn3Ag0.5Cu0.5In0.05Ni joints. Furthermore, it was observed that the Sn3Ag0.5Cu0.5In0.05Ni joints were more prone to fail along the interface between the Ag3Sn layer and the solder matrix than were the Sn4Ag0.5Cu joints. It was assumed that the observed difference in the primary failure mechanisms resulted in the decreased lifetime duration of the SnAgCu-InNi/Arlon in both temperature cycling conditions. Originality/value The results proved that the solderability of both solders in AgPt-metallized modules in a typical surface mount technology process was poor; however, the solderability of the test modules can be notably enhanced with pre-tinned pads. This work also demonstrated the effect of the metallization/solder pair on the failure mechanisms and failure rate in LTCC/PWB assemblies with LGA joints; the work also proved in the TCT, over a temperature range of 0-100°C, that using the present LGA joints in LTCC/PWB assemblies with a high global thermal mismatch did not increase the lifetime duration of the joints to the preferred level (3,000 cycles), whereas the performance of these joints was adequate in assemblies with a low global thermal mismatch. Moreover, the results indicated that using the LGA joint configuration enhanced the reliability of the LTCC/PWB assemblies compared with similar assemblies with collapsible ball grid array solder spheres.

Stress relaxation in stamped metal LGA sockets can result in a loss of normal force and an increase in contact resistance, potentially leading to a failure. This paper describes an approach for determining the risks from stress relaxation in stamped metal LGA sockets by taking into account the effect of Joule heating of the socket contacts. Stress relaxation data were obtained at different temperatures and strain values, representative of both operating and overload conditions. Contact resistance measurements were conducted as the force was varied to determine the minimum force below which stress relaxation is likely to cause failure. Joule heating of the socket contacts was found to cause a measurable rise in temperature with a typical value of ~40°C above the unpowered state of 90°C at the maximum rated current of 3 A for the socket being studied. This temperature rise was determined to be a significant factor in stress relaxation and was found to cause an average reduction in normal force by ~26%. The properties of the polymer housing were found to be sensitive to Joule heating effects and to have a significant influence on the stress relaxation behavior of the socket.

This paper presents the design and fabrication of a stand-alone high directivity coupler using high dielectric constant multilayer organic (MLO) technology. MLO is a low cost high density interconnect technology that allows for the realization of high Q and low loss inductor and capacitor elements that allow for the miniaturization of RF and mixed signal circuits. Q values above 300 have been measured for MLO with costs being lower than both LTCC and TFOS technologies. Low-loss lumped and distributed elements were realized using a novel multilayer build up process that supports both land grid array (LGA) and edge terminations. The couplers which support frequencies between 700 MHz and 2GHz exhibit coupling coefficients above 20db and isolation greater than 40db. The couplers can be combined with low pass harmonic filters in the same technology.

The component-level drop reliability of micro-electronic packages has been a concern. Proper modeling approaches can significantly reduce the time and costs and provide valued data support not only on the failure analysis but also on product development. Based on finite element methods, the presented study performed explicit dynamic drop modeling to simulate the actual drop tests using ANSYS and LS-DYNA. A generic over-molded LGA (land grid array) module was selected and 3D parametric models were utilized to carry out the study. As in the actual drop test, the standard JEDEC test board and JEDEC drop condition were applied. The over-molded modules together with the test board under 1500G gravity was simulated to identify the failure locations. The results were fairly correlated to the actual FA observation. Potential key factors such as solder pad size, pitch size, module size, and thickness were studied through the parametric modeling. The impact of board side defect, such as solder void, was also studied because it is common to have this kind of defect in assembly. Besides component-level drop reliability, we also studied the board-level drop reliability by investigating the LGA solder stress.

Land grid array (LGA) sockets are used as separable interconnects between printed circuit boards, and high I/O integrated circuit components. Because the socket contacts with the component and the circuit board on both sides, low and stable contact resistances among these interfaces are desirable for the reliable electrical connection of the LGA package. This paper compares the contact resistance degradation of two LGA socket designs, silver particles in an elastomer column, and silver-plated-nickel in an elastomer film, subjected to accelerated corrosion environment, or so-called mixed flowing gases (MFG). Increased contact resistance was observed in the sockets due to corrosion products over the contact surface after metal corrosion. Corrosion products were analysed using environmental scanning electron microscopy (E-SEM), energy dispersive spectroscopy (EDS), and x-ray photoelectron spectroscopy (XPS). AgCl, Aga2O, and Ag2SO4 were identified after silver corrosion; NiCl2, Ni2SO4, and MS were found after Ni corrosion. The nickel corrosion product bridged the adjacent contacts as whiskers with time. The lifetime can be estimated by an acceleration factor: two day MFG Battelle Class II exposure equals one year of field service. The shelf life of conductive elastomer LGA sockets is expected to be longer than five years.

The relaxation behavior of an epoxy molding compound (EMC) subjected to a constant strain can cause new reliability challenges in automotive electronics. This problem will be exacerbated due to the ever-increasing demand in modern electronics systems for miniaturization with more functionality, yet it has not been studied extensively to mitigate its effect on reliability. In this study, a piezoresistive silicon-based stress sensor is used to understand the stress state in an electronic control unit (ECU), more specifically the relaxation behavior of EMC caused by the storage time of an ECU (i.e., duration between production and actual usage). Mechanical stresses are measured by the piezoresistive stress sensor that is encapsulated in a standard microelectronic 3 × 3 mm land grid array (LGA) package. The relaxation behavior is observed at three different temperatures for 1 week: 75 °C, 100 °C and 125 °C. The relaxation behavior is measured continuously for one more week after cooling the package to room temperature (at 25 °C). An additional test is conducted at 85 °C with 85% relative humidity to investigate the effect of moisture diffusion on the package. The experimental results clearly indicate that the proposed approach can be used for better understanding of the evolution of stresses in molded packages during their lifetime, especially during storage, which in turn can lead to more optimal designs in the future.

A land grid array (LGA) socket provides high-density, electrically-separable interconnect between a component and a printed circuit board. The LGA socket must not be susceptible to creep and stress relaxation, which can lead to loss of contact force and consequently the degradation of contact resistance. In this paper, the time-dependent contact resistance failure mechanisms were experimentally assessed and theoretically analyzed for silicone elastomer matrix socket interconnects. A time-dependent physics-of-failure model was developed for contact resistance simulation

As handheld electronic products are more prone to being dropped during useful life, package to board interconnect reliability has become a major concern for these products. This has prompted the industry to evaluate the drop performance of CSP packages while mounted on printed wiring boards using board level drop testing. Although a new board level test method has been standardized through JEDEC (JESD22-B 111), characterization tests take quite a long time to complete, extending the design cycle. This paper proposes a method to compare and evaluate the drop performance through simulations at the design stage. A global-local approach is used to first determine the dynamic response of the board during drop and then to translate it into stresses and strain energy density in solder joints and intermetallic layers. The dynamic response of the board is validated by using data from actual board level testing as per JEDEC standard. The solder joint and intermetallic stresses are then related to drop to failure test data to derive a prediction model. The method is then applied to quantify the effect of package design parameters on the drop performance. Factors considered include material set, thickness of various material layers, pad size, and ball size. The same factors were tested in board level drop to further validate the prediction model. Experiments were also conducted to quantify the effects of package ball pad finish on the drop performance through board level testing according to JESD22-B111. The results indicate that the drop performance can be increased by a factor of 4 or more by changing package design and material variables.

Electro Magnetic and Radio Frequency Interference (EMI/RFI) occur in mobile electronics as high functioning devices with multiple operating frequencies are packaged in dense form factors. The most fundamental protection is through metal shielding to produce a "Faraday Cage" (e.g. a metal box) [1], a structure that absorbs or reflects EMI/RFI and boosts performance. A simple and direct means to shield packages is through physical vapor deposition (PVD). Temporary bonding adhesives are used to affix land grid array (LGA) and ball grid array (BGA) packages onto substrates and sent into the PVD line. The properties of the adhesive must be thermally stable, exhibit reduced sidewall creep, prevent under-side deposition (back spill), and be free of residue. Several adhesive solutions exist for EMI shielding processes [2], they exhibit low outgas to 300°C, and are proven to accept package bow and warp of greater than 30um [3]. LGA and BGA packages are affixed using a sufficient adhesion force that is tuned by mixing different resin molecular weights (MW) and activator amounts, all known to have a direct effect on peel force. Adhesion force has been shown to trend with MW of the resin and seemingly supports affixing, while simultaneous adjusting down activator until tearing begins to produce unwanted residue (Fig. 3). Through tuning, solutions are created that allow rapid sealing of small components with topographies exceeding 300um, metal deposition, and rapid satisfactory removal. These temporary bonding adhesives are formulated to achieve a desired modulus and elasticity to accept small packages, allow rapid processing and support high volume manufacturing. Similar work has been conducted to reduce the bow/warp of interposers during stacking with micro-bumped chips. The C4 bumps are encapsulated and protected during thermal exposure [4]. Simple tapes may support low profile LGAs whereas the high standoff in BGAs can create challenges in proper affixing, sealing, and processing. One solution in affixing packages with topographies is based upon the use of rigid etched or "pocket" carriers [5]. Once believed to be a solution for high-density placement of BGAs, there exist challenges in geometric design, glue placement, execution, and recycling (cleanup). Another possible solution is tape that is patterned using CAD-driven laser tooling, producing pockets within the flexible backing. However, the same flexible plastic backing that provides simplicity and ease creates challenges during high-density placement. Placement on flexible tapes can shift to lower density (increased separation), reduction in throughput, and increased cost of ownership (COO). New affixing introductions include laminates and composites that combine the design targets of rigid carriers with the simplicity of tapes [2]. While activity in affixing technologies remains high, PVD systems are also shifting towards small footprints and lower operating temperatures. While low temperatures may be more compatible with epoxy molding compound (EMC), it is uncertain if this will create a main effect and drive down PVD processing temperatures without affect on throughput. This paper will discuss irregularities in package type and shape, adhesive system, adhesion force, and the entire process execution, including PVD systems.

We demonstrate a 32 × 32 path-independent-insertion-loss optical path switch that integrates 1024 thermooptic Mach-Zehnder switches and 961 intersections on a small, 11 × 25 mm2 die. The switch is fabricated on a 300-mm-diameter silicon-on-insulator wafer by a complementary metal-oxide semiconductor-compatible process with advanced ArF immersion lithography. For reliable electrical packaging, the switch chip is flip-chip bonded to a ceramic interposer that arranges the electrodes in a 0.5-mm pitch land grid array. The on-chip loss is measured to be 15.8 ± 1.0 dB, and successful switching is demonstrated for digital-coherent 43-Gb/s QPSK signals. The total crosstalk of the switch is estimated to be less than −20 dB at the center wavelength of 1545 nm. The bandwidth narrowing caused by dimensional errors that arise during fabrication is discussed.

Power Semiconductor packaging has been saddled with five key complaints since the advent of the solid state transistor; (1) packages have too much resistance, (2) they have too much inductance, (3) they take up too much space, (4) they have poor thermal properties that limit heat extraction, and (5) they cost too much. In 2010 enhancement mode gallium nitride power transistors were introduced without a surrounding plastic package. The unique characteristics of the lateral GaN-on-silicon transistors enable the active devices to be protected from the normal environmental abuses without a cumbersome molded plastic package. These chipscale packages, with a Land Grid Array (LGA) format, eliminate the parasitic inductance and resistance of the semiconductor package as well as the space occupied by a conventional package. In this paper we quantify the advantages of chipscale packaging in these five areas of complaint and show how system performance benefits in high frequency DC-DC conversion.