600 results on '"Lacaita, Andrea"'
Search Results
2. A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC
3. Random Telegraph Noise in Flash Memories
4. 10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and −252.4dB FoM
5. 10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion
6. A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering
7. Compact modeling of GIDL-assisted erase in 3-D NAND Flash strings
8. A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS
9. 4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering
10. 4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology
11. Phase Noise Analysis of Periodically ON/OFF Switched Oscillators
12. A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays
13. A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time
14. High Quality Wafer-scale CVD Graphene on Molybdenum Thin Film for Sensing Application
15. A 70.7-dB SNDR 100-kS/s 14-b SAR ADC with attenuation capacitance calibration in 0.35-µm CMOS
16. A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations
17. The race of phase change memories to nanoscale storage and applications
18. A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping
19. Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology
20. Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise
21. A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler
22. Phase change materials in non-volatile storage
23. Impact of Ge–Sb–Te compound engineering on the set operation performance in phase-change memories
24. A $68.6\text{fs}_{\text{rms}}$-Total-integrated-Jitter and $1.5\mu \mathrm{s}-\text{LocKing}$-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching
25. A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter
26. A 72-fs-Total-Integrated-Jitter Two-Core Fractional-$N$ Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner
27. A 6-fJ/conversion-step 200-kSps asynchronous SAR ADC with attenuation capacitor in 130-nm CMOS
28. A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity
29. Integrated Frequency Synthesizers for Wireless Systems
30. Investigation of the RTN amplitude statistics of nanoscale MOS devices by the statistical impedance field method
31. A Generalization of the Groszkowski’s Result in Differential Oscillator Topologies
32. A glitch-corrector circuit for low-spur ADPLLs
33. A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner
34. Reliability impact of chalcogenide-structure relaxation in phase-change memory (PCM) cells-part I: experimental study
35. Reliability impact of chalcogenide-structure relaxation in phase-change memory (PCM) cells-part II: physics-based modeling
36. Study of multilevel programming in programmable metallization cell (PMC) memory
37. Self-accelerated thermal dissolution model for reset programming in unipolar resistive-switching memory (RRAM) devices
38. Filament conduction and reset mechanism in NiO-based resistive-switching memory (RRAM) devices
39. Random Telegraph Noise in 3D NAND Flash Memories
40. High-Density Solid-State Storage: A Long Path to Success
41. A 13.6-69.1GHz 5.6mW Ring-Type Injection-Locked Frequency Divider by Five with >20% Continuous Locking Range and Operation up to 101.6GHz in 28nm CMOS
42. Modeling of programming and read performance in phase-change memories - part II: program disturb and mixed-scaling approach
43. Modeling of programming and read performance in phase-change memories- part I: cell optimization and scaling
44. Statistical model for random telegraph noise in Flash memories
45. Analytical modeling of chalcogenide crystallization for PCM data-retention extrapolation
46. Recovery and drift dynamics of resistance and threshold voltages in phase-change memories
47. Intrinsic data retention in nanoscaled phase-change memories-part II: Statistical analysis and prediction of failure time
48. Intrinsic data retention in nanoscaled phase-change memories-part I: Monte Carlo model for crystallization and percolation
49. Multiphase LC oscillators
50. Matching requirements in LINC transmitters for OFDM signals
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.