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We proposed an in-memory spin coupler based on the 55 nm NOR flash technology to tackle the combinatorial optimization problems. The high-density and cost-effective floating-gate (FG) devices can overcome the capacity limitation in the conventional annealing machines based on static random access memory. In addition, the FG devices featuring high endurance and excellent data retention provide more robust annealing computation as compared to resistive random access memory. A novel complementary read algorithm is further developed to increase the tolerance on threshold voltage (V th) variation by 60%. Demonstrations show that the proposed in-memory spin coupling architecture with high efficiency and scalability has great potential for solving the combinatorial optimizations regardless of the problem size.

We present an in-memory-searching (IMS) architecture which features ultra-high parallel operation. It is based-on high-density, low-power, and low-cost 3D-NAND technology. The IMS unit cell composition, operation algorithm, and array structures are discussed in detail. Reliability concerns including program/read disturbance and retention issues are evaluated and solutions provided. The proposed novel coding scheme can not only provide flexibility to the searching function but also help to improve reliability. An application example on machine learning with k-NN model is demonstrated with good results. The IMS searching efficiency can evolve along with the 3D-NAND technology and is promising to play a key role in the future memory-centric computing systems.

We demonstrate a 3D stackable AND-type Flash memory architecture for high-density and fast-read non-volatile memory solution. The device is based on a gate-all-around (GAA) macaroni thin-body device, with two vertical buried diffusion lines by N+ doped poly plug to connect all memory cells in a parallel way to achieve 3D AND-type array. High sensing current >6uA enables fast Tread ~100ns like NOR Flash, while the structure can enable hundreds of stacked layers eventually. Large transistor ON/OFF ratio of >5 orders, >5V Vt memory window, 100K Endurance, read-disturb free property, and small RTN are demonstrated in our 3D architecture using the BE-MANOS charge-trapping device. This architecture is promising to realize high-density 3D NOR Flash and future storage-class memory (SCM).

A self-reference resistive random-access memory (ReRAM)-based one-transistor, two-ReRAM (1T2R) physically unclonable function (PUF) is proposed to provide a hardware security feature for electrical products in the IoT/5G era. There are four advantages from the proposed structure: (1) a small cell size; (2) intrinsic randomness; (3) no programming circuit; and (4) no data retention concerns. The conduction mechanism, temperature dependency, and read fluctuation of the pristine ReRAM device are studied. An information–address separation scheme is proposed which not only reduces the impact of the read noise and the temperature effect, but also improves system integrity against hardware attacks. The proposed 1T2R PUF unit also has great potential for use as a random seed for linear-feedback shift registers in pseudo random number generators with high unpredictability, good randomness, and a high data rate.

The resistance of transition metal oxide (TMO) ReRAM is a strong function of temperature which resulting in the variation of the memory window and limiting the applications in wide-temperature range or multi-level data storage. This paper investigates the device conduction mechanism and suggests a model to correlate the cell resistance with temperature and the bias condition. The testing results from the 1Mb WOx ReRAM array agree with the model very well. A read scheme that varies the read bias based on the device temperature as well as target sensing level is discussed here. A large and constant memory window is preserved for MLC across a wide temperature range (−40°C to 125°C), suitable for high-reliability applications

The impact of adjacent word-line's pass gate voltage interference on charge-trapping (CT) NAND Flash is extensively studied in this paper. From our previous work with a 38-nm half-pitch BE-SONOS NAND Flash device, we found that the threshold voltage significantly decreases with increasing pass gate voltage during reading. This observation is in contrary to the common belief that the CT NAND devices are immune to interference. In this paper, we further evaluate the pass gate voltage interference on 3-D CT NAND Flash, which is the most promising path for the future NAND Flash industry. Owing to the superior gate control ability in the double-gate architecture, the commonly observed pass gate voltage interference due to pitch scaling is suppressed. Stronger gate control ability also restrains the impact of field penetration in devices with narrow channel width. In 3-D CT NAND Flash, the thinner channel can also provide better gate control ability, which, in turn, results in smaller pass gate voltage interference.

Significant improvements for low power WO x ReRAMs have been achieved through optimizing the oxide quality and managing the sizes and densities of the initial filament. We proposed an operation sequence to evaluate the optimal forming condition which may affect the stability of the following cycling operations. An illustrative model is also provided to explain the correlation of forming current and the filament structure including its dimension and the density of oxygen vacancy.

The 3-D stacking of multiple layers of NAND using thin-film transistor (TFT) devices is widely accepted as the next step in continuing NAND Flash scaling. Low mobility and reliability problems are two well-known concerns regarding TFT devices. However, another important implication of using TFT devices is that the Vt variation induced by randomly distributed grain boundaries degrades the array performance. In this paper, an extensive TCAD simulation was conducted to systematically investigate how grain boundary generated traps affect NAND Flash devices. Minimizing the density of grain boundary traps is crucial for array performance. In addition, optimal gate control ability reduces the impact of grain boundaries. Thus, using double gate architecture in vertical gate 3-D NAND is favorable. Furthermore, when pitch is scaled in the future, device exhibiting smaller channel thickness should be used to increase the gate control.

Lower saturation current flowing through the same cell twice is a major drawback of vertical stack array transistor architecture. A loading effect further reduces the saturation current and causes higher threshold voltage. A simple word line cut process not only doubles the bit density to reduce the bit cost, but also reduces the loading effect. This letter used an assisted gate can to further enhance the saturation current with acceptable cell characteristics. Furthermore, the major parameters that influence the performance of the vertical stack array transistor architecture were studied extensively. An ultra-high density three-dimensional NAND flash architecture can be used in the future NAND flash industry.

We have developed a novel single-gate vertical channel (SGVC) 3D NAND Flash architecture. The device is a single-gate, flat-channel TFT charge-trapping device with ultra-thin body. The ultra-thin body TFT device enables tight initial Vt distribution as well as excellent short-channel effect that is comparable to and sometimes superior than the more prevailing gate-all-around (GAA) macaroni devices of other 3D NAND architectures. Unlike GAA device for which the electric field is a function of channel hole curvature, the flat cell is insensitive to etching CD, thus SGVC device is very tolerable to the non-ideal vertical etching and has shown superb layer-to-layer device uniformity. Even without help from curvature (like in GAA) our SGVC flat cell achieves excellent P/E window of >10V with only modest interferences that can support TLC (3 logic bits per cell) operation. Owing to the double-density in a single WL trench and much more efficient array design with minimal overhead, SGVC architecture offers 2 to 4 times memory density than GAA VC 3D NAND at the same stack layer number.

We developed a simple structure that can enhance the local electric field thus reduce the forming and SET/RESET operation voltage for WOx ReRAM. Si-doped W film is used to further increase the initial resistance and improve the reliability properties. TCAD simulation shows that the field enhanced structure provides an equivalent electrical field that would only be achieved by very small conventional W plug ~ 10nm in size. Thus our novel but simple structure can provide the benefit of deep scaled device without expensive advanced lithography, and with better performance and reliability of larger devices. Furthermore,Si-doping provides an additional knob that allows resistance tuning to optimize the cell and array performance. The 1T1R memory array is well controlled and MLC operation can be reliably achieved by constant current RESET with logic states determined by cumulative RESET pulse duration.

TMO ReRAMs, being built on defect states, are intrinsically subject to variability. In this work, cell to cell variability is studied by applying write shots with different current and voltage for Forming, SET and RESET operation, respectively. We found the keys to eliminate tail bits consist of (1) longer write pulse, (2) higher write current and (3) higher write voltage. In order to optimize the performance of write speed, write power and device reliability, we developed a novel resistance control method using a smart writing algorithm. Compared to the conventional ISPP writing scheme, this smart writing algorithm covers much wider switching condition variability and cell-to-cell variation by controlling both current and voltage for ReRAM operation.

Barrier-engineered charge-trapping NAND Flash (BE-CTNF) devices are extensively examined by theoretical modeling and experimental validation. A general analytical tunneling current equation for multilayer barrier is derived using the Wentzel-Kramers-Brillouin approximation. The rigorously derived analytical form is valid for both electron and hole tunnelings, as well as for any barrier composition. With this, the time evolution (Vt-time) of any BE-CTNF device during programming/erasing can be accurately simulated. The model is validated by experimental results from bandgap-engineered silicon-oxide-nitride-oxide-silicon and various structures using an Al2O3 top-capping layer. Using this model, various structures of BE-CTNF with high-κ tunneling or blocking dielectric are investigated. Finally, the impacts of barrier engineering on incremental-step pulse programming are examined.

A high performance physically unclonable function (PUF) implemented with WO3 resistive random access memory (ReRAM) is presented in this paper. This robust ReRAM-PUF can eliminated bit flipping problem at very high temperature (up to 250 °C) due to plentiful read margin by using initial resistance state and set resistance state. It is also promised 10 years retention at the temperature range of 210 °C. These two stable resistance states enable stable operation at automotive environments from −40 to 125 °C without need of temperature compensation circuit. The high uniqueness of PUF can be achieved by implementing a proposed identification (ID)-generation method. Optimized forming condition can move 50% of the cells to low resistance state and the remaining 50% remain at initial high resistance state. The inter- and intra-PUF evaluations with unlimited separation of hamming distance (HD) are successfully demonstrated even under the corner condition. The number of reproduction was measured to exceed 107 times with 0% bit error rate (BER) at read voltage from 0.4 to 0.7 V.

The physical model for field enhancement (FE) and the edge effects of body-tied FinFET charge-trapping NAND Flash devices are extensively studied in this paper. First, analytical equations are derived to provide insight to the FE effect for FinFET devices, and these analytical results are validated by 3-D TCAD simulation and experimental verification. Next, complicated programming and erasing characteristics and transconductance and subthreshold slope (gm/SS) behaviors are completely explained by the nonuniform injection behavior along various corner edges in FinFET. FE allows high program and erase speed and larger memory window. On the other hand, the edge effect complicates the device DC I-V, as well as programming and erasing characteristics, and these must be taken into account in memory circuit design.

Flash memory application has seen explosive growth in recent years and this trend is likely to continue because new and more demanding applications are constantly added partly due to the need for low power solid-state storage and partly due to rapidly declining prices. Conventional floating gate flash memories, no matter in NOR or NAND architecture, however, face steep challenges. For NOR flash, the junction breakdown and short channel effects have essentially squeezed out the device design space below 45nm node. For NAND flash, the tight spacing, floating gate interference and the need for sufficient gate control (gate coupling ratio) have also ruled out the continuation of the conventional floating gate device below approximately 32nm node. Charge trapping devices, exploiting high-K inter-poly dielectric (IPD) or by innovative tunneling barrier engineering, are proposed to continue scaling flash memories. Eventually, when too few electrons are stored and the logic level retention becomes smeared by statistical fluctuation over the life time of the device, 3-D layering of devices may provide the ultimate solution.

Using a recently developed gate-sensing and channel- sensing (GSCS) transient analysis method, we have studied the detailed charge-trapping behavior for SONOS-type devices. By adding gate sensing to the conventional channel sensing, the two variables (total charge Qtot and mean vertical location x circ) can be solved simultaneously. By using this powerful new tool on several SONOS-type structures, we have studied the charge centroid as well as the capture efficiency of various SONOS devices. Our results clearly prove that electrons are mainly distributed inside the bulk nitride instead of the interfaces between oxide and nitride. For the first time, we show that nitride 7 nm or thicker can essentially capture electrons with 100% efficiency up to a density of Qtot ~1013 cm-2. Structures without top blocking oxide suffer from hole back tunneling and show apparent low electron capture efficiency, which led to confusion in the past. Moreover, multilayer stacks of nitride-trapping layers do not provide more efficient interfacial traps.

For the first time, we can directly investigate the charge transport and intra-nitride behaviors of SONOS-type devices by exploiting the gate-sensing and channel-sensing (GSCS) method. Our results clearly indicate that for electron injection (+FN program), the electron centroid migrates from the bottom toward the nitride center, whereas for hole injection (-FN erase), holes first recombine with the bottom electrons and then gradually move upward. For the electron de-trapping processes under -VG stressing, the trapped electrons de-trap first from the bottom portion of nitride. We also develop a method to distinguish the electron de-trapping and hole injection erasing methods by comparing the erasing current density (J) versus the bottom oxide electric field (E). At short-term high-temperature baking, the electrons move from the top portion toward the bottom portion, and this intra-nitride transport becomes more significant for a thicker nitride. On the other hand, after long-term baking, the charge loss mainly comes from the bottom portion of nitride.

Several novel negative Fowler-Nordheim (FN) operations for hot-hole-erased SONOS-type devices are studied. By using p+-poly gate instead of n+-poly gate, gate injection is greatly suppressed, and the device shows self-convergent VT after -FN. By using this self-converging property, -FN operation can be applied to both erased and programmed states in various sequences/algorithms. In the erase state, a short -FN channel erase called "soft erase" can be performed after hot-hole sector erase. It provides a strong electrical annealing effect to recover the hot-hole damages. On the other hand, "refill" is a shorter version of the soft erase method that expels shallow-level electrons and replaces them with deeper level ones. A spectrum blue shift model is proposed to explain the shifting of the trapped-electron energy distribution to a bluer (deeper) spectrum during refill. Various soft erase and refill conditions are examined to study the charge loss mechanism. The experimental results exhibit superior retention by combining the suitable soft erase and refill conditions. We find that the vertical charge losses measured by VG -accelerated retention test at room temperature (25 degC) are highly correlated to that measured at high temperature baking (150 degC), and a reliability model is proposed to explain these mechanisms.

We have proposed an approach to grow ultra-thin oxynitride film with high nitrogen concentration (≈13 at%) on the top and low interface state density ( D it =2×10 10 cm −2 eV −1 ). In general, a high-nitrogen oxynitride film provides a rather reliable and higher dielectric constant. In this method, oxynitride growth included three process stages—chemical oxide growth, nitridation and subsequent dry oxidation. By this technique, the films demonstrate the desirable nitrogen concentration profile and excellent properties in terms of low D it , low leakage current, and high endurance in stressing. Better controllability in film thickness may be achieved because the oxidation rate of the nitride-chemical oxide is much smaller than that of the conventional oxide. Most importantly, this process is simple and fully compatible with current process technology.

A novel channel-program and erase method is presented to replace the FN tunneling operation for SONOS cells in NAND architecture for the first time [Hsu TH, Wu JY, King YC, Lue HT, Shih YH, Lai EK, et al. A novel channel-program–erase technique with substrate transient hot carrier injection for SONOS memory application. In: Tech digest 2006 European solid-state device research conference (ESSDERC); 2006. p. 222–5], [1] . The proposed operation utilizes substrate transient hot electron (STHE) injection and substrate transient hot-hole (STHH) injection for programming and erasing, respectively. Gate bias polarity serves to control whether hot electrons or hot holes are injected into the nitride storage layer. More efficient program and erase operations are achieved compared to the conventional Fowler–Nordheim (FN) tunneling method. The new technique operates at lower programming voltages and with shorter duration pulses, thus increases the programming throughput. Moreover, good program/erase disturb immunity, cycling endurance and data retention are demonstrated.

The gate-sensing and channel-sensing transient analysis method is studied in detail. This method introduces an additional gate-sensing capacitor to be compared with the conventional channel-sensing one. Sensing in both modes provides two equations that are suitable to solve for two variables-the charge density (Q ) and the average charge vertical location (x ). In this paper, the principle of this method is discussed in detail. Several factors that affect the measurement accuracy are also analyzed. The power of this method is demonstrated by program/erase cycling and data retention tests. This method is indeed a powerful tool for detailed understanding of trapping dynamics.

This paper studies hydrogen diffusion in nitride-based Flash memory. Distorted capacitance-voltage ( C-V) curves were obtained when the programmed devices were baked in an environment of hydrogen at a temperature of 400 degC. Hydrogen may invade the edge of the device. The effectively trapped electrons were eliminated by the invading hydrogen. Elimination is responsible for a nonuniform distribution of charges in capacitors and contributes to the distortion of C-V curves. The distorted C-V curve can be accurately simulated by superposing only two subcapacitors with appropriate area ratios. The hydrogen-invasion depth can also be calculated from the ratio of the subcapacitances. The hydrogen diffusion length decreased as the number of programmed electrons increased. Hydrogen invasion is modeled as a diffusion-limited process

The band-to-band tunneling hot-electron (BBHE) programming characteristics of the 2 bit/cell p-channel bandgap-engineered silicon-oxide-nitride-oxide-semiconductor (SONOS) (H. T. Lue, et al., in IEDM Tech. Diag., p. 331) device are extensively studied. The lateral BBHE profile is extracted by fitting the experimental current-voltage (I-V) characteristics with 2-D simulation. The results suggest that, after BBHE injection, the local channel potential barrier is reduced, which, in turn, raises the Vt of the p-channel device. The 2 bit/cell operation methods and second-bit effect (2 bit interaction) are examined. The effects of channel-length scaling, junction profile, and effective oxide thickness of the gate stack are also addressed

The sintered Co 1− x O ceramics with or without 20 mol% MgO solid solution in the rock salt type structure were annealed in the temperature range of 400–1500 °C in air for surface morphology development study. Electron microscopic observations indicated the MgO component considerably suppressed the thermal etching and the nucleation of the Co-rich spinel as expected. Surprisingly, prolonged annealing at 1500 °C caused anisotropic development of the {1 1 1}/{1 0 0}-faceted etch pits/hillocks from the cubic crystal system, which can be rationalized by the predominant exposure of 〈1 1 0〉 oriented dislocations on the {1 1 1} surfaces. Meanwhile, sublimation–condensation at this temperature caused cube-like Co 1− x O crystallites to deposit preferentially on the (1 0 0) surface following parallel or 45° off crystallographic relationship via Brownian motion of the crystallites.

Double-trapping bandgap engineered SONOS (DT BE-SONOS) [1] was proposed to provide both fast erase speed and deep erase by means of a second nitride trapping layer and an additional blocking oxide on top of BE-SONOS. Although this provides excellent erase performance but the additional layers increase the EOT and subsequently the erase voltage, thus it is desirable to minimize their impact. This work investigates exhaustively the effect of thinning down the blocking layers. Since the ISPP and high temperature retention charge loss are mainly dominated by the ONO thickness of BE-SONOS below the blocking layers, reducing the blocking layer thickness has only minor impact on ISPP and retention. Moreover, erase saturation is determined by the dynamic balance of channel hole injection and gate electron injection. Experimental data show that reducing the thickness of the oxide between two trapping layers has little impact on erase saturation once the gate injected electrons are efficiently suppressed by the top most oxide. We have also investigated retention improvement by various oxides. By using HQ-SiO2 to replace the top tunnel ONO the trapped electron out-tunneling is reduced. Thus retention may be improved without increasing the effective oxide thickness.

The charge trapping behavior of SiON thin films using various processing methods are studied. The transient analysis method [Lue HT, Shih YH, Hsieh KY, Liu R, Lu CY. A transient analysis method to characterize the trap vertical location in nitride-trapping devices. IEEE Electron Dev Lett 2004;25:816–8] reveals that SiON has a higher capture efficiency than SiN so that gate injected electrons are mostly stopped at the interface between top oxide and trapping layer, independent of whether the SiON is formed by thermal oxidation of SiN or direct LPCVD deposition. On the other hand, the excess Si piling-up behavior is observed during oxidation process over SiN, and it shows correlation with the native negative charge. Therefore, the effect of excess Si piling-up and SiON trapping layer are discriminated for the first time.

We have proposed an approach for growing robust ultrathin oxynitride using conventional thermal processes with the capability of preventing boron penetration. In this method, we obtain oxynitride with high nitrogen concentration (≈13 at. %) on the top and low interface state density (Dit=2×1010 cm-2 eV-1). The films demonstrate excellent properties in terms of low Dit, low leakage current, high endurance in stressing and superior boron diffusion blocking behavior. This method does not involve any additional capital equipment [such as decoupled plasma nitridation (DPN) or remote plasma nitridation (RPN)] or gas (NO or N2O). In addition, it obtains high-quality oxynitride film with low thermal budget. Most importantly, this process is simple and fully compatible with current process technology. It would be important and interesting for process engineers engaged in the field of gate dielectrics. It is suitable for the next generation of ULSI technology.

The reverse read method and second-bit effect of the 2-bit/cell nitride-trapping device are comprehensively studied by a quasi-two-dimensional (2-D) model. Based on this model, analytical equations are derived to simulate the surface potential of the device with locally injected electrons. This model indicates that the reverse read method exploits the local drain-induced barrier lowering (DIBL) effect that reduces the potential barrier produced by the locally injected electrons. The experimental results of the two-region behavior of second-bit effect can be well explained and simulated by this analytical model. Two-dimensional numerical calculations are also carried out to verify these analytical equations. The impact of short-channel effect on the second-bit effect is also examined.

Comparing to conventional short-pulse (

A TiO x /TiO x N y resistive random access memory (ReRAM) with a sidewall bottom electrode (BE) is demonstrated for the first time. Several interesting characteristics that are very desirable for high reliability memory applications are observed: (1) a stable RESET and SET resistance switching window even without write verification, (2) good 250 °C data retention, (3) ReRAM switching instability after cycling is monitored and corrected, resulting in good reliability, and (4) using only complementary metal oxide semiconductor (CMOS) familiar materials and processes, thus very manufacture-friendly. The thickness and quality of TiO x and TiO x N y are well controlled by plasma oxidation, and a large resistance switching window (>10×), a low operation voltage, and good reliability are realized.

A novel CMOS compatible photo oxidation (PO) technology is proposed in this paper which, by only using standard DUV photo lithography process, demonstrates a strong oxidation capability to form CMOS compatible WOx. The oxidation occurs through catalytic chemical reaction during the post exposure baking (PEB) process. Based on this unique PO process, a high performance forming free 1T-1R WOx ReRAM is demonstrated. Furthermore, this PO WOx ReRAM can withstand high temperature baking (@ 250°C) for 30 min thus is suitable for embedded systems that require pre-coding, and automotive and other industrial applications.

The transient behavior of SONOS-type devices was investigated for the first time using pulse- IV technique. Three kinds of SONOS devices are studied: SONS (without top oxide), SONoS (with a thin top oxide), and SoNOS (with a thin bottom oxide). Devices with or without a thin tunnel oxide were able to provide very fast charge injection/detrapping, but their charge-transient behavior cannot be accurately monitored by conventional DC-IV method. By using specific pulse-IV setup for memory, we can measure the drain current response immediately after programming and erasing, as well as the fast charge relaxation under various reliability tests. The program and erase transient behavior shows that all devices are easily programmed and erased within 1 mus at low gate voltages (

The erase characteristics and mechanism of metal- Al2O3-nitride-oxide-silicon (MANOS) devices are extensively studied. We use transient analysis to transform the erase curve (VFB - time) into a J-E curve (J = transient current, E = field in the tunnel oxide) in order to understand the underlying physics. The measured erase current of MANOS is three orders of magnitude higher than that can be theoretically provided by substrate hole current. In addition, the erase current is very sensitive to the Al2O3 processing condition - also inconsistent with substrate hole injection model. Thus, we propose that MANOS erase occurs through an electron detrapping mechanism. We have further carried out a refill test and its results support the detrapping model. Our results suggest that the interfacial layer between Al2O3 and nitride is a key process that dominates the erase mechanism of MANOS.

A body-tied FinFET bandgap engineered (BE)-silicon-oxide-nitride-oxide-silicon (SONOS) nand Flash device is successfully demonstrated for the first time. BE-SONOS device with a BE oxide-nitride-oxide barrier is integrated in the FinFET structure with a 30-nm fin width. FinFET BE-SONOS can overcome the unsolvable tradeoff between retention and erase speed of the conventional SONOS. Compared with the current floating-gate Flash devices, FinFET BE-SONOS provides both retention and erase-speed performance, while eliminating the scaling limitations and is, thus, an important candidate for further scaling of nand Flash

A new method to probe the trap vertical location for nitride-trapping devices is proposed. This method requires only measuring the time dependence of gate injection at various gate voltages on a single wafer. The transient current (J) and the instantaneous electric field (E) across the top oxide can be directly obtained based on various cases of trap location. Comparisons can be made to check which case has the best consistency for the J versus E behaviors. The only assumption in this method is that the transient current J and the instantaneous E field should follow a consistent tunneling relationship at different gate voltages. The experimental results show unequivocally that electrons are trapped at the interface between top oxide and nitride for oxide grown by thermal conversion. However, for the direct-deposited top oxide the electrons are more spatially distributed in the nitride. This method is a simple and convincing tool to detect the nitride trap vertical location.

The nonvolatile memory characteristics of metal-oxide-semiconductor structures containing Pt nanocrystals in SiO2 gate oxide were studied. The Pt nanocrystals of 2–3nm in diameter were self-assembled from reduction of an ultrathin PtOx layer embedded in the SiO2 by vacuum annealing at 425°C. A large hysteresis loop was found in the capacitance–voltage (C–V) relation indicating this significant memory effect. However, two different charge storage mechanisms were found for the Pt nanocrystals in devices with different tunnel oxide thickness. A counterclockwise C–V hysteresis was induced from substrate injection for the devices made with a thin tunnel oxide layer 2.5–5.0nm thick. Contrast, a clockwise behavior attributed to the electron transfer from charged defects in the gate oxide was found for the devices having a tunnel oxide layer 7.5nm thick. The relatively stable memory characteristics of Pt nanocrystals resulted from substrate injection were also demonstrated.

This paper provides an overview of 3D NAND Flash memory architecture and a comprehensive study on various array decoding methods of vertical gate (VG) NAND Flash. A certain memory density may be achieved by any array architecture but with different numbers of stacking layers. A smaller pitch allows the achieving of high density at reasonable number of stacked memory layers (≤ 32) and thus potentially offers lower cost. VG NAND has good pitch scalability thus is very attractive. On the other hand, it is more difficult to decode the bit line in a VG architecture, thus decoding innovations are required for a compact array architecture design. This paper provides a systematic comparison of four different decoding methods of VG NAND. Performance of the TFT BE-SONOS device used in 3D VG NAND is also addressed.