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In this article, the mechanism of stability in amorphous indium-gallium-zinc oxide ( ${a}$ -IGZO) thin-film transistors (TFTs) with a natural length of $\sim $ 8 nm was investigated from the perspective of hafnium oxide (HfO $_{{2}}{)}$ gate dielectric point defects. The point defects in HfO2 responded to external stresses such as electric field ( ${E}{)}$ and temperature. In particular, oxygen vacancies and the positively charged defects caused an abnormal negative shift in threshold voltage ( ${V}_{\text {TH}}{)}$ under positive gate bias temperature stress (PBTS). Therefore, reducing the positively charged defects was important to eliminate the abnormal behavior. Inserting a 0.7-nm-thick ultrathin SiO2 interlayer between ${a}$ -IGZO and optimized HfO2 further improved device performance including stability. Consequently, the resultant ${a}$ -IGZO TFT exhibited promising device performance with $\mu _{\text {FE}}$ of 22.3 ±0.5 cm $^{{2}}\text{V}^{-{1}}\text{s}^{-{1}}$ , subthreshold swing (SS) of 64 ±0.5 mVdec $^{-{1}}$ , hysteresis of 4 mV, and $\Delta {V}_{\text {TH}}$ of 124 mV under harsh PBTS with ${E}$ of 4 MV/cm at 80 °C for 3600 s.

We report the effects of sputter‐based multi‐stack interlayer on the electrical contact properties of a‐IGZO TFTs. The a‐IGZO TFTs with a multi‐stack interlayer of TiN and IGTO showed remarkable outcomes, including the lowest specific contact resistivity (ρC) and the highest field‐effect mobility (μFET). This research suggests a highly effective approach to reduce the contact resistivity of oxide semiconductors by nearly two orders magnitude.

The high‐performance amorphous In‐Ga‐Sn‐O (a‐IGTO) thin‐film transistors (TFTs) was fabricated with plasma‐enhanced atomic layer deposition (PEALD)‐derived Al2O3high‐k gate dielectric at a maximum processing temperature of 150 °C. During the deposition of Al2O3dielectric on a‐IGTO films, the hydrogen (H) and excess oxygen (Oi) defects from the Al2O3act significant role on TFTs operation. The amounts of H and Oican be controlled by adjusting oxygen plasma density in radio‐frequency (rf) of PEALD. The optimized a‐IGTO TFT exhibit high‐performance electrical properties with field‐effect mobility (μFE) of 58.8 cm2/Vs, subthreshold gate swing (SS) of 0.12 V/decade, threshold voltage (VTH) of 0.5 V.

In this work, high-performance amorphous In0.75Ga0.23Sn0.02O (a-IGTO) transistors with an atomic layer-deposited Al2O3dielectric layer were fabricated at a maximum processing temperature of 150 °C. Hydrogen (H) and excess oxygen (Oi) in the Al2O3film, which was controlled by adjusting the oxygen radical density (PO2: flow rate of O2/[Ar+O2]) in the radio-frequency (rf) plasma during ALD growth of Al2O3, significantly affected the performance and stability of the resulting IGTO transistors. The concentrations of H and Oiin Al2O3/IGTO stacks according to PO2were characterized by secondary ion mass spectroscopy, X-ray photoelectron spectroscopy, hard X-ray photoemission spectroscopy, and thermal desorption spectroscopy. The high concentration of H at a low PO2of 2.5% caused heavy electron doping in the underlying IGTO during thermal annealing at 150 °C, leading to a conductive behavior in the resulting transistor without modulation capability. In contrast, a high PO2condition of 20% introduced O2molecules (or Oi) into the Al2O3film, which negatively impacted the carrier mobility and caused anomalous photo-bias instability in the IGTO transistor. Through in-depth understanding of how to manipulate H and Oiin Al2O3by controlling the PO2, we fabricated high-performance IGTO transistors with a high field-effect mobility (μFE) of 58.8 cm2/Vs, subthreshold gate swing (SS) of 0.12 V/decade, threshold voltage (VTH) of 0.5 V, and ION/OFFratio of ∼109even at the maximum processing temperature of 150 °C. Simultaneously, the optimized devices were resistant to exposure to external positive gate bias stress (PBS) and negative bias stress (NBS) for 3600 s, where the VTHshifts for exposure to PBS and NBS for this duration were 0.1 V and −0.15 V, respectively.

Development of high‐performance p‐channel thin‐film transistors (TFTs) can be an essential building block for next‐generation display technologies which require a great power efficiency. While an n‐channel InGaZnO TFT has been practically demonstrated, the counterparts are still challenging because of their ionic bonding nature. Here we report high‐performance p‐channel hexagonal tellurium (Te) TFT which exhibits outstanding device performances with a field‐effect mobility of 21.2 cm2/Vs, a current modulation ratio of 2.3 × 105, a subthreshold swing of 0.2 V/dec, and a threshold voltage of ‐0.3 V. This study shows a strong potential of p‐channel Te TFT for next‐generation display applications.

Capacitor structures utilized in modern dynamic random access memory (DRAM) cells require the conformal growth of high-kfilms on electrode materials. In this context, the atomic layer deposition (ALD) of rutile-phase TiO2on nearly lattice-matched substrates such as RuO2has been extensively explored. It is typically desired to grow such insulating films at high temperatures to ensure low defect concentrations and high crystallinity. However, with increasing growth temperature, it is also crucial to consider the aggravated effect of interface reactions that could potentially hinder final device performance. Here, we report the high-temperature ALD growth of TiO2on RuO2substrates using the heteroleptic precursor trimethoxy(pentamethylcyclopentadienyl)titanium ((CpMe5)Ti(OMe)3) and O3. High-quality, rutile-phase TiO2films with large dielectric constants of ∼100 could be grown at temperatures exceeding 300 °C. When the growth temperature reaches 330 °C, we find that an anomalous RuO2reduction reaction occurs due to interactions between the substrate and Ti precursor. The reduced Ru is transformed into volatile RuO4during the subsequent O3injection steps, resulting in partial etching of the substrate. Simple RuO2/TiO2/RuO2capacitor devices fabricated from optimized films demonstrate excellent dielectric performance with an equivalent oxide thickness (EOT) of 0.5 nm at leakage current densities of less than 10–7A/cm2. A further reduction of EOT to 0.4 nm could be achieved by implementing a single cycle of Al doping to the TiO2films, surpassing the benchmark values proposed for next-generation DRAM capacitors by a safe margin. Our findings clearly showcase the benefits of high-temperature ALD in the semiconductor technology, as well as providing guidelines for the interpretation of the convoluted interface reactions tied to its implementation.

In general, the electronic and optical properties of oxide films can significantly benefit from highly textured crystallinity. However, oxide films grown by atomic layer deposition (ALD), a powerful technique for the synthesis of high-quality, nanoscale thin films, usually exhibit amorphous or randomly oriented polycrystalline phases. Here, we demonstrate the growth of highly textured rutile phase ALD TiO2films through rational substrate design. Both a- and c-axis preferentially oriented TiO2films are obtained by varying the lattice parameters of the initial ALD growth surface. Under optimized conditions, we find that it is possible to deposit high-quality, c-axis preferentially aligned TiO2films with a bulk dielectric constant approaching 185, rivaling the single crystal limit. These films display a remarkably high dielectric constant of 117 despite thin thickness of 5.2 nm. Moreover, the addition of a single doping sequence of Al2O3successfully suppresses leakage currents to levels compatible with modern dynamic random access memory cells, all the while maintaining the high bulk dielectric constant of 137. These results clearly highlight the prospect of utilizing crystal orientation engineering in ALD thin films for emerging semiconductor devices.

Development of p‐type inorganic semiconductors for high performance thin‐film transistor (TFT) can be an essential ingredient for next‐generation display applications which requires a low power consumption. However, the conventional p‐type oxide semiconductors exhibit the poor electrical characteristics, which is mainly attributed to the inefficient conduction path formation from oxygen 2p orbitals. Here, we report a new p‐type material, tin oxyselenide (SnSeO) semiconductors for high performance p‐channel TFTs. The SnSeO was designed with the concept that valence band maximum (VBM), hole conduction path, becomes delocalized by hybridizing selenium 4p and tin 5s orbitals. The SnSe0.56O0.44thin‐film exhibited the highest Hall mobility of 15.0 cm2V‐1s‐1and hole carrier density of 1.2 x 1017cm‐3. In addition, the SnSe0.56O0.44TFT showed the excellent field‐effect mobility of 5.9 cm2V‐1s‐1and current modulation ratio of 3.0 x 102. This high mobility is explained by the low hole effective mass through valence band engineering, which was confirmed by density functional theory calculation. Moreover, complementary metal oxide semiconductor (CMOS) inverter using the p‐type SnSe0.56O0.44with n‐type IGZO showed excellent intrinsic gain of 15.7. This anion hybridization can provide a facile route to the realization of a high performance p‐channel TFT for next‐generation displays.

High off‐current in p‐type SnO thin‐film transistors (TFTs) limits the application to active matrix devices for next generation display industry. Here, we propose a new approach to suppress the off‐current using metal‐interlayer‐semiconductor (MIS) contact structure. The MIS contact structure makes Fermi‐level pinning (FLP) alleviated through an ultrathin interlayer (IL) which prevents metal‐induced gap states (MIGSs), the origin of severe FLP, and thereby Schottky barrier height (SBH) can be modulated. With the electron SBH (eSBH) increasing, the electron injection from drain electrode into the SnO channel is suppressed, which results in the reduction of the off‐current from 5.1 × 10‐8A to 2.4 × 10‐9A and the enhancement of the ION/OFFfrom 2.7 × 102to 2.8 × 103compared with the conventional metal‐semiconductor (MS) contacted TFTs. This work shows not only the enhancement in device performance but also a new perspective on the origin of off‐current in the p‐type SnO TFTs.